coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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1236 discussions

New patch to review for coreboot: 46427b8 Makefile: Test clang -std=c11 compat to be ready for LLVM3.7
by Edward O'Callaghan 15 Jan '15

15 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8231 -gerrit commit 46427b80079ed4f909c18d163fb1bf2fae2a97a3 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jan 16 03:37:21 2015 +1100 Makefile: Test clang -std=c11 compat to be ready for LLVM3.7 Change-Id: Ic08c65fc9bc0b5daef6c6561ff72f941db73c3db Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index 8fdd5d3..3b6dcd6 100644 --- a/Makefile +++ b/Makefile @@ -118,6 +118,8 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # NOTE: clang puts compiler-rt under lib/linux/libclang_rt.builtins-i386.a # this means the triple is i386-linux-elf instead of i386-none-elf CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 +# Test C11 compat for LLVM 3.7 +CFLAGS_x86_32 += -std=c11 # Tone down some clang warnings CFLAGS_x86_32 += -Wno-unused-function -Wno-tautological-compare -Wno-shift-overflow CC_x86_32:=clang

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Patch set updated for coreboot: eec10db Makefile: clang - ramp up some more warnings
by Edward O'Callaghan 15 Jan '15

15 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8197 -gerrit commit eec10db3324182a4b029fce027987ab98dfc7364 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 13 04:15:29 2015 +1100 Makefile: clang - ramp up some more warnings Back out '-Wno-unused-variable'. Change-Id: Icd15b03d3a41f4933c9ae0a4c497ccadcccbefb5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 017ca47..8fdd5d3 100644 --- a/Makefile +++ b/Makefile @@ -119,7 +119,7 @@ ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) # this means the triple is i386-linux-elf instead of i386-none-elf CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-linux-elf -m32 # Tone down some clang warnings -CFLAGS_x86_32 += -Wno-unused-variable -Wno-unused-function -Wno-tautological-compare -Wno-shift-overflow +CFLAGS_x86_32 += -Wno-unused-function -Wno-tautological-compare -Wno-shift-overflow CC_x86_32:=clang HOSTCC := clang

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New patch to review for coreboot: 5f27d98 3rdparty: Update to latest commit in blobs repository
by Dave Frodin 15 Jan '15

15 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8230 -gerrit commit 5f27d98334570214b3e9c127c9b94709d456be5a Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jan 15 09:18:39 2015 -0700 3rdparty: Update to latest commit in blobs repository 'blobs' now contains the update for the Mullins binaryPI. Change-Id: Ife5dc73a856697c23a6d6b27fd5280f972992631 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- 3rdparty | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index a8b0c52..571952f 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit a8b0c52850495c30dfa1cd8cc2c679a6ba4e18ac +Subproject commit 571952f6d41f415b9e5630f6957e6f9a775df0cd

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Patch merged into coreboot/master: 660ec7c drivers/i2c/w83795: Fix tautology from wrong return type
by gerrit＠coreboot.org 15 Jan '15

15 Jan '15

the following patch was just integrated into master: commit 660ec7cfdf0b48c135ada6cd67af25d66404d3ba Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 14 02:14:21 2015 +1100 drivers/i2c/w83795: Fix tautology from wrong return type The correct type-signature of 'do_smbus_write_byte' is: int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) and so storing the return type in a 'u32' is inappropriate, leading to a tautological compare of 'ret < 0' and 'err < 0'. Change-Id: I65486df7156c70af84fa00c336142d9a45998620 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8209 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/8209 for details. -gerrit

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New patch to review for coreboot: a5b979b asrock/e350m1: Fix PCIe slot for x4 cards
by Kyösti Mälkki 15 Jan '15

15 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8229 -gerrit commit a5b979b61699b1377fedd953e0941cc4190821a5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 15 17:42:53 2015 +0200 asrock/e350m1: Fix PCIe slot for x4 cards Configuration for GNB GPP was incorrect, only PCIe x1 cards worked. Change-Id: I369bf6382080e6034ff138ac664c76b03280ca69 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index 76e5ade..a704c4b 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -58,29 +58,9 @@ PCIe_PORT_DESCRIPTOR PortList [] = { // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) }, - #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) - }, - #endif // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array

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Patch merged into coreboot/master: b0a00c9 mainboard/tyan/s2882/irq_tables.c: Remove dead code under #if 0
by gerrit＠coreboot.org 15 Jan '15

15 Jan '15

the following patch was just integrated into master: commit b0a00c996d8d60cf207156f0a5176310dc4d7403 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 13 05:47:41 2015 +1100 mainboard/tyan/s2882/irq_tables.c: Remove dead code under #if 0 Silence unused variable warning. Change-Id: I2671e0843a60e5bd857b233a45ea68715461f187 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8202 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/8202 for details. -gerrit

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Patch set updated for coreboot: 34d00c2 device/oprom/realmode/x86: Fix memory corruption
by Paul Menzel 15 Jan '15

15 Jan '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8227 -gerrit commit 34d00c203579fe7de4d1f0268367f68b4adf0c26 Author: Zhuo-Hao Lee <zhuo-hao.lee(a)intel.com> Date: Wed Dec 24 11:13:34 2014 +0800 device/oprom/realmode/x86: Fix memory corruption The length of the memcpy is incorrect and this will cause the destination buffer to corrupt the following 2 bytes of data. BUG=none BRANCH=All TEST=build and boot on rambi, system boot up without error Change-Id: I96adf2555b01aa35bb38a2e0f221fc2b2e87a41b Signed-off-by: Zhuo-Hao Lee <zhuo-hao.lee(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/237510 Reviewed-by: Ryan Lin <ryan.lin(a)intel.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/device/oprom/realmode/x86.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index fc3c40c..07eb26c 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -233,7 +233,8 @@ static u8 vbe_get_mode_info(vbe_mode_info_t * mi) u16 buffer_adr = ((unsigned long)buffer) & 0xffff; realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode, 0x0000, buffer_seg, buffer_adr); - memcpy(mi->mode_info_block, buffer, sizeof(vbe_mode_info_t)); + memcpy(mi->mode_info_block, buffer, + FIELD_SIZEOF(vbe_mode_info_t, mode_info_block)); mode_info_valid = 1; return 0; }

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New patch to review for coreboot: 692605d device/oprom/realmode/x86: Fix programming error causing memory corruption
by Paul Menzel 14 Jan '15

14 Jan '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8227 -gerrit commit 692605d8131ce02a7adebe7feb9a867fca82608b Author: Zhuo-Hao Lee <zhuo-hao.lee(a)intel.com> Date: Wed Dec 24 11:13:34 2014 +0800 device/oprom/realmode/x86: Fix programming error causing memory corruption The length of the memcpy is incorrect and this will cause the destination buffer to corrupt the following 2-byte data. BUG=none BRANCH=All TEST=build and boot on rambi, system boot up without error Change-Id: I96adf2555b01aa35bb38a2e0f221fc2b2e87a41b Signed-off-by: Zhuo-Hao Lee <zhuo-hao.lee(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/237510 Reviewed-by: Ryan Lin <ryan.lin(a)intel.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/device/oprom/realmode/x86.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index fc3c40c..07eb26c 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -233,7 +233,8 @@ static u8 vbe_get_mode_info(vbe_mode_info_t * mi) u16 buffer_adr = ((unsigned long)buffer) & 0xffff; realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000, mi->video_mode, 0x0000, buffer_seg, buffer_adr); - memcpy(mi->mode_info_block, buffer, sizeof(vbe_mode_info_t)); + memcpy(mi->mode_info_block, buffer, + FIELD_SIZEOF(vbe_mode_info_t, mode_info_block)); mode_info_valid = 1; return 0; }

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New patch to review for coreboot: b9b29ef include/stdlib.h: Add macro `FIELD_SIZEOF(t, f)`
by Paul Menzel 14 Jan '15

14 Jan '15

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8226 -gerrit commit b9b29efcc10aeb3bbcc1db38cb8b71985b6b4319 Author: Zhuo-Hao Lee <zhuo-hao.lee(a)intel.com> Date: Wed Jan 14 23:28:52 2015 +0100 include/stdlib.h: Add macro `FIELD_SIZEOF(t, f)` Change-Id: I6e86025d3bbb0cd2ed82bc42b798d331046beb15 Signed-off-by: Zhuo-Hao Lee <zhuo-hao.lee(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/237510 Reviewed-by: Ryan Lin <ryan.lin(a)intel.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/include/stdlib.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 2fc6805..88456be 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -4,6 +4,7 @@ #include <stddef.h> #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#define FIELD_SIZEOF(t, f) (sizeof(((t *)0)->f)) #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) #define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))

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Patch set updated for coreboot: c8d5102 vboot2: fix up "add verstage"
by Stefan Reinauer 14 Jan '15

14 Jan '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8225 -gerrit commit c8d51027d0d932b88468bcbeadded374a6e104b6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jan 14 11:07:49 2015 -0800 vboot2: fix up "add verstage" Architecture support was incomplete, which lead to toolchain.inc choking on some of its implicit expectations from Kconfig. Fix config variable usage in tegra124 bootblock and remove extra whitespace. Change-Id: I0a504f01d10302fbf2bd1bbc82cfd047ed02157f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/arm/Kconfig | 4 ++-- src/arch/arm/Makefile.inc | 2 +- src/arch/arm64/Kconfig | 4 ++++ src/arch/arm64/armv8/Kconfig | 3 +++ src/arch/riscv/Kconfig | 4 ++++ src/arch/x86/Kconfig | 4 ++++ src/soc/nvidia/tegra124/bootblock.c | 12 ++++-------- 7 files changed, 22 insertions(+), 11 deletions(-) diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index f73ad27..1c3a339 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -4,8 +4,8 @@ config ARCH_BOOTBLOCK_ARM select ARCH_ARM config ARCH_VERSTAGE_ARM - bool - default n + bool + default n config ARCH_ROMSTAGE_ARM bool diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index ba7fb60..6f65a71 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -61,7 +61,7 @@ bootblock-y += memcpy.S bootblock-y += memmove.S bootblock-y += div0.c -$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $$(VERSTAGE_LIB) +$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $$(VERSTAGE_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm/bootblock.ld diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index dc0e332..186dd44 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -3,6 +3,10 @@ config ARCH_BOOTBLOCK_ARM64 default n select ARCH_ARM64 +config ARCH_VERSTAGE_ARM64 + bool + default n + config ARCH_ROMSTAGE_ARM64 bool default n diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index fc2e668..5840e81 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -1,6 +1,9 @@ config ARCH_BOOTBLOCK_ARM_V8_64 def_bool n select ARCH_BOOTBLOCK_ARM64 +config ARCH_VERSTAGE_ARM_V8_64 + def_bool n + select ARCH_VERSTAGE_ARM64 config ARCH_ROMSTAGE_ARM_V8_64 def_bool n select ARCH_ROMSTAGE_ARM64 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 120203d..f2dc41e 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -3,6 +3,10 @@ config ARCH_BOOTBLOCK_RISCV default n select ARCH_RISCV +config ARCH_VERSTAGE_RISCV + bool + default n + config ARCH_ROMSTAGE_RISCV bool default n diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 56d8f88..edbc67a 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -3,6 +3,10 @@ config ARCH_BOOTBLOCK_X86_32 default n select ARCH_X86 +config ARCH_VERSTAGE_X86_32 + bool + default n + config ARCH_ROMSTAGE_X86_32 bool default n diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 0456b48..5f1e850 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -25,10 +25,7 @@ #include <soc/nvidia/tegra/apbmisc.h> #include "pinmux.h" #include "power.h" - -#if CONFIG_VBOOT2_VERIFY_FIRMWARE #include "verstage.h" -#endif void main(void) { @@ -75,11 +72,10 @@ void main(void) power_enable_cpu_rail(); power_ungate_cpu(); -#if CONFIG_VBOOT2_VERIFY_FIRMWARE - entry = (void *)verstage_vboot_main; -#else - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); -#endif + if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) + entry = (void *)verstage_vboot_main; + else + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); if (entry) clock_cpu0_config_and_reset(entry);

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coreboot-gerrit January 2015