coreboot-gerrit January 2015

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Patch set updated for coreboot: 8068ad8 vboot2: implement select_firmware for pre-romstage verification
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8160 -gerrit commit 8068ad80531dbd40a33fd75ebaa2a20d24761b98 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Thu Jun 19 19:16:24 2014 -0700 vboot2: implement select_firmware for pre-romstage verification This patch has a basic structure of vboot2 integration. It supports only Nyans, which have bootblock architecture and romstage architecture are compatible from linker's perspective. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa Original-Reviewed-on: https://chromium-review.googlesource.com/204522 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001 --- src/arch/arm/Makefile.inc | 12 + src/arch/arm/armv7/Makefile.inc | 12 + src/arch/arm/bootblock.ld | 1 + src/arch/arm/libgcc/Makefile.inc | 4 + src/console/Makefile.inc | 4 + src/include/reset.h | 1 + src/lib/Makefile.inc | 6 + src/mainboard/google/nyan_blaze/Makefile.inc | 2 + src/mainboard/google/nyan_blaze/romstage.c | 4 + src/soc/nvidia/tegra124/Kconfig | 11 + src/soc/nvidia/tegra124/Makefile.inc | 8 + src/soc/nvidia/tegra124/verstage.c | 8 +- src/vendorcode/google/chromeos/Makefile.inc | 26 +++ src/vendorcode/google/chromeos/chromeos.h | 9 +- src/vendorcode/google/chromeos/vboot_handoff.c | 7 + src/vendorcode/google/chromeos/vboot_main.c | 311 +++++++++++++++++++++++++ 16 files changed, 423 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 6f65a71..96c8b49 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -68,6 +68,18 @@ $(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(boo endif # CONFIG_ARCH_BOOTBLOCK_ARM ############################################################################### +# verification stage +############################################################################### + +verstage-y += early_console.c +verstage-y += div0.c +verstage-y += eabi_compat.c +verstage-y += memset.S +verstage-y += memcpy.S +verstage-y += memmove.S +verstage-y += stages.c + +############################################################################### # romstage ############################################################################### diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 7e67178..0919a93 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -46,6 +46,18 @@ bootblock-S-ccopts += $(armv7_asm_flags) endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 +################################################################################ +## verification stage +################################################################################ + +verstage-c-ccopts += $(armv7_flags) +verstage-S-ccopts += $(armv7_asm_flags) +verstage-y += cache.c +verstage-y += cpu.S +verstage-y += exception.c +verstage-y += exception_asm.S +verstage-y += mmu.c + ############################################################################### # romstage ############################################################################### diff --git a/src/arch/arm/bootblock.ld b/src/arch/arm/bootblock.ld index 150bf2d..c1a6ccf 100644 --- a/src/arch/arm/bootblock.ld +++ b/src/arch/arm/bootblock.ld @@ -50,6 +50,7 @@ SECTIONS } : to_load = 0xff preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + verstage_preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; /DISCARD/ : { *(.comment) diff --git a/src/arch/arm/libgcc/Makefile.inc b/src/arch/arm/libgcc/Makefile.inc index a1d325d..5e8858a 100644 --- a/src/arch/arm/libgcc/Makefile.inc +++ b/src/arch/arm/libgcc/Makefile.inc @@ -25,6 +25,10 @@ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y) bootblock-y += $(libgcc_files) endif +ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) +verstage-y += $(libgcc_files) +endif + ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y) romstage-y += $(libgcc_files) endif diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index d339500..64d980b 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -6,6 +6,10 @@ ramstage-y += die.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c +verstage-y += vtxprintf.c +verstage-y += console.c +verstage-y += die.c + romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c diff --git a/src/include/reset.h b/src/include/reset.h index 9f117db..9430ffe 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -7,5 +7,6 @@ void hard_reset(void); #define hard_reset() do {} while(0) #endif void soft_reset(void); +void cpu_reset(void); #endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 9b5f56b..946012d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -24,6 +24,12 @@ bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c bootblock-y += memchr.c bootblock-y += memcmp.c +verstage-y += delay.c +verstage-y += cbfs.c +verstage-y += memcmp.c +verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c + + romstage-y += memchr.c romstage-y += memcmp.c $(foreach arch,$(ARCH_SUPPORTED),\ diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index b66cd55..02b3977 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -32,6 +32,8 @@ bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c +verstage-y += reset.c + romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..480abd6 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -228,7 +228,11 @@ static void __attribute__((noinline)) romstage(void) cbmemc_reinit(); #endif +#if CONFIG_VBOOT2_VERIFY_FIRMWARE + // vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); +#else vboot_verify_firmware(romstage_handoff_find_or_add()); +#endif timestamp_add(TS_START_COPYRAM, timestamp_get()); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index ea946e6..d9264fe 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -46,10 +46,12 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" + default 0x1e000 if VBOOT2_VERIFY_FIRMWARE default 0x18000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" + default 0x1e080 if VBOOT2_VERIFY_FIRMWARE default 0x18080 config SYS_SDRAM_BASE @@ -62,6 +64,7 @@ config BOOTBLOCK_BASE config ROMSTAGE_BASE hex + default 0x4002d000 if VBOOT2_VERIFY_FIRMWARE default 0x4002c000 config RAMSTAGE_BASE @@ -94,6 +97,14 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00017fe0 +config VBOOT_WORK_BUFFER_ADDRESS + hex "memory address of vboot work buffer" + default 0x40018000 + +config VBOOT_WORK_BUFFER_SIZE + hex "size of vboot work buffer" + default 0x00004000 + config TEGRA124_MODEL_TD570D bool "TD570D" diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index b306412..4b0ec96 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -21,6 +21,14 @@ bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c endif verstage-y += verstage.c +verstage-y += cbfs.c +verstage-y += dma.c +verstage-y += monotonic_timer.c +verstage-y += spi.c +verstage-y += timer.c +verstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +verstage-y += ../tegra/gpio.c +verstage-y += ../tegra/pinmux.c romstage-y += cbfs.c romstage-y += cbmem.c diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 234a89d..d85fc5c 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -1,9 +1,15 @@ #include "verstage.h" +#include <vendorcode/google/chromeos/chromeos.h> /** * Stage entry point */ void vboot_main(void) { - for(;;); + /* Stub to force arm_init_caches to the top, before any stack/memory + * accesses */ + asm volatile ("bl arm_init_caches" + ::: "r0","r1","r2","r3","r4","r5","ip"); + + select_firmware(); } diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 12d35b6..cb3d9a6 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -95,7 +95,33 @@ $(VB_LIB): endif ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y) +VB_SOURCE := vboot_reference VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a + +INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include +INCLUDES += -I$(VB_SOURCE)/firmware/include +verstage-y += vboot_main.c fmap.c chromeos.c + +VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-VERSTAGE-y)) +VB2_LIB = $(obj)/external/vboot_reference/vboot_fw2.a +VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CFLAGS_verstage))) +VBOOT_CFLAGS += $(verstage-c-ccopts) +VBOOT_CFLAGS += -include $(top)/src/include/kconfig.h -Wno-missing-prototypes +VBOOT_CFLAGS += -DVBOOT_DEBUG + +$(VB2_LIB): $(obj)/config.h + @printf " MAKE $(subst $(obj)/,,$(@))\n" + $(Q)FIRMWARE_ARCH=$(VB_FIRMWARE_ARCH) \ + CC="$(CC_verstage)" \ + CFLAGS="$(VBOOT_CFLAGS)" VBOOT2="y" \ + make -C $(VB_SOURCE) \ + BUILD=$(top)/$(dir $(VB2_LIB)) \ + V=$(V) \ + fwlib2 + mv $@ $@.tmp + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY_verstage) --prefix-symbols=verstage_ $@.tmp $@ + $(VERSTAGE_LIB): $$(verstage-objs) @printf " AR $(subst $(obj)/,,$(@))\n" $(AR_verstage) rc $@.tmp $(verstage-objs) diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a2ecac8..a799528 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,7 +46,7 @@ struct romstage_handoff; /* TODO(shawnn): Remove these CONFIGs and define default weak functions * that can be overridden in the platform / MB code. */ -#if CONFIG_VBOOT_VERIFY_FIRMWARE +#if CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE /* * This is a dual purpose routine. If dest is non-NULL the region at * offset_addr will be read into the area pointed to by dest. If dest @@ -67,7 +67,8 @@ static inline int vboot_get_handoff_info(void **addr, uint32_t *size) return -1; } static inline int vboot_skip_display_init(void) { return 0; } -#endif +#endif /* CONFIG_VBOOT_VERIFY_FIRMWARE || CONFIG_VBOOT2_VERIFY_FIRMWARE */ + int vboot_get_sw_write_protect(void); #include "gnvs.h" @@ -85,4 +86,8 @@ static inline void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) {} static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} #endif /* CONFIG_CHROMEOS_RAMOOPS */ +#if CONFIG_VBOOT2_VERIFY_FIRMWARE +void select_firmware(void); +#endif + #endif diff --git a/src/vendorcode/google/chromeos/vboot_handoff.c b/src/vendorcode/google/chromeos/vboot_handoff.c index 7ef2c7e..7ea21ea 100644 --- a/src/vendorcode/google/chromeos/vboot_handoff.c +++ b/src/vendorcode/google/chromeos/vboot_handoff.c @@ -105,6 +105,12 @@ int __attribute((weak)) vboot_get_sw_write_protect(void) return 0; } +#if CONFIG_VBOOT2_VERIFY_FIRMWARE + +void *vboot_get_payload(int *len) { return NULL; } + +#else /* CONFIG_VBOOT2_VERIFY_FIRMWARE */ + static void *vboot_get_payload(size_t *len) { struct vboot_handoff *vboot_handoff; @@ -131,6 +137,7 @@ static void *vboot_get_payload(size_t *len) return (void *)fwc->address; } +#endif static int vboot_locate_payload(struct payload *payload) { diff --git a/src/vendorcode/google/chromeos/vboot_main.c b/src/vendorcode/google/chromeos/vboot_main.c new file mode 100644 index 0000000..9779d35 --- /dev/null +++ b/src/vendorcode/google/chromeos/vboot_main.c @@ -0,0 +1,311 @@ +#include <2api.h> +#include <2struct.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> +#include <console/vtxprintf.h> +#include <reset.h> +#include <string.h> + +#include "chromeos.h" +#include "fmap.h" + +#define VBDEBUG(format, args...) \ + printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) +#define TODO_BLOCK_SIZE 8192 +#define MAX_PARSED_FW_COMPONENTS 5 +#define ROMSTAGE_INDEX 2 + +struct component_entry { + uint32_t offset; + uint32_t size; +} __attribute__((packed)); + +struct components { + uint32_t num_components; + struct component_entry entries[MAX_PARSED_FW_COMPONENTS]; +} __attribute__((packed)); + +struct vboot_region { + uintptr_t offset_addr; + int32_t size; +}; + +/* exports */ + +void vb2ex_printf(const char *func, const char *fmt, ...) +{ + va_list args; + + printk(BIOS_INFO, "VB2:%s() ", func); + va_start(args, fmt); + printk(BIOS_INFO, fmt, args); + va_end(args); + + return; +} + +int vb2ex_tpm_clear_owner(struct vb2_context *ctx) +{ + VBDEBUG("Clearing owner\n"); + return VB2_ERROR_UNKNOWN; +} + +int vb2ex_read_resource(struct vb2_context *ctx, + enum vb2_resource_index index, + uint32_t offset, + void *buf, + uint32_t size) +{ + VBDEBUG("Reading resource\n"); + return VB2_ERROR_UNKNOWN; +} + +/* locals */ + +static void locate_region(const char *name, struct vboot_region *region) +{ + region->size = find_fmap_entry(name, (void **)&region->offset_addr); + VBDEBUG("Located %s @%x\n", name, region->offset_addr); +} + +static int is_slot_a(struct vb2_context *ctx) +{ + return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); +} + +static int in_ro(void) +{ + /* TODO: Implement */ + return 1; +} + +static void reboot(void) +{ + cpu_reset(); +} + +static void recovery(void) +{ + void *entry; + + if (!in_ro()) + reboot(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + if (entry != (void *)-1) + stage_exit(entry); + + for(;;); +} + +static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main) +{ + uint32_t expected_size; + uint8_t block[TODO_BLOCK_SIZE]; + size_t block_size = sizeof(block); + uintptr_t offset; + int rv; + + expected_size = fw_main->size; + offset= fw_main->offset_addr; + + /* Start the body hash */ + rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size); + if (rv) { + return rv; + } + + /* Extend over the body */ + while (expected_size) { + void *b; + if (block_size > expected_size) + block_size = expected_size; + + b = vboot_get_region(offset, block_size, block); + if (b == NULL) + return VB2_ERROR_UNKNOWN; + rv = vb2api_extend_hash(ctx, b, block_size); + if (rv) + return rv; + + expected_size -= block_size; + offset+= block_size; + } + + /* Check the result */ + rv = vb2api_check_hash(ctx); + if (rv) { + return rv; + } + + return VB2_SUCCESS; +} + +static int locate_fw_components(struct vb2_context *ctx, + struct vboot_region *fw_main, + struct components *fw_info) +{ + if (is_slot_a(ctx)) + locate_region("FW_MAIN_A", fw_main); + else + locate_region("FW_MAIN_B", fw_main); + if (fw_main->size < 0) + return 1; + + if (vboot_get_region(fw_main->offset_addr, + sizeof(*fw_info), fw_info) == NULL) + return 1; + return 0; +} + +static struct cbfs_stage *load_stage(struct vb2_context *ctx, + int stage_index, + struct vboot_region *fw_main, + struct components *fw_info) +{ + struct cbfs_stage *stage; + uint32_t fc_addr; + uint32_t fc_size; + + /* Check for invalid address. */ + fc_addr = fw_main->offset_addr + fw_info->entries[stage_index].offset; + fc_size = fw_info->entries[stage_index].size; + if (fc_addr == 0 || fc_size == 0) { + VBDEBUG("romstage address invalid.\n"); + return NULL; + } + + /* Loading to cbfs cache. This stage data must be retained until it's + * decompressed. */ + stage = vboot_get_region(fc_addr, fc_size, NULL); + + if (stage == NULL) { + VBDEBUG("Unable to load a stage.\n"); + return NULL; + } + + return stage; +} + +static void enter_stage(struct cbfs_stage *stage) +{ + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *) (uintptr_t)stage->load, 0, stage->memlen); + + if (cbfs_decompress(stage->compression, + (unsigned char *)stage + sizeof(*stage), + (void *) (uintptr_t) stage->load, + stage->len)) + return; + + VBDEBUG("Jumping to entry @%llx.\n", stage->entry); + stage_exit((void *)(uintptr_t)stage->entry); +} + +/** + * Save non-volatile and/or secure data if needed. + */ +static void save_if_needed(struct vb2_context *ctx) +{ + if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { + VBDEBUG("Saving nvdata\n"); + //save_vbnv(ctx->nvdata); + ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; + } + if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { + VBDEBUG("Saving secdata\n"); + //antirollback_write_space_firmware(ctx); + ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; + } +} + +void __attribute__((noinline)) select_firmware(void) +{ + struct vb2_context ctx; + uint8_t *workbuf = (uint8_t *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS; + struct vboot_region fw_main; + struct components fw_info; + struct cbfs_stage *stage; + int rv; + + console_init(); + + /* Set up context */ + memset(&ctx, 0, sizeof(ctx)); + ctx.workbuf = workbuf; + ctx.workbuf_size = CONFIG_VBOOT_WORK_BUFFER_SIZE; + memset(ctx.workbuf, 0, ctx.workbuf_size); + + /* Read nvdata from a non-volatile storage */ + //read_vbnv(ctx.nvdata); + + /* Read secdata from TPM. Initialize TPM if secdata not found. We don't + * check the return value here because vb2api_fw_phase1 will catch + * invalid secdata and tell us what to do (=reboot). */ + //antirollback_read_space_firmware(&ctx); + + //if (get_developer_mode_switch()) + // ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; + //if (get_recovery_mode_switch()) { + // clear_recovery_mode_switch(); + // ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; + //} + + /* Do early init */ + VBDEBUG("Phase 1\n"); + rv = vb2api_fw_phase1(&ctx); + if (rv) { + VBDEBUG("Recovery requested (%x)\n", rv); + /* If we need recovery mode, leave firmware selection now */ + save_if_needed(&ctx); + recovery(); + } + + /* Determine which firmware slot to boot */ + VBDEBUG("Phase 2\n"); + rv = vb2api_fw_phase2(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + save_if_needed(&ctx); + reboot(); + } + + /* Try that slot */ + VBDEBUG("Phase 3\n"); + rv = vb2api_fw_phase3(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + save_if_needed(&ctx); + reboot(); + } + + VBDEBUG("Phase 4\n"); + rv = locate_fw_components(&ctx, &fw_main, &fw_info); + if (rv) { + VBDEBUG("Failed to locate firmware components\n"); + reboot(); + } + rv = hash_body(&ctx, &fw_main); + stage = load_stage(&ctx, ROMSTAGE_INDEX, &fw_main, &fw_info); + if (stage == NULL) { + VBDEBUG("Failed to load stage\n"); + reboot(); + } + save_if_needed(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + reboot(); + } + + /* TODO: Do we need to lock secdata? */ + VBDEBUG("Locking TPM\n"); + + /* Load next stage and jump to it */ + VBDEBUG("Jumping to rw-romstage @%llx\n", stage->entry); + enter_stage(stage); + + /* Shouldn't reach here */ + VBDEBUG("Halting\n"); + for(;;); +}

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Patch set updated for coreboot: 08bf8fa arm64: Prepare ARM64 for building
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8236 -gerrit commit 08bf8fa2c89da2a50ecea9a90c4339f5ba1d1bf7 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jan 16 13:45:23 2015 -0700 arm64: Prepare ARM64 for building There were a number of issues with the ARM64 build files. This patch ports the following changes from ARMV4/V7 to ARMV8: - make armv8 Kconfig options consistent with armv4/v7 - fix build include issues in boot.c, tables.c, and early_variables.h by matching armv4/v7. Change-Id: I57359a96821d88c50f48dc0bb6ad226cacb0c2ec Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Iacd95d336559c45458784d1da67bde62a0956620 --- src/arch/arm64/Makefile.inc | 35 ++++++++++++++------------- src/arch/arm64/armv8/Kconfig | 8 +++--- src/arch/arm64/armv8/Makefile.inc | 9 ++++--- src/arch/arm64/boot.c | 7 +++--- src/arch/arm64/include/arch/early_variables.h | 4 --- src/arch/arm64/tables.c | 10 +++++--- 6 files changed, 39 insertions(+), 34 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 5bf72b2..a080e23 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -37,6 +37,16 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) CBFSTOOL_PRE1_OPTS = -m arm64 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET) endif +ifeq ($(CONFIG_ARCH_ARM64),y) +stages_c = $(src)/arch/arm64/stages.c +stages_o = $(obj)/arch/arm64/stages.o + +$(stages_o): $(stages_c) $(obj)/config.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_arm) -I. $(CPPFLAGS_arm) -c -o $@ $< -marm + +endif + ################################################################################ # bootblock ################################################################################ @@ -44,14 +54,11 @@ endif ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM64),y) bootblock-y += div0.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c - bootblock-y += id.S $(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h bootblock-y += stages.c bootblock-y += eabi_compat.c - bootblock-y += memset.S bootblock-y += memcpy.S bootblock-y += memmove.S @@ -60,7 +67,7 @@ bootblock-y += memmove.S $(objcbfs)/bootblock.debug: $(src)/arch/arm64/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm64/bootblock.ld + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm64/bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -72,7 +79,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) romstage-y += stages.c romstage-y += div0.c -romstage-y += early_console.c romstage-y += eabi_compat.c romstage-y += memset.S romstage-y += memcpy.S @@ -80,6 +86,7 @@ romstage-y += memmove.S romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c # Build the romstage +VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o $(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm64/romstage.ld $(obj)/ldoptions @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -102,24 +109,18 @@ ramstage-y += tables.c ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S - -rmodules_$(ARCH-ramstage-y) += memset.S -rmodules_$(ARCH-ramstage-y) += memcpy.S -rmodules_$(ARCH-ramstage-y) += memmove.S -rmodules_$(ARCH-ramstage-y) += eabi_compat.c - -VBOOT_STUB_DEPS += $(obj)/arch/arm64/eabi_compat.rmodules.o - -$(eval $(call create_class_compiler,rmodules,arm64)) - ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c +ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) # Build the ramstage $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm64/ramstage.ld $(obj)/ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld + $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld + +$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(LD_ramstage) -nostdlib --gc-sections -r -o $@ --start-group $(ramstage-objs) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index fc2e668..1dd2576 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -1,9 +1,11 @@ -config ARCH_BOOTBLOCK_ARM_V8_64 +config ARCH_BOOTBLOCK_ARMV8_64 def_bool n select ARCH_BOOTBLOCK_ARM64 -config ARCH_ROMSTAGE_ARM_V8_64 + +config ARCH_ROMSTAGE_ARMV8_64 def_bool n select ARCH_ROMSTAGE_ARM64 -config ARCH_RAMSTAGE_ARM_V8_64 + +config ARCH_RAMSTAGE_ARMV8_64 def_bool n select ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 973b391..c5f7a80 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -26,7 +26,7 @@ armv8_asm_flags = $(armv8_flags) ################################################################################ ## bootblock ################################################################################ -ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock.S @@ -46,7 +46,7 @@ endif ################################################################################ ## romstage ################################################################################ -ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) romstage-y += cache.c romstage-y += cpu.S @@ -61,7 +61,7 @@ endif ################################################################################ ## ramstage ################################################################################ -ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) ramstage-y += cache.c ramstage-y += cpu.S @@ -71,4 +71,7 @@ ramstage-y += exception_asm.S ramstage-c-ccopts += $(armv8_flags) ramstage-S-ccopts += $(armv8_asm_flags) +rmodules_arm64-c-ccopts += $(armv8_flags) +rmodules_arm64-S-ccopts += $(armv8_asm_flags) + endif diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 6fb0e65..85b2cce 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -21,13 +21,14 @@ #include <arch/stages.h> #include <cbmem.h> #include <console/console.h> +#include <payload_loader.h> -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) +void arch_payload_run(const struct payload *payload) { - void (*doit)(void *) = entry; + void (*doit)(void *) = payload->entry; void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE); - printk(BIOS_SPEW, "entry = %p\n", entry); + printk(BIOS_SPEW, "entry = %p\n", payload->entry); cache_sync_instructions(); doit(cb_tables); } diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 3d9fa26..5b58baa 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -20,10 +20,6 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if CONFIG_CAR_MIGRATION - #error "This is ARM, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index ce7ad5a..a2b7b9b 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -33,7 +33,11 @@ void cbmem_arch_init(void) { } -struct lb_memory *write_tables(void) +void cbmem_fail_resume(void) +{ +} + +void write_tables(void) { unsigned long table_pointer, new_table_pointer; @@ -43,7 +47,7 @@ struct lb_memory *write_tables(void) MAX_COREBOOT_TABLE_SIZE); if (!table_pointer) { printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return NULL; + return; } new_table_pointer = write_coreboot_table(0UL, 0UL, @@ -61,6 +65,4 @@ struct lb_memory *write_tables(void) /* Print CBMEM sections */ cbmem_list(); - - return get_lb_mem(); }

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Patch set updated for coreboot: 4820aac tegra132: Add support for tegra132 soc
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8040 -gerrit commit 4820aacefdb129b5e4ff47a52a8757dc7304ba69 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Apr 28 16:43:07 2014 -0700 tegra132: Add support for tegra132 soc Add basic support for tegra132 soc. BUG=None BRANCH=None TEST=Compiles successfully for rush board using tegra132 soc Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197398 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 --- src/soc/nvidia/Kconfig | 1 + src/soc/nvidia/Makefile.inc | 1 + src/soc/nvidia/tegra132/Kconfig | 24 ++ src/soc/nvidia/tegra132/Makefile.inc | 12 + src/soc/nvidia/tegra132/cbfs.c | 26 +++ src/soc/nvidia/tegra132/cbmem.c | 26 +++ src/soc/nvidia/tegra132/chip.h | 31 +++ src/soc/nvidia/tegra132/include/soc/addressmap.h | 83 +++++++ src/soc/nvidia/tegra132/include/soc/clock.h | 276 +++++++++++++++++++++++ src/soc/nvidia/tegra132/include/soc/display.h | 202 +++++++++++++++++ src/soc/nvidia/tegra132/timer.c | 31 +++ 11 files changed, 713 insertions(+) diff --git a/src/soc/nvidia/Kconfig b/src/soc/nvidia/Kconfig index 836edeb..cb1f468 100644 --- a/src/soc/nvidia/Kconfig +++ b/src/soc/nvidia/Kconfig @@ -1 +1,2 @@ source src/soc/nvidia/tegra124/Kconfig +source src/soc/nvidia/tegra132/Kconfig diff --git a/src/soc/nvidia/Makefile.inc b/src/soc/nvidia/Makefile.inc index 34feb0a..100cb94 100644 --- a/src/soc/nvidia/Makefile.inc +++ b/src/soc/nvidia/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_SOC_NVIDIA_TEGRA124) += tegra124 +subdirs-$(CONFIG_SOC_NVIDIA_TEGRA132) += tegra132 diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig new file mode 100644 index 0000000..df58f06 --- /dev/null +++ b/src/soc/nvidia/tegra132/Kconfig @@ -0,0 +1,24 @@ +config SOC_NVIDIA_TEGRA132 + bool + default n + select ARCH_BOOTBLOCK_ARMV4 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM_LPAE + select DYNAMIC_CBMEM + +if SOC_NVIDIA_TEGRA132 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x18080 + +endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc new file mode 100644 index 0000000..e31bbb6 --- /dev/null +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -0,0 +1,12 @@ +bootblock-y += cbfs.c +bootblock-y += timer.c + +romstage-y += cbfs.c +romstage-y += cbmem.c +romstage-y += timer.c + +ramstage-y += cbfs.c +ramstage-y += cbmem.c +ramstage-y += timer.c + +CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ diff --git a/src/soc/nvidia/tegra132/cbfs.c b/src/soc/nvidia/tegra132/cbfs.c new file mode 100644 index 0000000..ac4a557 --- /dev/null +++ b/src/soc/nvidia/tegra132/cbfs.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cbfs.h> /* This driver serves as a CBFS media source. */ + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/nvidia/tegra132/cbmem.c b/src/soc/nvidia/tegra132/cbmem.c new file mode 100644 index 0000000..495fcba --- /dev/null +++ b/src/soc/nvidia/tegra132/cbmem.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ +/* TODO: update with real cbmem_top function. */ + return NULL; +} diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h new file mode 100644 index 0000000..394f0a4 --- /dev/null +++ b/src/soc/nvidia/tegra132/chip.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_CHIP_H__ +#define __SOC_NVIDIA_TEGRA132_CHIP_H__ +#include <arch/cache.h> +#include <soc/addressmap.h> + +#define EFAULT 1 +#define EINVAL 2 + +struct soc_nvidia_tegra132_config { +}; + +#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h new file mode 100644 index 0000000..d9d970a --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ +#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ + +#include <stddef.h> + +enum { + TEGRA_SRAM_BASE = 0x40000000, + TEGRA_SRAM_SIZE = 0x40000 +}; + +enum { + TEGRA_ARM_PERIPHBASE = 0x50040000, + TEGRA_ARM_DISPLAYA = 0x54200000, + TEGRA_ARM_DISPLAYB = 0x54240000, + TEGRA_ARM_SOR = 0x54540000, + TEGRA_ARM_DPAUX = 0x545c0000, + TEGRA_PG_UP_BASE = 0x60000000, + TEGRA_TMRUS_BASE = 0x60005010, + TEGRA_CLK_RST_BASE = 0x60006000, + TEGRA_FLOW_BASE = 0x60007000, + TEGRA_GPIO_BASE = 0x6000D000, + TEGRA_EVP_BASE = 0x6000F000, + TEGRA_APB_DMA_BASE = 0x60020000, + TEGRA_APB_MISC_BASE = 0x70000000, + TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, + TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, + TEGRA_APB_PINMUX_BASE = TEGRA_APB_MISC_BASE + 0x3000, + TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000, + TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040, + TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200, + TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300, + TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400, + TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000, + TEGRA_PWM_BASE = TEGRA_APB_MISC_BASE + 0xA000, + TEGRA_I2C_BASE = TEGRA_APB_MISC_BASE + 0xC000, + TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380, + TEGRA_I2C2_BASE = TEGRA_APB_MISC_BASE + 0xC400, + TEGRA_I2C3_BASE = TEGRA_APB_MISC_BASE + 0xC500, + TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700, + TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000, + TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100, + TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400, + TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600, + TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800, + TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, + TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, + TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, + TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, + TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, + TEGRA_MC_BASE = 0x70019000, + TEGRA_EMC_BASE = 0x7001B000, + TEGRA_CSITE_BASE = 0x70040000, + TEGRA_SYSCTR0_BASE = 0x700F0000, + TEGRA_USBD_BASE = 0x7D000000, + TEGRA_USB2_BASE = 0x7D004000, + TEGRA_USB3_BASE = 0x7D008000, +}; + +enum { + TEGRA_I2C_BASE_COUNT = 6, +}; + +#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h new file mode 100644 index 0000000..5fc10c3 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -0,0 +1,276 @@ +/* + * Copyright 2014 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_CLOCK_H__ +#define __SOC_NVIDIA_TEGRA132_CLOCK_H__ + +#include <stdint.h> + +enum { + CLK_L_CPU = 0x1 << 0, + CLK_L_COP = 0x1 << 1, + CLK_L_TRIG_SYS = 0x1 << 2, + CLK_L_RTC = 0x1 << 4, + CLK_L_TMR = 0x1 << 5, + CLK_L_UARTA = 0x1 << 6, + CLK_L_UARTB = 0x1 << 7, + CLK_L_GPIO = 0x1 << 8, + CLK_L_SDMMC2 = 0x1 << 9, + CLK_L_SPDIF = 0x1 << 10, + CLK_L_I2S1 = 0x1 << 11, + CLK_L_I2C1 = 0x1 << 12, + CLK_L_NDFLASH = 0x1 << 13, + CLK_L_SDMMC1 = 0x1 << 14, + CLK_L_SDMMC4 = 0x1 << 15, + CLK_L_PWM = 0x1 << 17, + CLK_L_I2S2 = 0x1 << 18, + CLK_L_EPP = 0x1 << 19, + CLK_L_VI = 0x1 << 20, + CLK_L_2D = 0x1 << 21, + CLK_L_USBD = 0x1 << 22, + CLK_L_ISP = 0x1 << 23, + CLK_L_3D = 0x1 << 24, + CLK_L_DISP2 = 0x1 << 26, + CLK_L_DISP1 = 0x1 << 27, + CLK_L_HOST1X = 0x1 << 28, + CLK_L_VCP = 0x1 << 29, + CLK_L_I2S0 = 0x1 << 30, + CLK_L_CACHE2 = 0x1 << 31, + + CLK_H_MEM = 0x1 << 0, + CLK_H_AHBDMA = 0x1 << 1, + CLK_H_APBDMA = 0x1 << 2, + CLK_H_KBC = 0x1 << 4, + CLK_H_STAT_MON = 0x1 << 5, + CLK_H_PMC = 0x1 << 6, + CLK_H_FUSE = 0x1 << 7, + CLK_H_KFUSE = 0x1 << 8, + CLK_H_SBC1 = 0x1 << 9, + CLK_H_SNOR = 0x1 << 10, + CLK_H_JTAG2TBC = 0x1 << 11, + CLK_H_SBC2 = 0x1 << 12, + CLK_H_SBC3 = 0x1 << 14, + CLK_H_I2C5 = 0x1 << 15, + CLK_H_DSI = 0x1 << 16, + CLK_H_HSI = 0x1 << 18, + CLK_H_HDMI = 0x1 << 19, + CLK_H_CSI = 0x1 << 20, + CLK_H_I2C2 = 0x1 << 22, + CLK_H_UARTC = 0x1 << 23, + CLK_H_MIPI_CAL = 0x1 << 24, + CLK_H_EMC = 0x1 << 25, + CLK_H_USB2 = 0x1 << 26, + CLK_H_USB3 = 0x1 << 27, + CLK_H_MPE = 0x1 << 28, + CLK_H_VDE = 0x1 << 29, + CLK_H_BSEA = 0x1 << 30, + CLK_H_BSEV = 0x1 << 31, + + CLK_U_UARTD = 0x1 << 1, + CLK_U_UARTE = 0x1 << 2, + CLK_U_I2C3 = 0x1 << 3, + CLK_U_SBC4 = 0x1 << 4, + CLK_U_SDMMC3 = 0x1 << 5, + CLK_U_PCIE = 0x1 << 6, + CLK_U_OWR = 0x1 << 7, + CLK_U_AFI = 0x1 << 8, + CLK_U_CSITE = 0x1 << 9, + CLK_U_PCIEXCLK = 0x1 << 10, + CLK_U_AVPUCQ = 0x1 << 11, + CLK_U_TRACECLKIN = 0x1 << 13, + CLK_U_SOC_THERM = 0x1 << 14, + CLK_U_DTV = 0x1 << 15, + CLK_U_NAND_SPEED = 0x1 << 16, + CLK_U_I2C_SLOW = 0x1 << 17, + CLK_U_DSIB = 0x1 << 18, + CLK_U_TSEC = 0x1 << 19, + CLK_U_IRAMA = 0x1 << 20, + CLK_U_IRAMB = 0x1 << 21, + CLK_U_IRAMC = 0x1 << 22, + + // Clock reset. + CLK_U_EMUCIF = 0x1 << 23, + // Clock enable. + CLK_U_IRAMD = 0x1 << 23, + + CLK_U_CRAM2 = 0x2 << 24, + CLK_U_XUSB_HOST = 0x1 << 25, + CLK_U_MSENC = 0x1 << 27, + CLK_U_SUS_OUT = 0x1 << 28, + CLK_U_DEV2_OUT = 0x1 << 29, + CLK_U_DEV1_OUT = 0x1 << 30, + CLK_U_XUSB_DEV = 0x1 << 31, + + CLK_V_CPUG = 0x1 << 0, + CLK_V_CPULP = 0x1 << 1, + CLK_V_3D2 = 0x1 << 2, + CLK_V_MSELECT = 0x1 << 3, + CLK_V_I2S3 = 0x1 << 5, + CLK_V_I2S4 = 0x1 << 6, + CLK_V_I2C4 = 0x1 << 7, + CLK_V_SBC5 = 0x1 << 8, + CLK_V_SBC6 = 0x1 << 9, + CLK_V_AUDIO = 0x1 << 10, + CLK_V_APBIF = 0x1 << 11, + CLK_V_DAM0 = 0x1 << 12, + CLK_V_DAM1 = 0x1 << 13, + CLK_V_DAM2 = 0x1 << 14, + CLK_V_HDA2CODEC_2X = 0x1 << 15, + CLK_V_ATOMICS = 0x1 << 16, + CLK_V_ACTMON = 0x1 << 23, + CLK_V_EXTPERIPH1 = 0x1 << 24, + CLK_V_SATA = 0x1 << 28, + CLK_V_HDA = 0x1 << 29, + + CLK_W_HDA2HDMICODEC = 0x1 << 0, + CLK_W_SATACOLD = 0x1 << 1, + CLK_W_CEC = 0x1 << 8, + CLK_W_XUSB_PADCTL = 0x1 << 14, + CLK_W_ENTROPY = 0x1 << 21, + CLK_W_AMX0 = 0x1 << 25, + CLK_W_ADX0 = 0x1 << 26, + CLK_W_DVFS = 0x1 << 27, + CLK_W_XUSB_SS = 0x1 << 28, + CLK_W_MC1 = 0x1 << 30, + CLK_W_EMC1 = 0x1 << 31, + + CLK_X_AFC0 = 0x1 << 31, + CLK_X_AFC1 = 0x1 << 30, + CLK_X_AFC2 = 0x1 << 29, + CLK_X_AFC3 = 0x1 << 28, + CLK_X_AFC4 = 0x1 << 27, + CLK_X_AFC5 = 0x1 << 26, + CLK_X_AMX1 = 0x1 << 25, + CLK_X_GPU = 0x1 << 24, + CLK_X_SOR0 = 0x1 << 22, + CLK_X_DPAUX = 0x1 << 21, + CLK_X_ADX1 = 0x1 << 20, + CLK_X_VIC = 0x1 << 18, + CLK_X_CLK72MHZ = 0x1 << 17, + CLK_X_HDMI_AUDIO = 0x1 << 16, + CLK_X_EMC_DLL = 0x1 << 14, + CLK_X_VIM2_CLK = 0x1 << 11, + CLK_X_I2C6 = 0x1 << 6, + CLK_X_CAM_MCLK2 = 0x1 << 5, + CLK_X_CAM_MCLK = 0x1 << 4, + CLK_X_SPARE = 0x1 << 0, +}; + +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +#define IO_STABILIZATION_DELAY (2) +/* Calculate clock fractional divider value from ref and target frequencies. + * This is for a U7.1 format. This is not well written up in the book and + * there have been some questions about this macro, so here we go. + * U7.1 format is defined as (ddddddd+1) + (h*.5) + * The lowest order bit is actually a fractional bit. + * Hence, the divider can be thought of as 9 bits. + * So: + * divider = ((ref/freq) << 1 - 1) (upper 7 bits) | + * (ref/freq & 1) (low order half-bit) + * however we can't do fractional arithmetic ... these are integers! + * So we normalize by shifting the result left 1 bit, and extracting + * ddddddd and h directly to the returned u8. + * divider = 2*(ref/freq); + * We want to + * preserve 7 bits of divisor and one bit of fraction, in 8 bits, as well as + * subtract one from ddddddd. Since we computed ref*2, the dddddd is now nicely + * situated in the upper 7 bits, and the h is sitting there in the low order + * bit. To subtract 1 from ddddddd, just subtract 2 from the 8-bit number + * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you + * will assign this to a u8, it gets nicely truncated for you. + */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / (FREQ)) - 2) + +/* Calculate clock frequency value from reference and clock divider value + * The discussion in the book is pretty lacking. + * The idea is that we need to divide a ref clock by a divisor + * in U7.1 format, where 7 upper bits are the integer + * and lowest order bit is a fraction. + * from the book, U7.1 is (ddddddd+1) + (h*.5) + * To normalize to an actual number, we might do this: + * ((d>>7+1)&0x7f) + (d&1 >> 1) + * but as you might guess, the low order bit would be lost. + * Since we can't express the fractional bit, we need to multiply it all by 2. + * ((d + 2)&0xfe) + (d & 1) + * Since we're just adding +2, the lowest order bit is preserved. Hence + * (d+2) is the same as ((d + 2)&0xfe) + (d & 1) + * + * Since you multiply denominator * 2 (by NOT shifting it), + * you multiply numerator * 2 to cancel it out. + */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2)) + +#define clock_configure_irregular_source(device, src, freq, src_id) \ + clrsetbits_le32(&clk_rst->clk_src_##device, \ + CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \ + src_id << CLK_SOURCE_SHIFT | \ + CLK_DIVIDER(TEGRA_##src##_KHZ, freq)) + +/* Warning: Some devices just use different bits for the same sources for no + * apparent reason. *Always* double-check the TRM before trusting this macro. */ +#define clock_configure_source(device, src, freq) \ + clock_configure_irregular_source(device, src, freq, src) + +/* The I2C divisors are not 7.1 divisors like the others, they divide by n + 1 + * directly. Also, there are internal divisors in the I2C controller itself. + * We can deal with those here and make it easier to select what the actual + * bus frequency will be. The 0x19 value is the default divisor in the + * clk_divisor register in the controller, and 8 is just a magic number in the + * documentation. Multiplying by 2 compensates for the different format of the + * divisor. + */ +#define clock_configure_i2c_scl_freq(device, src, freq) \ + clock_configure_source(device, src, (freq) * (0x19 + 1) * 8 * 2) + +enum clock_source { /* Careful: Not true for all sources, always check TRM! */ + PLLP = 0, + PLLC2 = 1, + PLLC = 2, + PLLD = 2, + PLLC3 = 3, + PLLA = 3, + PLLM = 4, + PLLD2 = 5, + CLK_M = 6, +}; + +/* soc-specific */ +#define TEGRA_CLK_M_KHZ clock_get_osc_khz() +#define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ +#define TEGRA_PLLP_KHZ (408000) +#define TEGRA_PLLC_KHZ (600000) +#define TEGRA_PLLD_KHZ (925000) +#define TEGRA_PLLU_KHZ (960000) + +int clock_get_osc_khz(void); +void clock_early_uart(void); +void clock_external_output(int clk_id); +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq); +void clock_cpu0_config_and_reset(void * entry); +void clock_halt_avp(void); +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); +void clock_init(void); +void clock_init_arm_generic_timer(void); +void sor_clock_stop(void); +void sor_clock_start(void); + +#endif /* __SOC_NVIDIA_TEGRA132_CLOCK_H__ */ + diff --git a/src/soc/nvidia/tegra132/include/soc/display.h b/src/soc/nvidia/tegra132/include/soc/display.h new file mode 100644 index 0000000..2c21292 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/display.h @@ -0,0 +1,202 @@ +/* + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ +#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ + +/* ardisplay.h */ +#define DC_CMD_DISPLAY_WINDOW_HEADER_0 0x42 +#define DC_COM_CRC_CONTROL_0 0x300 +#define DC_COM_CRC_CHECKSUM_0 0x301 +#define DC_COM_PIN_OUTPUT_ENABLE0_0 0x302 +#define DC_COM_PIN_OUTPUT_ENABLE1_0 0x303 +#define DC_COM_PIN_OUTPUT_ENABLE2_0 0x304 +#define DC_COM_PIN_OUTPUT_ENABLE3_0 0x305 +#define DC_CMD_STATE_ACCESS_0 0x40 +#define DC_DISP_DISP_CLOCK_CONTROL_0 0x42e +#define DC_DISP_DISP_TIMING_OPTIONS_0 0x405 +#define DC_DISP_REF_TO_SYNC_0 0x406 +#define DC_DISP_SYNC_WIDTH_0 0x407 +#define DC_DISP_BACK_PORCH_0 0x408 +#define DC_DISP_DISP_ACTIVE_0 0x409 +#define DC_DISP_FRONT_PORCH_0 0x40a +#define DC_DISP_DISP_WIN_OPTIONS_0 0x402 +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT 25 +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD (0x1 << DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0 0x400 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0 0x4e4 +#define DC_CMD_DISPLAY_COMMAND_0 0x32 +#define DC_CMD_STATE_CONTROL_0 0x41 +#define DC_CMD_DISPLAY_POWER_CONTROL_0 0x36 + +/* ardisplay_a.h */ +#define DC_WIN_A_WIN_OPTIONS_0 0x700 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT 30 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD (0x1 << DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE (1) +#define DC_WIN_A_BYTE_SWAP_0 0x701 +#define DC_WIN_A_BUFFER_CONTROL_0 0x702 +#define DC_WIN_A_COLOR_DEPTH_0 0x703 +#define DC_WIN_A_POSITION_0 0x704 +#define DC_WIN_A_SIZE_0 0x705 +#define DC_WIN_A_PRESCALED_SIZE_0 0x706 +#define DC_WIN_A_H_INITIAL_DDA_0 0x707 +#define DC_WIN_A_V_INITIAL_DDA_0 0x708 +#define DC_WIN_A_DDA_INCREMENT_0 0x709 +#define DC_WIN_A_LINE_STRIDE_0 0x70a +#define DC_WIN_A_DV_CONTROL_0 0x70e +#define DC_WIN_A_BLEND_LAYER_CONTROL_0 0x716 +#define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719 +#define DC_WINBUF_A_START_ADDR_LO_0 0x800 +#define DC_WINBUF_A_START_ADDR_HI_0 0x80d +#define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806 +#define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808 + +/* ardisplay_bd.h */ +#define DC_B_WIN_BD_SIZE_0 0xd85 +#define DC_B_WIN_BD_PRESCALED_SIZE_0 0xd86 +#define DC_B_WIN_BD_LINE_STRIDE_0 0xd8a +#define DC_B_WIN_BD_COLOR_DEPTH_0 0xd83 +#define DC_B_WINBUF_BD_START_ADDR_0 0xdc0 +#define DC_B_WIN_BD_DDA_INCREMENT_0 0xd89 +#define DC_B_WIN_BD_WIN_OPTIONS_0 0xd80 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT 30 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD (0x1 << DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE (1) + +/* arsor.h */ +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c +#define SOR_NV_PDISP_SOR_PLL0_0 0x17 +#define SOR_NV_PDISP_SOR_PLL1_0 0x18 +#define SOR_NV_PDISP_SOR_PLL2_0 0x19 +#define SOR_NV_PDISP_SOR_PLL3_0 0x1a +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT 22 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT 0 +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT 2 +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT 24 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT 23 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT 25 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 0x4e +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 0x52 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0 0x56 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT 8 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD (0xff << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT 22 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0 0x1c +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0 0x4c +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0 0x21 +#define SOR_NV_PDISP_SOR_DP_TPG_0 0x6d +#define SOR_NV_PDISP_HEAD_STATE1_0 0x7 +#define SOR_NV_PDISP_HEAD_STATE2_0 0x9 +#define SOR_NV_PDISP_HEAD_STATE3_0 0xb +#define SOR_NV_PDISP_HEAD_STATE4_0 0xd +#define SOR_NV_PDISP_SOR_STATE1_0 0x4 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT 12 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT 13 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT 8 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_LVDS_CUSTOM (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A (8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_B (9) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_CUSTOM (15) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_ACTIVE_RASTER (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_NON_ACTIVE_RASTER (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT 6 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT 4 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD0 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD1 (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_BOTH (3) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT 0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_NONE (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD1 (2) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0 0x58 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT 24 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT 16 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD (0xf << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT 8 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT 0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD (0x3f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT 2 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT 17 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULTVAL (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_16_422 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444 (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_20_422 (3) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_422 (4) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 (5) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_30_444 (6) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_32_422 (7) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_36_444 (8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_48_444 (9) + +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0 0x11 +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0 0x64 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0 0x60 +#define SOR_NV_PDISP_SOR_PWR_0 0x15 +#define SOR_NV_PDISP_SOR_STATE0_0 0x3 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0 0x2 +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0 0x1 + +/* ardpaux.h */ +#define DPAUX_DP_AUXDATA_READ_W0 0x19 + +#define DP_LVDS_SHIFT 25 +#define DP_LVDS (1 << DP_LVDS_SHIFT) + +#define SRC_BPP 16 +#define COLORDEPTH 0x6 +#define COLOR_WHITE 0xFFFFFF + +struct soc_nvidia_tegra132_config; /* forward declaration */ +void setup_display(struct soc_nvidia_tegra132_config *config); +void init_dca_regs(void); +void dp_io_powerup(void); +u32 dp_setup_timing(u32 width, u32 height); +void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, + u32 lane_count, u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); + +#define FB_SIZE_MB (32) + +#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra132/timer.c b/src/soc/nvidia/tegra132/timer.c new file mode 100644 index 0000000..e2b0b82 --- /dev/null +++ b/src/soc/nvidia/tegra132/timer.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +void init_timer(void) +{ +} + +void udelay(unsigned usec) +{ +}

1 0

Patch set updated for coreboot: 1da5351 rush: Add support for rush board
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8041 -gerrit commit 1da53512f73df8897ee41aa00396eeab18694dd7 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Apr 28 16:44:21 2014 -0700 rush: Add support for rush board Add basic support for rush board BUG=None BRANCH=None TEST=Compiles successfully with soc tegra132 and armv8 arch selected for romstage and ramstage Original-Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197399 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 06a040dc320d7b04ec0f7e51c1b3987c8f6d80f3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ica57c68d230e4e0e9916729752395843de188733 --- src/mainboard/google/Kconfig | 3 +++ src/mainboard/google/rush/Kconfig | 39 +++++++++++++++++++++++++++++++++ src/mainboard/google/rush/Makefile.inc | 22 +++++++++++++++++++ src/mainboard/google/rush/devicetree.cb | 22 +++++++++++++++++++ src/mainboard/google/rush/mainboard.c | 35 +++++++++++++++++++++++++++++ src/mainboard/google/rush/romstage.c | 30 +++++++++++++++++++++++++ 6 files changed, 151 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index e84cd7c..dd77bf3 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -47,6 +47,8 @@ config BOARD_GOOGLE_PEPPY bool "Peppy" config BOARD_GOOGLE_RAMBI bool "Rambi" +config BOARD_GOOGLE_RUSH + bool "Rush" config BOARD_GOOGLE_SAMUS bool "Samus" config BOARD_GOOGLE_SLIPPY @@ -71,6 +73,7 @@ source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/peach_pit/Kconfig" source "src/mainboard/google/peppy/Kconfig" source "src/mainboard/google/rambi/Kconfig" +source "src/mainboard/google/rush/Kconfig" source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/storm/Kconfig" diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig new file mode 100644 index 0000000..96a17f8 --- /dev/null +++ b/src/mainboard/google/rush/Kconfig @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_RUSH + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_NVIDIA_TEGRA132 + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default google/rush + +config MAINBOARD_PART_NUMBER + string + default "Rush" + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_GOOGLE_RUSH diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc new file mode 100644 index 0000000..94a0e28 --- /dev/null +++ b/src/mainboard/google/rush/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += romstage.c + +ramstage-y += mainboard.c \ No newline at end of file diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb new file mode 100644 index 0000000..73836a4 --- /dev/null +++ b/src/mainboard/google/rush/devicetree.cb @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/nvidia/tegra132 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c new file mode 100644 index 0000000..9b8e354 --- /dev/null +++ b/src/mainboard/google/rush/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <boot/coreboot_tables.h> + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "rush", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c new file mode 100644 index 0000000..e2b75f6 --- /dev/null +++ b/src/mainboard/google/rush/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +}

1 0

Patch set updated for coreboot: bbea900 rush: Add support for rush board
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8041 -gerrit commit bbea900aadbb00882331ad9ec21bcedc82ab92cd Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Apr 28 16:44:21 2014 -0700 rush: Add support for rush board Add basic support for rush board BUG=None BRANCH=None TEST=Compiles successfully with soc tegra132 and armv8 arch selected for romstage and ramstage Original-Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197399 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 06a040dc320d7b04ec0f7e51c1b3987c8f6d80f3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ica57c68d230e4e0e9916729752395843de188733 --- src/mainboard/google/Kconfig | 3 +++ src/mainboard/google/rush/Kconfig | 39 +++++++++++++++++++++++++++++++++ src/mainboard/google/rush/Makefile.inc | 22 +++++++++++++++++++ src/mainboard/google/rush/devicetree.cb | 22 +++++++++++++++++++ src/mainboard/google/rush/mainboard.c | 35 +++++++++++++++++++++++++++++ src/mainboard/google/rush/romstage.c | 30 +++++++++++++++++++++++++ 6 files changed, 151 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index e84cd7c..dd77bf3 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -47,6 +47,8 @@ config BOARD_GOOGLE_PEPPY bool "Peppy" config BOARD_GOOGLE_RAMBI bool "Rambi" +config BOARD_GOOGLE_RUSH + bool "Rush" config BOARD_GOOGLE_SAMUS bool "Samus" config BOARD_GOOGLE_SLIPPY @@ -71,6 +73,7 @@ source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/peach_pit/Kconfig" source "src/mainboard/google/peppy/Kconfig" source "src/mainboard/google/rambi/Kconfig" +source "src/mainboard/google/rush/Kconfig" source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/storm/Kconfig" diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig new file mode 100644 index 0000000..96a17f8 --- /dev/null +++ b/src/mainboard/google/rush/Kconfig @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_RUSH + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_NVIDIA_TEGRA132 + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default google/rush + +config MAINBOARD_PART_NUMBER + string + default "Rush" + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_GOOGLE_RUSH diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc new file mode 100644 index 0000000..94a0e28 --- /dev/null +++ b/src/mainboard/google/rush/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += romstage.c + +ramstage-y += mainboard.c \ No newline at end of file diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb new file mode 100644 index 0000000..73836a4 --- /dev/null +++ b/src/mainboard/google/rush/devicetree.cb @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/nvidia/tegra132 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c new file mode 100644 index 0000000..9b8e354 --- /dev/null +++ b/src/mainboard/google/rush/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <boot/coreboot_tables.h> + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "rush", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c new file mode 100644 index 0000000..e2b75f6 --- /dev/null +++ b/src/mainboard/google/rush/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +}

1 0

Patch set updated for coreboot: fdda2dd arm64: Prepare ARM64 for building
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8236 -gerrit commit fdda2dd5afd08f11913dba4609d06a1a726165f8 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jan 16 13:45:23 2015 -0700 arm64: Prepare ARM64 for building There were a number of issues with the ARM64 build files. This patch ports the following changes from ARMV4/V7 to ARMV8: - make armv8 Kconfig options consistent with armv4/v7 - fix build include issues in boot.c, tables.c, and early_variables.h by matching armv4/v7. Change-Id: I57359a96821d88c50f48dc0bb6ad226cacb0c2ec Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Iacd95d336559c45458784d1da67bde62a0956620 --- src/arch/arm64/Makefile.inc | 35 ++++++++++++++------------- src/arch/arm64/armv8/Kconfig | 8 +++--- src/arch/arm64/armv8/Makefile.inc | 9 ++++--- src/arch/arm64/boot.c | 7 +++--- src/arch/arm64/include/arch/early_variables.h | 4 --- src/arch/arm64/tables.c | 10 +++++--- 6 files changed, 39 insertions(+), 34 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 5bf72b2..75c256a 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -37,6 +37,16 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) CBFSTOOL_PRE1_OPTS = -m arm64 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET) endif +ifeq ($(CONFIG_ARCH_ARM64),y) +stages_c = $(src)/arch/arm/stages.c +stages_o = $(obj)/arch/arm/stages.o + +$(stages_o): $(stages_c) $(obj)/config.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_arm) -I. $(CPPFLAGS_arm) -c -o $@ $< -marm + +endif + ################################################################################ # bootblock ################################################################################ @@ -44,14 +54,11 @@ endif ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM64),y) bootblock-y += div0.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += early_console.c - bootblock-y += id.S $(obj)/arch/arm64/id.bootblock.o: $(obj)/build.h bootblock-y += stages.c bootblock-y += eabi_compat.c - bootblock-y += memset.S bootblock-y += memcpy.S bootblock-y += memmove.S @@ -60,7 +67,7 @@ bootblock-y += memmove.S $(objcbfs)/bootblock.debug: $(src)/arch/arm64/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) -nostdlib --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm64/bootblock.ld + $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm64/bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -72,7 +79,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM64),y) romstage-y += stages.c romstage-y += div0.c -romstage-y += early_console.c romstage-y += eabi_compat.c romstage-y += memset.S romstage-y += memcpy.S @@ -80,6 +86,7 @@ romstage-y += memmove.S romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c # Build the romstage +VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o $(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm64/romstage.ld $(obj)/ldoptions @printf " LINK $(subst $(obj)/,,$(@))\n" @@ -102,24 +109,18 @@ ramstage-y += tables.c ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S - -rmodules_$(ARCH-ramstage-y) += memset.S -rmodules_$(ARCH-ramstage-y) += memcpy.S -rmodules_$(ARCH-ramstage-y) += memmove.S -rmodules_$(ARCH-ramstage-y) += eabi_compat.c - -VBOOT_STUB_DEPS += $(obj)/arch/arm64/eabi_compat.rmodules.o - -$(eval $(call create_class_compiler,rmodules,arm64)) - ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c +ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) # Build the ramstage $(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm64/ramstage.ld $(obj)/ldoptions @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld + $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm64/ramstage.ld + +$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(LD_ramstage) -nostdlib --gc-sections -r -o $@ --start-group $(ramstage-objs) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index fc2e668..1dd2576 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -1,9 +1,11 @@ -config ARCH_BOOTBLOCK_ARM_V8_64 +config ARCH_BOOTBLOCK_ARMV8_64 def_bool n select ARCH_BOOTBLOCK_ARM64 -config ARCH_ROMSTAGE_ARM_V8_64 + +config ARCH_ROMSTAGE_ARMV8_64 def_bool n select ARCH_ROMSTAGE_ARM64 -config ARCH_RAMSTAGE_ARM_V8_64 + +config ARCH_RAMSTAGE_ARMV8_64 def_bool n select ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 973b391..c5f7a80 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -26,7 +26,7 @@ armv8_asm_flags = $(armv8_flags) ################################################################################ ## bootblock ################################################################################ -ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y) bootblock-y += bootblock.S @@ -46,7 +46,7 @@ endif ################################################################################ ## romstage ################################################################################ -ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) romstage-y += cache.c romstage-y += cpu.S @@ -61,7 +61,7 @@ endif ################################################################################ ## ramstage ################################################################################ -ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM_V8_64),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) ramstage-y += cache.c ramstage-y += cpu.S @@ -71,4 +71,7 @@ ramstage-y += exception_asm.S ramstage-c-ccopts += $(armv8_flags) ramstage-S-ccopts += $(armv8_asm_flags) +rmodules_arm64-c-ccopts += $(armv8_flags) +rmodules_arm64-S-ccopts += $(armv8_asm_flags) + endif diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 6fb0e65..85b2cce 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -21,13 +21,14 @@ #include <arch/stages.h> #include <cbmem.h> #include <console/console.h> +#include <payload_loader.h> -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) +void arch_payload_run(const struct payload *payload) { - void (*doit)(void *) = entry; + void (*doit)(void *) = payload->entry; void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE); - printk(BIOS_SPEW, "entry = %p\n", entry); + printk(BIOS_SPEW, "entry = %p\n", payload->entry); cache_sync_instructions(); doit(cb_tables); } diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 3d9fa26..5b58baa 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -20,10 +20,6 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if CONFIG_CAR_MIGRATION - #error "This is ARM, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index ce7ad5a..a2b7b9b 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -33,7 +33,11 @@ void cbmem_arch_init(void) { } -struct lb_memory *write_tables(void) +void cbmem_fail_resume(void) +{ +} + +void write_tables(void) { unsigned long table_pointer, new_table_pointer; @@ -43,7 +47,7 @@ struct lb_memory *write_tables(void) MAX_COREBOOT_TABLE_SIZE); if (!table_pointer) { printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return NULL; + return; } new_table_pointer = write_coreboot_table(0UL, 0UL, @@ -61,6 +65,4 @@ struct lb_memory *write_tables(void) /* Print CBMEM sections */ cbmem_list(); - - return get_lb_mem(); }

1 0

Patch set updated for coreboot: aff2fa0 xcompile: Rename aarch64 to arm64
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8235 -gerrit commit aff2fa0fa319a5de8b60c0c9cd2a699cf7eed572 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Jan 16 13:19:04 2015 -0700 xcompile: Rename aarch64 to arm64 coreboot toolchain.inc uses the ARCH_SUPPORTED variable set by xcompile. This change allows for consistent naming in the toolchain.inc generated variables. Change-Id: Iafed06cf2d19a533f99e10b76aca82adc3e09fa8 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- util/xcompile/xcompile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 45dae8c..47e4338 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -168,7 +168,7 @@ EOF } # Architecture definition -SUPPORTED_ARCHITECTURE="x86 arm aarch64 riscv" +SUPPORTED_ARCHITECTURE="x86 arm arm64 riscv" arch_config_arm() { TARCH="arm" @@ -179,8 +179,8 @@ arch_config_arm() { TABI="eabi" } -arch_config_aarch64() { - TARCH="aarch64" +arch_config_arm64() { + TARCH="arm64" TBFDARCH="littleaarch64" TCLIST="aarch64" TWIDTH="64"

1 0

Patch set updated for coreboot: f535320 tegra132: Add support for tegra132 soc
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8040 -gerrit commit f535320f4dc1c6da7fb6f80bc03d208f81e3be06 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Apr 28 16:43:07 2014 -0700 tegra132: Add support for tegra132 soc Add basic support for tegra132 soc. BUG=None BRANCH=None TEST=Compiles successfully for rush board using tegra132 soc Original-Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197398 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 4746bff6e9f4b20abc44d0b6fce9691aea63583c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: If2a3de80026e7729ac6da8484ff6c56607c52a63 --- src/soc/nvidia/Kconfig | 1 + src/soc/nvidia/Makefile.inc | 1 + src/soc/nvidia/tegra132/Kconfig | 24 ++ src/soc/nvidia/tegra132/Makefile.inc | 12 + src/soc/nvidia/tegra132/cbfs.c | 26 +++ src/soc/nvidia/tegra132/cbmem.c | 26 +++ src/soc/nvidia/tegra132/chip.h | 31 +++ src/soc/nvidia/tegra132/include/soc/addressmap.h | 83 +++++++ src/soc/nvidia/tegra132/include/soc/clock.h | 276 +++++++++++++++++++++++ src/soc/nvidia/tegra132/include/soc/display.h | 202 +++++++++++++++++ src/soc/nvidia/tegra132/timer.c | 31 +++ 11 files changed, 713 insertions(+) diff --git a/src/soc/nvidia/Kconfig b/src/soc/nvidia/Kconfig index 836edeb..cb1f468 100644 --- a/src/soc/nvidia/Kconfig +++ b/src/soc/nvidia/Kconfig @@ -1 +1,2 @@ source src/soc/nvidia/tegra124/Kconfig +source src/soc/nvidia/tegra132/Kconfig diff --git a/src/soc/nvidia/Makefile.inc b/src/soc/nvidia/Makefile.inc index 34feb0a..100cb94 100644 --- a/src/soc/nvidia/Makefile.inc +++ b/src/soc/nvidia/Makefile.inc @@ -1 +1,2 @@ subdirs-$(CONFIG_SOC_NVIDIA_TEGRA124) += tegra124 +subdirs-$(CONFIG_SOC_NVIDIA_TEGRA132) += tegra132 diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig new file mode 100644 index 0000000..df58f06 --- /dev/null +++ b/src/soc/nvidia/tegra132/Kconfig @@ -0,0 +1,24 @@ +config SOC_NVIDIA_TEGRA132 + bool + default n + select ARCH_BOOTBLOCK_ARMV4 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM_LPAE + select DYNAMIC_CBMEM + +if SOC_NVIDIA_TEGRA132 + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x18080 + +endif diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc new file mode 100644 index 0000000..e31bbb6 --- /dev/null +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -0,0 +1,12 @@ +bootblock-y += cbfs.c +bootblock-y += timer.c + +romstage-y += cbfs.c +romstage-y += cbmem.c +romstage-y += timer.c + +ramstage-y += cbfs.c +ramstage-y += cbmem.c +ramstage-y += timer.c + +CPPFLAGS_common += -Isrc/soc/nvidia/tegra132/include/ diff --git a/src/soc/nvidia/tegra132/cbfs.c b/src/soc/nvidia/tegra132/cbfs.c new file mode 100644 index 0000000..ac4a557 --- /dev/null +++ b/src/soc/nvidia/tegra132/cbfs.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cbfs.h> /* This driver serves as a CBFS media source. */ + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/nvidia/tegra132/cbmem.c b/src/soc/nvidia/tegra132/cbmem.c new file mode 100644 index 0000000..495fcba --- /dev/null +++ b/src/soc/nvidia/tegra132/cbmem.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ +/* TODO: update with real cbmem_top function. */ + return NULL; +} diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h new file mode 100644 index 0000000..394f0a4 --- /dev/null +++ b/src/soc/nvidia/tegra132/chip.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_CHIP_H__ +#define __SOC_NVIDIA_TEGRA132_CHIP_H__ +#include <arch/cache.h> +#include <soc/addressmap.h> + +#define EFAULT 1 +#define EINVAL 2 + +struct soc_nvidia_tegra132_config { +}; + +#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h new file mode 100644 index 0000000..d9d970a --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2014 Google Inc. + * + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ +#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ + +#include <stddef.h> + +enum { + TEGRA_SRAM_BASE = 0x40000000, + TEGRA_SRAM_SIZE = 0x40000 +}; + +enum { + TEGRA_ARM_PERIPHBASE = 0x50040000, + TEGRA_ARM_DISPLAYA = 0x54200000, + TEGRA_ARM_DISPLAYB = 0x54240000, + TEGRA_ARM_SOR = 0x54540000, + TEGRA_ARM_DPAUX = 0x545c0000, + TEGRA_PG_UP_BASE = 0x60000000, + TEGRA_TMRUS_BASE = 0x60005010, + TEGRA_CLK_RST_BASE = 0x60006000, + TEGRA_FLOW_BASE = 0x60007000, + TEGRA_GPIO_BASE = 0x6000D000, + TEGRA_EVP_BASE = 0x6000F000, + TEGRA_APB_DMA_BASE = 0x60020000, + TEGRA_APB_MISC_BASE = 0x70000000, + TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, + TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, + TEGRA_APB_PINMUX_BASE = TEGRA_APB_MISC_BASE + 0x3000, + TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000, + TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040, + TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200, + TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300, + TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400, + TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000, + TEGRA_PWM_BASE = TEGRA_APB_MISC_BASE + 0xA000, + TEGRA_I2C_BASE = TEGRA_APB_MISC_BASE + 0xC000, + TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380, + TEGRA_I2C2_BASE = TEGRA_APB_MISC_BASE + 0xC400, + TEGRA_I2C3_BASE = TEGRA_APB_MISC_BASE + 0xC500, + TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700, + TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000, + TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100, + TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400, + TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600, + TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800, + TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, + TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, + TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, + TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, + TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, + TEGRA_MC_BASE = 0x70019000, + TEGRA_EMC_BASE = 0x7001B000, + TEGRA_CSITE_BASE = 0x70040000, + TEGRA_SYSCTR0_BASE = 0x700F0000, + TEGRA_USBD_BASE = 0x7D000000, + TEGRA_USB2_BASE = 0x7D004000, + TEGRA_USB3_BASE = 0x7D008000, +}; + +enum { + TEGRA_I2C_BASE_COUNT = 6, +}; + +#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h new file mode 100644 index 0000000..5fc10c3 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -0,0 +1,276 @@ +/* + * Copyright 2014 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_CLOCK_H__ +#define __SOC_NVIDIA_TEGRA132_CLOCK_H__ + +#include <stdint.h> + +enum { + CLK_L_CPU = 0x1 << 0, + CLK_L_COP = 0x1 << 1, + CLK_L_TRIG_SYS = 0x1 << 2, + CLK_L_RTC = 0x1 << 4, + CLK_L_TMR = 0x1 << 5, + CLK_L_UARTA = 0x1 << 6, + CLK_L_UARTB = 0x1 << 7, + CLK_L_GPIO = 0x1 << 8, + CLK_L_SDMMC2 = 0x1 << 9, + CLK_L_SPDIF = 0x1 << 10, + CLK_L_I2S1 = 0x1 << 11, + CLK_L_I2C1 = 0x1 << 12, + CLK_L_NDFLASH = 0x1 << 13, + CLK_L_SDMMC1 = 0x1 << 14, + CLK_L_SDMMC4 = 0x1 << 15, + CLK_L_PWM = 0x1 << 17, + CLK_L_I2S2 = 0x1 << 18, + CLK_L_EPP = 0x1 << 19, + CLK_L_VI = 0x1 << 20, + CLK_L_2D = 0x1 << 21, + CLK_L_USBD = 0x1 << 22, + CLK_L_ISP = 0x1 << 23, + CLK_L_3D = 0x1 << 24, + CLK_L_DISP2 = 0x1 << 26, + CLK_L_DISP1 = 0x1 << 27, + CLK_L_HOST1X = 0x1 << 28, + CLK_L_VCP = 0x1 << 29, + CLK_L_I2S0 = 0x1 << 30, + CLK_L_CACHE2 = 0x1 << 31, + + CLK_H_MEM = 0x1 << 0, + CLK_H_AHBDMA = 0x1 << 1, + CLK_H_APBDMA = 0x1 << 2, + CLK_H_KBC = 0x1 << 4, + CLK_H_STAT_MON = 0x1 << 5, + CLK_H_PMC = 0x1 << 6, + CLK_H_FUSE = 0x1 << 7, + CLK_H_KFUSE = 0x1 << 8, + CLK_H_SBC1 = 0x1 << 9, + CLK_H_SNOR = 0x1 << 10, + CLK_H_JTAG2TBC = 0x1 << 11, + CLK_H_SBC2 = 0x1 << 12, + CLK_H_SBC3 = 0x1 << 14, + CLK_H_I2C5 = 0x1 << 15, + CLK_H_DSI = 0x1 << 16, + CLK_H_HSI = 0x1 << 18, + CLK_H_HDMI = 0x1 << 19, + CLK_H_CSI = 0x1 << 20, + CLK_H_I2C2 = 0x1 << 22, + CLK_H_UARTC = 0x1 << 23, + CLK_H_MIPI_CAL = 0x1 << 24, + CLK_H_EMC = 0x1 << 25, + CLK_H_USB2 = 0x1 << 26, + CLK_H_USB3 = 0x1 << 27, + CLK_H_MPE = 0x1 << 28, + CLK_H_VDE = 0x1 << 29, + CLK_H_BSEA = 0x1 << 30, + CLK_H_BSEV = 0x1 << 31, + + CLK_U_UARTD = 0x1 << 1, + CLK_U_UARTE = 0x1 << 2, + CLK_U_I2C3 = 0x1 << 3, + CLK_U_SBC4 = 0x1 << 4, + CLK_U_SDMMC3 = 0x1 << 5, + CLK_U_PCIE = 0x1 << 6, + CLK_U_OWR = 0x1 << 7, + CLK_U_AFI = 0x1 << 8, + CLK_U_CSITE = 0x1 << 9, + CLK_U_PCIEXCLK = 0x1 << 10, + CLK_U_AVPUCQ = 0x1 << 11, + CLK_U_TRACECLKIN = 0x1 << 13, + CLK_U_SOC_THERM = 0x1 << 14, + CLK_U_DTV = 0x1 << 15, + CLK_U_NAND_SPEED = 0x1 << 16, + CLK_U_I2C_SLOW = 0x1 << 17, + CLK_U_DSIB = 0x1 << 18, + CLK_U_TSEC = 0x1 << 19, + CLK_U_IRAMA = 0x1 << 20, + CLK_U_IRAMB = 0x1 << 21, + CLK_U_IRAMC = 0x1 << 22, + + // Clock reset. + CLK_U_EMUCIF = 0x1 << 23, + // Clock enable. + CLK_U_IRAMD = 0x1 << 23, + + CLK_U_CRAM2 = 0x2 << 24, + CLK_U_XUSB_HOST = 0x1 << 25, + CLK_U_MSENC = 0x1 << 27, + CLK_U_SUS_OUT = 0x1 << 28, + CLK_U_DEV2_OUT = 0x1 << 29, + CLK_U_DEV1_OUT = 0x1 << 30, + CLK_U_XUSB_DEV = 0x1 << 31, + + CLK_V_CPUG = 0x1 << 0, + CLK_V_CPULP = 0x1 << 1, + CLK_V_3D2 = 0x1 << 2, + CLK_V_MSELECT = 0x1 << 3, + CLK_V_I2S3 = 0x1 << 5, + CLK_V_I2S4 = 0x1 << 6, + CLK_V_I2C4 = 0x1 << 7, + CLK_V_SBC5 = 0x1 << 8, + CLK_V_SBC6 = 0x1 << 9, + CLK_V_AUDIO = 0x1 << 10, + CLK_V_APBIF = 0x1 << 11, + CLK_V_DAM0 = 0x1 << 12, + CLK_V_DAM1 = 0x1 << 13, + CLK_V_DAM2 = 0x1 << 14, + CLK_V_HDA2CODEC_2X = 0x1 << 15, + CLK_V_ATOMICS = 0x1 << 16, + CLK_V_ACTMON = 0x1 << 23, + CLK_V_EXTPERIPH1 = 0x1 << 24, + CLK_V_SATA = 0x1 << 28, + CLK_V_HDA = 0x1 << 29, + + CLK_W_HDA2HDMICODEC = 0x1 << 0, + CLK_W_SATACOLD = 0x1 << 1, + CLK_W_CEC = 0x1 << 8, + CLK_W_XUSB_PADCTL = 0x1 << 14, + CLK_W_ENTROPY = 0x1 << 21, + CLK_W_AMX0 = 0x1 << 25, + CLK_W_ADX0 = 0x1 << 26, + CLK_W_DVFS = 0x1 << 27, + CLK_W_XUSB_SS = 0x1 << 28, + CLK_W_MC1 = 0x1 << 30, + CLK_W_EMC1 = 0x1 << 31, + + CLK_X_AFC0 = 0x1 << 31, + CLK_X_AFC1 = 0x1 << 30, + CLK_X_AFC2 = 0x1 << 29, + CLK_X_AFC3 = 0x1 << 28, + CLK_X_AFC4 = 0x1 << 27, + CLK_X_AFC5 = 0x1 << 26, + CLK_X_AMX1 = 0x1 << 25, + CLK_X_GPU = 0x1 << 24, + CLK_X_SOR0 = 0x1 << 22, + CLK_X_DPAUX = 0x1 << 21, + CLK_X_ADX1 = 0x1 << 20, + CLK_X_VIC = 0x1 << 18, + CLK_X_CLK72MHZ = 0x1 << 17, + CLK_X_HDMI_AUDIO = 0x1 << 16, + CLK_X_EMC_DLL = 0x1 << 14, + CLK_X_VIM2_CLK = 0x1 << 11, + CLK_X_I2C6 = 0x1 << 6, + CLK_X_CAM_MCLK2 = 0x1 << 5, + CLK_X_CAM_MCLK = 0x1 << 4, + CLK_X_SPARE = 0x1 << 0, +}; + +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +#define IO_STABILIZATION_DELAY (2) +/* Calculate clock fractional divider value from ref and target frequencies. + * This is for a U7.1 format. This is not well written up in the book and + * there have been some questions about this macro, so here we go. + * U7.1 format is defined as (ddddddd+1) + (h*.5) + * The lowest order bit is actually a fractional bit. + * Hence, the divider can be thought of as 9 bits. + * So: + * divider = ((ref/freq) << 1 - 1) (upper 7 bits) | + * (ref/freq & 1) (low order half-bit) + * however we can't do fractional arithmetic ... these are integers! + * So we normalize by shifting the result left 1 bit, and extracting + * ddddddd and h directly to the returned u8. + * divider = 2*(ref/freq); + * We want to + * preserve 7 bits of divisor and one bit of fraction, in 8 bits, as well as + * subtract one from ddddddd. Since we computed ref*2, the dddddd is now nicely + * situated in the upper 7 bits, and the h is sitting there in the low order + * bit. To subtract 1 from ddddddd, just subtract 2 from the 8-bit number + * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you + * will assign this to a u8, it gets nicely truncated for you. + */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / (FREQ)) - 2) + +/* Calculate clock frequency value from reference and clock divider value + * The discussion in the book is pretty lacking. + * The idea is that we need to divide a ref clock by a divisor + * in U7.1 format, where 7 upper bits are the integer + * and lowest order bit is a fraction. + * from the book, U7.1 is (ddddddd+1) + (h*.5) + * To normalize to an actual number, we might do this: + * ((d>>7+1)&0x7f) + (d&1 >> 1) + * but as you might guess, the low order bit would be lost. + * Since we can't express the fractional bit, we need to multiply it all by 2. + * ((d + 2)&0xfe) + (d & 1) + * Since we're just adding +2, the lowest order bit is preserved. Hence + * (d+2) is the same as ((d + 2)&0xfe) + (d & 1) + * + * Since you multiply denominator * 2 (by NOT shifting it), + * you multiply numerator * 2 to cancel it out. + */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / ((REG) + 2)) + +#define clock_configure_irregular_source(device, src, freq, src_id) \ + clrsetbits_le32(&clk_rst->clk_src_##device, \ + CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \ + src_id << CLK_SOURCE_SHIFT | \ + CLK_DIVIDER(TEGRA_##src##_KHZ, freq)) + +/* Warning: Some devices just use different bits for the same sources for no + * apparent reason. *Always* double-check the TRM before trusting this macro. */ +#define clock_configure_source(device, src, freq) \ + clock_configure_irregular_source(device, src, freq, src) + +/* The I2C divisors are not 7.1 divisors like the others, they divide by n + 1 + * directly. Also, there are internal divisors in the I2C controller itself. + * We can deal with those here and make it easier to select what the actual + * bus frequency will be. The 0x19 value is the default divisor in the + * clk_divisor register in the controller, and 8 is just a magic number in the + * documentation. Multiplying by 2 compensates for the different format of the + * divisor. + */ +#define clock_configure_i2c_scl_freq(device, src, freq) \ + clock_configure_source(device, src, (freq) * (0x19 + 1) * 8 * 2) + +enum clock_source { /* Careful: Not true for all sources, always check TRM! */ + PLLP = 0, + PLLC2 = 1, + PLLC = 2, + PLLD = 2, + PLLC3 = 3, + PLLA = 3, + PLLM = 4, + PLLD2 = 5, + CLK_M = 6, +}; + +/* soc-specific */ +#define TEGRA_CLK_M_KHZ clock_get_osc_khz() +#define TEGRA_PLLX_KHZ CONFIG_PLLX_KHZ +#define TEGRA_PLLP_KHZ (408000) +#define TEGRA_PLLC_KHZ (600000) +#define TEGRA_PLLD_KHZ (925000) +#define TEGRA_PLLU_KHZ (960000) + +int clock_get_osc_khz(void); +void clock_early_uart(void); +void clock_external_output(int clk_id); +void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90, + u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source, + u32 same_freq); +void clock_cpu0_config_and_reset(void * entry); +void clock_halt_avp(void); +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x); +void clock_init(void); +void clock_init_arm_generic_timer(void); +void sor_clock_stop(void); +void sor_clock_start(void); + +#endif /* __SOC_NVIDIA_TEGRA132_CLOCK_H__ */ + diff --git a/src/soc/nvidia/tegra132/include/soc/display.h b/src/soc/nvidia/tegra132/include/soc/display.h new file mode 100644 index 0000000..2c21292 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/display.h @@ -0,0 +1,202 @@ +/* + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ +#define __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ + +/* ardisplay.h */ +#define DC_CMD_DISPLAY_WINDOW_HEADER_0 0x42 +#define DC_COM_CRC_CONTROL_0 0x300 +#define DC_COM_CRC_CHECKSUM_0 0x301 +#define DC_COM_PIN_OUTPUT_ENABLE0_0 0x302 +#define DC_COM_PIN_OUTPUT_ENABLE1_0 0x303 +#define DC_COM_PIN_OUTPUT_ENABLE2_0 0x304 +#define DC_COM_PIN_OUTPUT_ENABLE3_0 0x305 +#define DC_CMD_STATE_ACCESS_0 0x40 +#define DC_DISP_DISP_CLOCK_CONTROL_0 0x42e +#define DC_DISP_DISP_TIMING_OPTIONS_0 0x405 +#define DC_DISP_REF_TO_SYNC_0 0x406 +#define DC_DISP_SYNC_WIDTH_0 0x407 +#define DC_DISP_BACK_PORCH_0 0x408 +#define DC_DISP_DISP_ACTIVE_0 0x409 +#define DC_DISP_FRONT_PORCH_0 0x40a +#define DC_DISP_DISP_WIN_OPTIONS_0 0x402 +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT 25 +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD (0x1 << DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0 0x400 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0 0x4e4 +#define DC_CMD_DISPLAY_COMMAND_0 0x32 +#define DC_CMD_STATE_CONTROL_0 0x41 +#define DC_CMD_DISPLAY_POWER_CONTROL_0 0x36 + +/* ardisplay_a.h */ +#define DC_WIN_A_WIN_OPTIONS_0 0x700 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT 30 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD (0x1 << DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE (1) +#define DC_WIN_A_BYTE_SWAP_0 0x701 +#define DC_WIN_A_BUFFER_CONTROL_0 0x702 +#define DC_WIN_A_COLOR_DEPTH_0 0x703 +#define DC_WIN_A_POSITION_0 0x704 +#define DC_WIN_A_SIZE_0 0x705 +#define DC_WIN_A_PRESCALED_SIZE_0 0x706 +#define DC_WIN_A_H_INITIAL_DDA_0 0x707 +#define DC_WIN_A_V_INITIAL_DDA_0 0x708 +#define DC_WIN_A_DDA_INCREMENT_0 0x709 +#define DC_WIN_A_LINE_STRIDE_0 0x70a +#define DC_WIN_A_DV_CONTROL_0 0x70e +#define DC_WIN_A_BLEND_LAYER_CONTROL_0 0x716 +#define DC_WIN_A_BLEND_MATCH_SELECT_0 0x717 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0 0x718 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0 0x719 +#define DC_WINBUF_A_START_ADDR_LO_0 0x800 +#define DC_WINBUF_A_START_ADDR_HI_0 0x80d +#define DC_WINBUF_A_ADDR_H_OFFSET_0 0x806 +#define DC_WINBUF_A_ADDR_V_OFFSET_0 0x808 + +/* ardisplay_bd.h */ +#define DC_B_WIN_BD_SIZE_0 0xd85 +#define DC_B_WIN_BD_PRESCALED_SIZE_0 0xd86 +#define DC_B_WIN_BD_LINE_STRIDE_0 0xd8a +#define DC_B_WIN_BD_COLOR_DEPTH_0 0xd83 +#define DC_B_WINBUF_BD_START_ADDR_0 0xdc0 +#define DC_B_WIN_BD_DDA_INCREMENT_0 0xd89 +#define DC_B_WIN_BD_WIN_OPTIONS_0 0xd80 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT 30 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD (0x1 << DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE (1) + +/* arsor.h */ +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c +#define SOR_NV_PDISP_SOR_PLL0_0 0x17 +#define SOR_NV_PDISP_SOR_PLL1_0 0x18 +#define SOR_NV_PDISP_SOR_PLL2_0 0x19 +#define SOR_NV_PDISP_SOR_PLL3_0 0x1a +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT 22 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT 0 +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT 2 +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT 24 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT 23 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT 25 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD (0x1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 0x4e +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 0x52 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0 0x56 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 0x5c +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT 8 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD (0xff << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT 22 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0 0x1c +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 0x13 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0 0x4c +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0 0x21 +#define SOR_NV_PDISP_SOR_DP_TPG_0 0x6d +#define SOR_NV_PDISP_HEAD_STATE1_0 0x7 +#define SOR_NV_PDISP_HEAD_STATE2_0 0x9 +#define SOR_NV_PDISP_HEAD_STATE3_0 0xb +#define SOR_NV_PDISP_HEAD_STATE4_0 0xd +#define SOR_NV_PDISP_SOR_STATE1_0 0x4 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT 12 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT 13 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD (0x1 << SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT 8 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_LVDS_CUSTOM (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A (8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_B (9) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_CUSTOM (15) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_ACTIVE_RASTER (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_NON_ACTIVE_RASTER (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT 6 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT 4 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD (0x3 << SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD0 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD1 (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_BOTH (3) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT 0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_NONE (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD1 (2) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0 0x58 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT 24 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD (0x1 << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT 16 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD (0xf << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT 8 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT 0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD (0x3f << SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT 2 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD (0x7f << SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT 17 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD (0xf << SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULTVAL (0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_16_422 (1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444 (2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_20_422 (3) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_422 (4) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 (5) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_30_444 (6) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_32_422 (7) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_36_444 (8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_48_444 (9) + +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0 0x11 +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0 0x64 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0 0x60 +#define SOR_NV_PDISP_SOR_PWR_0 0x15 +#define SOR_NV_PDISP_SOR_STATE0_0 0x3 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0 0x2 +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0 0x1 + +/* ardpaux.h */ +#define DPAUX_DP_AUXDATA_READ_W0 0x19 + +#define DP_LVDS_SHIFT 25 +#define DP_LVDS (1 << DP_LVDS_SHIFT) + +#define SRC_BPP 16 +#define COLORDEPTH 0x6 +#define COLOR_WHITE 0xFFFFFF + +struct soc_nvidia_tegra132_config; /* forward declaration */ +void setup_display(struct soc_nvidia_tegra132_config *config); +void init_dca_regs(void); +void dp_io_powerup(void); +u32 dp_setup_timing(u32 width, u32 height); +void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, + u32 lane_count, u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); + +#define FB_SIZE_MB (32) + +#endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra132/timer.c b/src/soc/nvidia/tegra132/timer.c new file mode 100644 index 0000000..e2b0b82 --- /dev/null +++ b/src/soc/nvidia/tegra132/timer.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +void init_timer(void) +{ +} + +void udelay(unsigned usec) +{ +}

1 0

Patch set updated for coreboot: e2fb4a9 rush: Add support for rush board
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8041 -gerrit commit e2fb4a944543b52745fcfd2239fa23e9a4bb0636 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon Apr 28 16:44:21 2014 -0700 rush: Add support for rush board Add basic support for rush board BUG=None BRANCH=None TEST=Compiles successfully with soc tegra132 and armv8 arch selected for romstage and ramstage Original-Change-Id: Ica57c68d230e4e0e9916729752395843de188733 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/197399 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 06a040dc320d7b04ec0f7e51c1b3987c8f6d80f3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ica57c68d230e4e0e9916729752395843de188733 --- configs/config.rush | 4 ++++ src/mainboard/google/Kconfig | 3 +++ src/mainboard/google/rush/Kconfig | 39 +++++++++++++++++++++++++++++++++ src/mainboard/google/rush/Makefile.inc | 22 +++++++++++++++++++ src/mainboard/google/rush/devicetree.cb | 22 +++++++++++++++++++ src/mainboard/google/rush/mainboard.c | 35 +++++++++++++++++++++++++++++ src/mainboard/google/rush/romstage.c | 30 +++++++++++++++++++++++++ 7 files changed, 155 insertions(+) diff --git a/configs/config.rush b/configs/config.rush new file mode 100644 index 0000000..e34f216 --- /dev/null +++ b/configs/config.rush @@ -0,0 +1,4 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_RUSH=y +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_CONSOLE_SERIAL=y diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index e84cd7c..dd77bf3 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -47,6 +47,8 @@ config BOARD_GOOGLE_PEPPY bool "Peppy" config BOARD_GOOGLE_RAMBI bool "Rambi" +config BOARD_GOOGLE_RUSH + bool "Rush" config BOARD_GOOGLE_SAMUS bool "Samus" config BOARD_GOOGLE_SLIPPY @@ -71,6 +73,7 @@ source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/peach_pit/Kconfig" source "src/mainboard/google/peppy/Kconfig" source "src/mainboard/google/rambi/Kconfig" +source "src/mainboard/google/rush/Kconfig" source "src/mainboard/google/samus/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/storm/Kconfig" diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig new file mode 100644 index 0000000..10654e4 --- /dev/null +++ b/src/mainboard/google/rush/Kconfig @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_RUSH + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_NVIDIA_TEGRA132 + select BOARD_ROMSIZE_KB_4096 + +config MAINBOARD_DIR + string + default google/rush + +config MAINBOARD_PART_NUMBER + string + default "Rush" + +config DRAM_SIZE_MB + int + default 2048 + +endif # BOARD_GOOGLE_RUSH diff --git a/src/mainboard/google/rush/Makefile.inc b/src/mainboard/google/rush/Makefile.inc new file mode 100644 index 0000000..94a0e28 --- /dev/null +++ b/src/mainboard/google/rush/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += romstage.c + +ramstage-y += mainboard.c \ No newline at end of file diff --git a/src/mainboard/google/rush/devicetree.cb b/src/mainboard/google/rush/devicetree.cb new file mode 100644 index 0000000..73836a4 --- /dev/null +++ b/src/mainboard/google/rush/devicetree.cb @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/nvidia/tegra132 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/rush/mainboard.c b/src/mainboard/google/rush/mainboard.c new file mode 100644 index 0000000..9b8e354 --- /dev/null +++ b/src/mainboard/google/rush/mainboard.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <boot/coreboot_tables.h> + +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "rush", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/rush/romstage.c b/src/mainboard/google/rush/romstage.c new file mode 100644 index 0000000..e2b75f6 --- /dev/null +++ b/src/mainboard/google/rush/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + stage_exit(entry); +}

1 0

New patch to review for coreboot: 7043fc6 x86: Add amd/pi to the list of excluded .illegal_globals
by Dave Frodin 21 Jan '15

21 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8256 -gerrit commit 7043fc6f49ae2446f6c00ae293bc10d4be69a9fd Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 20 18:00:57 2015 -0700 x86: Add amd/pi to the list of excluded .illegal_globals Change-Id: I5167910ff790a3152a4ad8e5af0a4a3b17894f0f Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/arch/x86/init/romstage.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 99bcc8e..9468cfe 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -72,7 +72,7 @@ SECTIONS . = 0xffffff00; .illegal_globals . : { - *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */cpu/amd/agesa/*.romstage.o */vendorcode/amd/agesa/* */vendorcode/amd/cimx/*) .data) + *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */cpu/amd/agesa/*.romstage.o */vendorcode/amd/agesa/* */cpu/amd/pi/*.romstage.o */vendorcode/amd/pi/* */vendorcode/amd/cimx/*) .data) *(.data.*) *(.bss) *(.bss.*)

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coreboot-gerrit January 2015