coreboot-gerrit January 2015

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Patch set updated for coreboot: 95d6245 southbridge/amd/pi/hudson: Add new PCI identifiers for AMD Bolton
by Dave Frodin 22 Jan '15

22 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7246 -gerrit commit 95d62458345fafe1c14ae3c7045496c8e112d7e6 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 20 14:19:49 2015 -0700 southbridge/amd/pi/hudson: Add new PCI identifiers for AMD Bolton This also creates the CONFIG_SOUTHBRIDGE_AMD_BOLTON and separates avalon from bolton features. Change-Id: Iada3d3e1dae5b69d2721b7cd309533eb121d74ef Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/Makefile.inc | 2 + src/southbridge/amd/pi/Makefile.inc | 1 + src/southbridge/amd/pi/hudson/Kconfig | 8 +++- src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 58 +++++++++++++++++++++-- src/southbridge/amd/pi/hudson/amd_pci_int_types.h | 12 +++++ src/southbridge/amd/pi/hudson/lpc.c | 4 +- src/southbridge/amd/pi/hudson/pci_devs.h | 30 ++++++++++++ 7 files changed, 109 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 01a8ccc..cfb89d5 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -16,6 +16,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += pi +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += pi ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c @@ -23,3 +24,4 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += amd_pci_util.c diff --git a/src/southbridge/amd/pi/Makefile.inc b/src/southbridge/amd/pi/Makefile.inc index d8e492a..b23c9b3 100644 --- a/src/southbridge/amd/pi/Makefile.inc +++ b/src/southbridge/amd/pi/Makefile.inc @@ -17,3 +17,4 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) += hudson diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c0ca85a..9d1010f 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -17,13 +17,19 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config SOUTHBRIDGE_AMD_PI_BOLTON + bool + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_HARD_RESET + config SOUTHBRIDGE_AMD_PI_AVALON bool select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET -if SOUTHBRIDGE_AMD_PI_AVALON +if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index e6bd2da..9994ec5 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -25,6 +25,57 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) + +#define FCH_INT_TABLE_SIZE 0x54 + +#define PIRQ_NC 0x1F /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_ASF 0x12 /* ASF */ +#define PIRQ_HDA 0x13 /* HDA 14h.2 */ +#define PIRQ_SD 0x14 /* SD */ +#define PIRQ_GEC 0x15 /* GEC */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#define PIRQ_IMC0 0x20 /* IMC INT0 */ +#define PIRQ_IMC1 0x21 /* IMC INT1 */ +#define PIRQ_IMC2 0x22 /* IMC INT2 */ +#define PIRQ_IMC3 0x23 /* IMC INT3 */ +#define PIRQ_IMC4 0x24 /* IMC INT4 */ +#define PIRQ_IMC5 0x25 /* IMC INT5 */ +#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ +#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ +#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ +#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ +#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ +#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ +#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ +#define PIRQ_IDE 0x40 /* IDE 14h.1 */ +#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ +#endif + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) + #define FCH_INT_TABLE_SIZE 0x63 #define PIRQ_NC 0x1F /* Not Used */ @@ -41,9 +92,9 @@ #define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ #define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ #define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ #define PIRQ_SCI 0x10 /* SCI IRQ */ #define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ #define PIRQ_ASF 0x12 /* ASF */ @@ -68,5 +119,6 @@ #define PIRQ_IDE 0x40 /* IDE 14h.1 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ +#endif #endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h index d0fe9c8..517c892 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_types.h @@ -20,6 +20,17 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) const char * intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", @@ -29,5 +40,6 @@ const char * intr_types[] = { [0x40] = "RSVD\t", "SATA\t", [0x60] = "RSVD\t", "RSVD\t", "GPIO\t", }; +#endif #endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index d15a6d1..7e2ec00 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -328,8 +328,8 @@ static struct device_operations lpc_ops = { .read_resources = hudson_lpc_read_resources, .set_resources = hudson_lpc_set_resources, .enable_resources = hudson_lpc_enable_resources, -#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) && IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, .scan_bus = scan_static_bus, diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index d2549d4..c22f758 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -28,6 +28,11 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#define XHCI2_DEV 0x10 +#define XHCI2_FUNC 1 +#define XHCI2_DEVID 0x7814 +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) + /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -69,6 +74,14 @@ #define SMBUS_DEVID 0x780B #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) +/* IDE */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +# define IDE_DEVID 0x780C +# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) +#endif + /* HD Audio */ #define HDA_DEV 0x14 #define HDA_FUNC 2 @@ -93,4 +106,21 @@ #define SD_DEVID 0x7806 #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) +/* PCIe Ports */ +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON) +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) +#endif + #endif /* _PI_HUDSON_PCI_DEVS_H_ */

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Patch set updated for coreboot: 7224b90 AMD Bald Eagle: Add northbridge files for new AMD processor
by Dave Frodin 22 Jan '15

22 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7247 -gerrit commit 7224b908f2590eb0cbf60b395e4093cf7aa34df3 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed Oct 22 03:33:49 2014 -0600 AMD Bald Eagle: Add northbridge files for new AMD processor Also fix a typo in a config option for SteppeEagle. Change-Id: Iad51cc917217aa0eac751dc805c304652d20e066 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/include/device/pci_ids.h | 2 + src/northbridge/amd/pi/00630F01/Kconfig | 53 + src/northbridge/amd/pi/00630F01/Makefile.inc | 23 + .../amd/pi/00630F01/acpi/northbridge.asl | 70 ++ src/northbridge/amd/pi/00630F01/chip.h | 28 + src/northbridge/amd/pi/00630F01/dimmSpd.c | 59 + src/northbridge/amd/pi/00630F01/iommu.c | 73 ++ src/northbridge/amd/pi/00630F01/northbridge.c | 1296 ++++++++++++++++++++ src/northbridge/amd/pi/00630F01/northbridge.h | 26 + src/northbridge/amd/pi/00630F01/pci_devs.h | 56 + src/northbridge/amd/pi/BiosCallOuts.h | 2 +- src/northbridge/amd/pi/Kconfig | 1 + src/northbridge/amd/pi/Makefile.inc | 1 + src/northbridge/amd/pi/agesawrapper.h | 1 + src/northbridge/amd/pi/def_callouts.c | 4 +- 15 files changed, 1692 insertions(+), 3 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 061a11e..2c1734a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -286,10 +286,12 @@ #define PCI_DEVICE_ID_AMD_15H_MODEL_000F_NB_HT 0x1600 #define PCI_DEVICE_ID_AMD_15H_MODEL_001F_NB_HT 0x1400 +#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT 0x141A #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 #define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT 0x1566 #define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419 +#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig new file mode 100644 index 0000000..4e71895 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -0,0 +1,53 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +config NORTHBRIDGE_AMD_PI_00630F01 + bool + select MMCONF_SUPPORT + select PER_DEVICE_ACPI_TABLES + +if NORTHBRIDGE_AMD_PI_00630F01 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MMCONF_BASE_ADDRESS + hex + default 0xF8000000 + +config MMCONF_BUS_NUMBER + int + default 64 + +config VGA_BIOS_ID + string + default "1002,1304" + help + The default VGA BIOS PCI vendor/device ID should be set to the + result of the map_oprom_vendev() function in northbridge.c. + +config VGA_BIOS_FILE + string + default "3rdparty/northbridge/amd/00630F01/VBIOS.bin" + +endif diff --git a/src/northbridge/amd/pi/00630F01/Makefile.inc b/src/northbridge/amd/pi/00630F01/Makefile.inc new file mode 100644 index 0000000..5013364 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/Makefile.inc @@ -0,0 +1,23 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += dimmSpd.c + +ramstage-y += iommu.c +ramstage-y += northbridge.c diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl new file mode 100644 index 0000000..af69576 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Note: Only need HID on Primary Bus */ +External (TOM1) +External (TOM2) +Name(_HID, EISAID("PNP0A03")) /* PCI Express Root Bridge */ +Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + +/* Describe the Northbridge devices */ + +Method (_BBN, 0, NotSerialized) +{ + Return (Zero) +} + +Method (_STA, 0, NotSerialized) +{ + Return (0x0B) +} + +Method (_PRT, 0, NotSerialized) +{ + If (PMOD) + { + Return (APR0) + } + + Return (PR0) +} + +Device(AMRT) { + Name(_ADR, 0x00000000) +} /* end AMRT */ + +/* Dev2 is also an external GFX bridge */ +Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR2 */ + +/* Dev3 GPP Root Port Bridge */ +Device(PBR3) { + Name(_ADR, 0x00030000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS3) } /* APIC mode */ + Return (PS3) /* PIC Mode */ + } /* end _PRT */ +} /* end PBR3 */ diff --git a/src/northbridge/amd/pi/00630F01/chip.h b/src/northbridge/amd/pi/00630F01/chip.h new file mode 100644 index 0000000..5ddd5b9 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/chip.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AGESA_00630F01_CHIP_H_ +#define _AGESA_00630F01_CHIP_H_ + +struct northbridge_amd_pi_00630F01_config +{ + u8 spdAddrLookup[1][2][2]; +}; + +#endif diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c new file mode 100644 index 0000000..b698b00 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci_def.h> +#include <device/device.h> + +/* warning: Porting.h includes an open #pragma pack(1) */ +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include "chip.h" + +#include "northbridge/amd/pi/dimmSpd.h" + +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) +{ + int spdAddress; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + ROMSTAGE_CONST struct northbridge_amd_pi_00630F01_config *config = dev->chip_info; + + if ((dev == 0) || (config == 0)) + return AGESA_ERROR; + + if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + return AGESA_ERROR; + if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) + return AGESA_ERROR; + + spdAddress = config->spdAddrLookup + [info->SocketId] [info->MemChannelId] [info->DimmId]; + + if (spdAddress == 0) + return AGESA_ERROR; + + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + if (err) + return AGESA_ERROR; + return AGESA_SUCCESS; +} diff --git a/src/northbridge/amd/pi/00630F01/iommu.c b/src/northbridge/amd/pi/00630F01/iommu.c new file mode 100644 index 0000000..0813434 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/iommu.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> + +static void iommu_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, 0x44); + res->size = 512 * 1024; + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffff; /* 4G */ + res->flags = IORESOURCE_MEM; +} + +static void iommu_set_resources(device_t dev) +{ + struct resource *res; + + pci_dev_set_resources(dev); + + res = find_resource(dev, 0x44); + /* Remember this resource has been stored */ + res->flags |= IORESOURCE_STORED; + /* For now, do only 32-bit space allocation */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x44, res->base | (1 << 0)); +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations iommu_ops = { + .read_resources = iommu_read_resources, + .set_resources = iommu_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = 0, + .scan_bus = 0, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver iommu_driver __pci_driver = { + .ops = &iommu_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, +}; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c new file mode 100644 index 0000000..53ba694 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -0,0 +1,1296 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <lib.h> +#include <cpu/cpu.h> +#include <cbmem.h> + +#include <Porting.h> +#include <AGESA.h> +#include <FieldAccessors.h> +#include <Options.h> +#include <Topology.h> +#include <cpu/amd/amdfam15.h> +#include <cpuRegisters.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include "northbridge.h" + +#include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <assert.h> + +#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) + +#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1 +#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore! +#endif + +typedef struct dram_base_mask { + u32 base; //[47:27] at [28:8] + u32 mask; //[47:27] at [28:8] and enable at bit 0 +} dram_base_mask_t; + +static unsigned node_nums; +static unsigned sblink; +static device_t __f0_dev[MAX_NODE_NUMS]; +static device_t __f1_dev[MAX_NODE_NUMS]; +static device_t __f2_dev[MAX_NODE_NUMS]; +static device_t __f4_dev[MAX_NODE_NUMS]; +static unsigned fx_devs = 0; + +static dram_base_mask_t get_dram_base_mask(u32 nodeid) +{ + device_t dev; + dram_base_mask_t d; + dev = __f1_dev[0]; + u32 temp; + temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] + d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too + temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.mask |= temp<<21; + temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] + d.mask |= (temp & 1); // enable bit + d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too + temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] + d.base |= temp<<21; + return d; +} + +static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, + u32 io_min, u32 io_max) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? +#if 0 + // FIXME: can we use VGA reg instead? + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n", + __func__, dev_path(dev), link); + tempreg |= PCI_IO_BASE_VGA_EN; + } + if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) { + tempreg |= PCI_IO_BASE_NO_ISA; + } +#endif + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) +{ + u32 i; + u32 tempreg; + /* io range allocation */ + tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit + for (i=0; i<nodes; i++) + pci_write_config32(__f1_dev[i], reg+4, tempreg); + tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); + for (i=0; i<node_nums; i++) + pci_write_config32(__f1_dev[i], reg, tempreg); +} + +static device_t get_node_pci(u32 nodeid, u32 fn) +{ +#if MAX_NODE_NUMS + CONFIG_CDB >= 32 + if ((CONFIG_CDB + nodeid) < 32) { + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); + } else { + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); + } +#else + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); +#endif +} + +static void get_fx_devs(void) +{ + int i; + for (i = 0; i < MAX_NODE_NUMS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { + die("Cannot find 0:0x18.[0|1]\n"); + } + printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs); +} + +static u32 f1_read_config32(unsigned reg) +{ + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} + +static void f1_write_config32(unsigned reg, u32 value) +{ + int i; + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { + device_t dev; + dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } +} + +static u32 amdfam15_nodeid(device_t dev) +{ +#if MAX_NODE_NUMS == 64 + unsigned busn; + busn = dev->bus->secondary; + if (busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; + } else { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + } + +#else + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; +#endif +} + +static void set_vga_enable_reg(u32 nodeid, u32 linkn) +{ + u32 val; + + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing + * (1)mmio 0xa0000:0xbffff + * (2)io 0x3b0:0x3bb, 0x3c0:0x3df + */ + f1_write_config32(0xf4, val); + +} + +/** + * @return + * @retval 2 resource does not exist, usable + * @retval 0 resource exists, but is not usable + * @retval 1 resource exists, but has been allocated before + */ +static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, + unsigned goal_link) +{ + struct resource *res; + unsigned nodeid, link = 0; + int result; + res = 0; + for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev; + dev = __f0_dev[nodeid]; + if (!dev) + continue; + for (link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ((goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + return result; +} + +static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xd8) { + reg = free_reg; // if no free, the free_reg still be 0 + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + + return resource; +} + +static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for (reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } + + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; +} + +static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) +{ + struct resource *resource; + + /* Initialize the io space constraints on the current bus */ + resource = amdfam15_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } + + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } + + /* Initialize the memory constraints on the current bus */ + resource = amdfam15_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + +} + +static void read_resources(device_t dev) +{ + u32 nodeid; + struct bus *link; + + nodeid = amdfam15_nodeid(dev); + for (link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam15_link_read_bases(dev, nodeid, link->link_num); + } + } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ +#if CONFIG_MMCONF_SUPPORT + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +#endif +} + +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) +{ + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; + + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } + + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } + + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; + + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; + + /* Get the limit (rounded up) */ + rend = resource_end(resource); + + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); + + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8] + } + resource->flags |= IORESOURCE_STORED; + snprintf(buf, sizeof (buf), " <node %x link %x>", + nodeid, link_num); + report_resource_stored(dev, resource, buf); +} + +/** + * I tried to reuse the resource allocation code in set_resource() + * but it is too difficult to deal with the resource allocation magic. + */ + +static void create_vga_resource(device_t dev, unsigned nodeid) +{ + struct bus *link; + + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { +#if CONFIG_MULTIPLE_VGA_ADAPTERS + extern device_t vga_pri; // the primary vga device, defined in device.c + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate ) + ) +#endif + break; + } + } + + /* no VGA card installed */ + if (link == NULL) + return; + + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); + set_vga_enable_reg(nodeid, sblink); +} + +static void set_resources(device_t dev) +{ + unsigned nodeid; + struct bus *bus; + struct resource *res; + + /* Find the nodeid */ + nodeid = amdfam15_nodeid(dev); + + create_vga_resource(dev, nodeid); //TODO: do we need this? + + /* Set each resource we have found */ + for (res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } + + for (bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) { + assign_resources(bus); + } + } + + /* Print the MMCONF region if it has been reserved. */ + res = find_resource(dev, 0xc0010058); + if (res) { + report_resource_stored(dev, res, " <mmconfig>"); + } +} + +static void northbridge_init(struct device *dev) +{ +} + +unsigned long acpi_fill_hest(acpi_hest_t *hest) +{ + void *addr, *current; + + /* Skip the HEST header. */ + current = (void *)(hest + 1); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); + if (addr != NULL) + current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + + return (unsigned long)current; +} + +/* Implemented with AGESA-specific code. Dummy to keep linker happy. */ +unsigned long acpi_fill_slit(unsigned long current) +{ + return current; +} + +/* Implemented with AGESA-specific code. Dummy to keep linker happy. */ +unsigned long acpi_fill_srat(unsigned long current) +{ + return current; +} + +static void northbridge_fill_ssdt_generator(void) +{ + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_pop_len(); +} + +static unsigned long agesa_write_acpi_tables(unsigned long current, + acpi_rsdp_t *rsdp) +{ + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *alib; + acpi_header_t *ivrs; + acpi_hest_t *hest; + + /* HEST */ + current = ALIGN(current, 8); + hest = (acpi_hest_t *)current; + acpi_write_hest((void *)current); + acpi_add_table(rsdp, (void *)current); + current += ((acpi_header_t *)current)->length; + + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = agesawrapper_getlateinitptr(PICK_IVRS); + if (ivrs != NULL) { + memcpy((void *)current, ivrs, ivrs->length); + ivrs = (acpi_header_t *) current; + current += ivrs->length; + acpi_add_table(rsdp, ivrs); + } else { + printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); + } + + /* SRAT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + current += srat->header.length; + acpi_add_table(rsdp, srat); + } else { + printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); + } + + /* SLIT */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + current += slit->header.length; + acpi_add_table(rsdp, slit); + } else { + printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); + } + + /* ALIB */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + alib = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp, (void *)alib); + } + else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ + /* SSDT */ + current = ALIGN(current, 16); + printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } + else { + printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); + return current; +} + +static struct device_operations northbridge_operations = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, + .enable = 0, + .ops_pci = 0, +}; + +static const struct pci_driver family15_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT, +}; + +static const struct pci_driver family10_northbridge __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_10H_NB_HT, +}; + +struct chip_operations northbridge_amd_pi_00630F01_ops = { + CHIP_NAME("AMD FAM15 Northbridge") + .enable_dev = 0, +}; + +static void domain_read_resources(device_t dev) +{ + unsigned reg; + + /* Find the already assigned resource pairs */ + get_fx_devs(); + for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { + u32 base, limit; + base = f1_read_config32(reg); + limit = f1_read_config32(reg + 0x04); + /* Is this register allocated? */ + if ((base & 3) != 0) { + unsigned nodeid, reg_link; + device_t reg_dev; + if (reg<0xc0) { // mmio + nodeid = (limit & 0xf) + (base&0x30); + } else { // io + nodeid = (limit & 0xf) + ((base>>4)&0x30); + } + reg_link = (limit >> 4) & 7; + reg_dev = __f0_dev[nodeid]; + if (reg_dev) { + /* Reserve the resource */ + struct resource *res; + res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); + if (res) { + res->flags = 1; + } + } + } + } + /* FIXME: do we need to check extend conf space? + I don't believe that much preset value */ + +#if !CONFIG_PCI_64BIT_PREF_MEM + pci_domain_read_resources(dev); + +#else + struct bus *link; + struct resource *resource; + for (link=dev->link_list; link; link = link->next) { + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, 0|(link->link_num<<2)); + resource->base = 0x400; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO; + + /* Initialize the system wide prefetchable memory resources constraints */ + resource = new_resource(dev, 1|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, 2|(link->link_num<<2)); + resource->limit = 0xfcffffffffULL; + resource->flags = IORESOURCE_MEM; + } +#endif +} + +#if CONFIG_HAVE_ACPI_RESUME +extern u8 acpi_slp_type; +#endif + +static void domain_enable_resources(device_t dev) +{ + u32 val; +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type == 3) + agesawrapper_fchs3laterestore(); +#endif + + /* Must be called after PCI enumeration and resource allocation */ + printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); + } +#else + printk(BIOS_DEBUG, "agesawrapper_amdinitmid "); + val = agesawrapper_amdinitmid (); + if (val) + printk(BIOS_DEBUG, "error level: %x \n", val); + else + printk(BIOS_DEBUG, "passed.\n"); +#endif + + printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); +} + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 +struct hw_mem_hole_info { + unsigned hole_startk; + int node_id; +}; +static struct hw_mem_hole_info get_hw_mem_hole_info(void) +{ + struct hw_mem_hole_info mem_hole; + int i; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; + mem_hole.node_id = -1; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + u32 hole; + d = get_dram_base_mask(i); + if (!(d.mask & 1)) continue; // no memory on this node + hole = pci_read_config32(__f1_dev[i], 0xf0); + if (hole & 1) { // we find the hole + mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; + mem_hole.node_id = i; // record the node No with hole + break; // only one hole + } + } + + /* We need to double check if there is special set on base reg and limit reg + * are not continuous instead of hole, it will find out its hole_startk. + */ + if (mem_hole.node_id == -1) { + resource_t limitk_pri = 0; + for (i=0; i<node_nums; i++) { + dram_base_mask_t d; + resource_t base_k, limit_k; + d = get_dram_base_mask(i); + if (!(d.base & 1)) continue; + base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; + if (base_k > 4 *1024 * 1024) break; // don't need to go to check + if (limitk_pri != base_k) { // we find the hole + mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G + mem_hole.node_id = i; + break; //only one hole + } + limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; + limitk_pri = limit_k; + } + } + return mem_hole; +} +#endif + +#define ONE_MB_SHIFT 20 +#define ONE_GB_SHIFT 30 + +static void setup_uma_memory(void) +{ + uint64_t topmem = bsp_topmem(); + uint64_t topmem2 = bsp_topmem2(); + uint32_t sysmem_mb, sysmem_gb; + + sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; // Ignore 16MB allocated for C6 when finding UMA size + sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; + sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); + printk(BIOS_SPEW, "%s: system memory size %luGB, topmem2 size %lluMB, topmem size %lluMB\n", __func__, (unsigned long)sysmem_gb, (topmem2 >> ONE_MB_SHIFT), (topmem >> ONE_MB_SHIFT)); + + /* + * Refer to UMA_AUTO size computation in the Family15h BKDG. + * This calculation needs to exactly match the same calculation + * used by AGESA. + */ + + if (sysmem_gb >= 6) { + uma_memory_size = 1024 << ONE_MB_SHIFT; + } else if (sysmem_gb >= 4) { + uma_memory_size = 512 << ONE_MB_SHIFT; + } else { + uma_memory_size = 256 << ONE_MB_SHIFT; + } + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ + + printk(BIOS_INFO, "%s: uma size %lluMB, memory start 0x%08llx\n", + __func__, uma_memory_size >> ONE_MB_SHIFT, uma_memory_base); + + /* TODO: TOP_MEM2 */ +} + +static void domain_set_resources(device_t dev) +{ +#if CONFIG_PCI_64BIT_PREF_MEM + struct resource *io, *mem1, *mem2; + struct resource *res; +#endif + unsigned long mmio_basek; + u32 pci_tolm; + u64 ramtop = 0; + int i, idx; + struct bus *link; +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + struct hw_mem_hole_info mem_hole; + u32 reset_memhole = 1; +#endif + +#if CONFIG_PCI_64BIT_PREF_MEM + + for (link = dev->link_list; link; link = link->next) { + /* Now reallocate the pci resources memory with the + * highest addresses I can manage. + */ + mem1 = find_resource(dev, 1|(link->link_num<<2)); + mem2 = find_resource(dev, 2|(link->link_num<<2)); + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + + /* See if both resources have roughly the same limits */ + if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) || + ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff))) + { + /* If so place the one with the most stringent alignment first */ + if (mem2->align > mem1->align) { + struct resource *tmp; + tmp = mem1; + mem1 = mem2; + mem2 = tmp; + } + /* Now place the memory as high up as it will go */ + mem2->base = resource_max(mem2); + mem1->limit = mem2->base - 1; + mem1->base = resource_max(mem1); + } + else { + /* Place the resources as high up as they will go */ + mem2->base = resource_max(mem2); + mem1->base = resource_max(mem1); + } + + printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n", + mem1->base, mem1->limit, mem1->size, mem1->align); + printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n", + mem2->base, mem2->limit, mem2->size, mem2->align); + } + + for (res = &dev->resource_list; res; res = res->next) + { + res->flags |= IORESOURCE_ASSIGNED; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, ""); + } +#endif + + pci_tolm = 0xffffffffUL; + for (link = dev->link_list; link; link = link->next) { + pci_tolm = find_pci_tolm(link); + } + + // FIXME handle interleaved nodes. If you fix this here, please fix + // amdk8, too. + mmio_basek = pci_tolm >> 10; + /* Round mmio_basek to something the processor can support */ + mmio_basek &= ~((1 << 6) -1); + + // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M + // MMIO hole. If you fix this here, please fix amdk8, too. + /* Round the mmio hole to 64M */ + mmio_basek &= ~((64*1024) - 1); + +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 + /* if the hw mem hole is already set in raminit stage, here we will compare + * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will + * use hole_basek as mmio_basek and we don't need to reset hole. + * otherwise We reset the hole to the mmio_basek + */ + + mem_hole = get_hw_mem_hole_info(); + + // Use hole_basek as mmio_basek, and we don't need to reset hole anymore + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + mmio_basek = mem_hole.hole_startk; + reset_memhole = 0; + } +#endif + + idx = 0x10; + for (i = 0; i < node_nums; i++) { + dram_base_mask_t d; + resource_t basek, limitk, sizek; // 4 1T + + d = get_dram_base_mask(i); + + if (!(d.mask & 1)) continue; + basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here + limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9 ; + + sizek = limitk - basek; + + /* see if we need a hole from 0xa0000 to 0xbffff */ + if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { + ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); + idx += 0x10; + basek = (8*64)+(16*16); + sizek = limitk - ((8*64)+(16*16)); + + } + + //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); + + /* split the region to accommodate pci memory space */ + if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) { + if (basek <= mmio_basek) { + unsigned pre_sizek; + pre_sizek = mmio_basek - basek; + if (pre_sizek>0) { + ram_resource(dev, (idx | i), basek, pre_sizek); + idx += 0x10; + sizek -= pre_sizek; + if (!ramtop) + ramtop = mmio_basek * 1024; + } + basek = mmio_basek; + } + if ((basek + sizek) <= 4*1024*1024) { + sizek = 0; + } + else { + uint64_t topmem2 = bsp_topmem2(); + basek = 4*1024*1024; + sizek = topmem2/1024 - basek; + } + } + + ram_resource(dev, (idx | i), basek, sizek); + idx += 0x10; + printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", + i, mmio_basek, basek, limitk); + if (!ramtop) + ramtop = limitk * 1024; + } + +#if CONFIG_GFXUMA + set_top_of_ram(uma_memory_base); + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#else + set_top_of_ram(ramtop); +#endif + + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + assign_resources(link); + } + } +} + +static struct device_operations pci_domain_ops = { + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static void sysconf_init(device_t dev) // first node +{ + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 + node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] +} + +static void add_more_links(device_t dev, unsigned total_links) +{ + struct bus *link, *last = NULL; + int link_num; + + for (link = dev->link_list; link; link = link->next) + last = link; + + if (last) { + int links = total_links - last->link_num; + link_num = last->link_num; + if (links > 0) { + link = malloc(links*sizeof(*link)); + if (!link) + die("Couldn't allocate more links!\n"); + memset(link, 0, links*sizeof(*link)); + last->next = link; + } + } + else { + link_num = -1; + link = malloc(total_links*sizeof(*link)); + memset(link, 0, total_links*sizeof(*link)); + dev->link_list = link; + } + + for (link_num = link_num + 1; link_num < total_links; link_num++) { + link->link_num = link_num; + link->dev = dev; + link->next = link + 1; + last = link; + link = link->next; + } + last->next = NULL; +} + +static u32 cpu_bus_scan(device_t dev, u32 max) +{ + struct bus *cpu_bus; + device_t dev_mc; +#if CONFIG_CBB + device_t pci_domain; +#endif + int i,j; + int coreid_bits; + int core_max = 0; + unsigned ApicIdCoreIdSize; + unsigned core_nums; + int siblings = 0; + unsigned int family; + u32 modules = 0; + VOID* modules_ptr = &modules; + BUILD_OPT_CFG* options = NULL; + int ioapic_count = 0; + + // TODO Remove the printk's. + printk(BIOS_SPEW, "KaveriPI Debug: Grabbing the AMD Topology Information.\n"); + AmdGetValue(AMD_GLOBAL_USER_OPTIONS, (VOID**)&options, sizeof(options)); + AmdGetValue(AMD_GLOBAL_NUM_MODULES, &modules_ptr, sizeof(modules)); + modules = (*(u32*)modules_ptr) && ((1ull << (sizeof(modules) * 8)) - 1); + ASSERT(modules > 0); + ASSERT(options); + ioapic_count = (int)options->CfgPlatNumIoApics; + ASSERT(ioapic_count > 0); + printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); + printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics)); + +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { + printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s",dev_path(dev_mc)); + } else { + printk(BIOS_DEBUG, " but it is not under pci_domain directly "); + } + printk(BIOS_DEBUG, "\n"); + } + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + if (dev_mc && dev_mc->bus) { + printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc)); + pci_domain = dev_mc->bus->dev; + if (pci_domain && (pci_domain->path.type == DEVICE_PATH_DOMAIN)) { + if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + while (dev_mc) { + printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc)); + dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0); + printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc)); + dev_mc = dev_mc->sibling; + } + } + } + } + } +#endif + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + if (!dev_mc) { + printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + die(""); + } + sysconf_init(dev_mc); +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe + if (pci_domain->link_list && !pci_domain->link_list->next) { + struct bus *new_link = new_link(pci_domain); + pci_domain->link_list->next = new_link; + new_link->link_num = 1; + new_link->dev = pci_domain; + new_link->children = 0; + printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain)); + } + pci_domain->link_list->next->secondary = CONFIG_CBB - 1; + } +#endif + + /* Get Max Number of cores(MNC) */ + coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12; + core_max = 1 << (coreid_bits & 0x000F); //mnc + + ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); + if (ApicIdCoreIdSize) { + core_nums = (1 << ApicIdCoreIdSize) - 1; + } else { + core_nums = 3; //quad core + } + + /* Find which cpus are present */ + cpu_bus = dev->link_list; + for (i = 0; i < node_nums; i++) { + device_t cdb_dev; + unsigned busn, devn; + struct bus *pbus; + + busn = CONFIG_CBB; + devn = CONFIG_CDB + i; + pbus = dev_mc->bus; +#if CONFIG_CBB && (MAX_NODE_NUMS > 32) + if (i >= 32) { + busn--; + devn -= 32; + pbus = pci_domain->link_list->next; + } +#endif + + /* Find the cpu's pci device */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { + /* If I am probing things in a weird order + * ensure all of the cpu's pci devices are found. + */ + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); + } + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + } else { + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + int linknum; +#if IS_ENABLED(CONFIG_HT3_SUPPORT) + linknum = 8; +#else + linknum = 4; +#endif + add_more_links(cdb_dev, linknum); + } + + family = cpuid_eax(1); + family = (family >> 20) & 0xFF; + if (family == 1) { //f10 + u32 dword; + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + dword = pci_read_config32(cdb_dev, 0xe8); + siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); + } else if (family == 6) {//f15 + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5)); + if (cdb_dev && cdb_dev->enabled) { + siblings = pci_read_config32(cdb_dev, 0x84); + siblings &= 0xFF; + } + } else { + siblings = 0; //default one core + } + int enable_node = cdb_dev && cdb_dev->enabled; + printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n", + dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); + + for (j = 0; j <= siblings; j++ ) { + u32 lapicid_start = 0; + + /* + * APIC ID calucation is tightly coupled with AGESA v5 code. + * This calculation MUST match the assignment calculation done + * in LocalApicInitializationAtEarly() function. + * And reference GetLocalApicIdForCore() + * + * Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * + * This is needed because many IO-APIC devices only have 4 bits + * for their APIC id and therefore must reside at 0..15 + */ + if ((node_nums * core_max) + ioapic_count >= 0x10) { + lapicid_start = (ioapic_count - 1) / core_max; + lapicid_start = (lapicid_start + 1) * core_max; + printk(BIOS_SPEW, "lapicid_start=0x%x ", lapicid_start); + } + u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); + printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", + i, j, apic_id); + + device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node); + if (cpu) + amd_cpu_topology(cpu, i, j); + } //j + } + return max; +} + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static void cpu_bus_read_resources(device_t dev) +{ +} + +static void cpu_bus_set_resources(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + +static void root_complex_enable_dev(struct device *dev) +{ + static int done = 0; + + /* Do not delay UMA setup, as a device on the PCI bus may evaluate + the global uma_memory variables already in its enable function. */ + if (!done) { + setup_bsp_ramtop(); + setup_uma_memory(); + done = 1; + } + + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations northbridge_amd_pi_00630F01_root_complex_ops = { + CHIP_NAME("AMD FAM15 Root Complex") + .enable_dev = root_complex_enable_dev, +}; + +/******************************************************************** +* Change the vendor / device IDs to match the generic VBIOS header. +********************************************************************/ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev=vendev; + + if (vendev == 0x10021308) + ; /* Do nothing, this is the HDMI HD Audio device */ + else if ((0x10021300 <= vendev) && (vendev <= 0x1002131F)) { + new_vendev=0x10021304; + } + + if (vendev != new_vendev) + printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); + + return new_vendev; +} diff --git a/src/northbridge/amd/pi/00630F01/northbridge.h b/src/northbridge/amd/pi/00630F01/northbridge.h new file mode 100644 index 0000000..0d91d5a --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/northbridge.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H +#define NORTHBRIDGE_AMD_AGESA_FAM15H_H + +static struct device_operations pci_domain_ops; +static struct device_operations cpu_bus_ops; + +#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */ diff --git a/src/northbridge/amd/pi/00630F01/pci_devs.h b/src/northbridge/amd/pi/00630F01/pci_devs.h new file mode 100644 index 0000000..4680621 --- /dev/null +++ b/src/northbridge/amd/pi/00630F01/pci_devs.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_00630F01_PCI_DEVS_H_ +#define _AMD_00630F01_PCI_DEVS_H_ + +#define BUS0 0 + +/* Graphics and Display */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVID 0x1304 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC) +#define PIRQ_GFX FCH_INT_TABLE_SIZE + /* Integrated graphics device, must be after the + * last C00/C01 entry + */ + +/* Internal Audio controller */ +#define ACTL_DEV 0x1 +#define ACTL_FUNC 1 +#define ACTL_DEVID 0x1308 +#define ACTL_DEVFN PCI_DEVFN(ACTL_DEV,ACTL_FUNC) +#define PIRQ_ACTL FCH_INT_TABLE_SIZE+1 + /* Integrated HDMI audio device, must be after the + * last C00/C01 entry + */ + +/* PCIe Ports */ +#define NB_GFX_PCIE_PORTS_DEV 0x2 +#define NB_GPP_PCIE_PORTS_DEV 0x3 +#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_GFX_PCIE_PORTS_DEV,0x01) +#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_GFX_PCIE_PORTS_DEV,0x02) +#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x01) +#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x02) +#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x03) +#define NB_PCIE_PORT6_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x04) +#define NB_PCIE_PORT7_DEVFN PCI_DEVFN(NB_GPP_PCIE_PORTS_DEV,0x05) + +#endif /* _AMD_00630F01_PCI_DEVS_H_ */ diff --git a/src/northbridge/amd/pi/BiosCallOuts.h b/src/northbridge/amd/pi/BiosCallOuts.h index feabf98..6e32afe 100644 --- a/src/northbridge/amd/pi/BiosCallOuts.h +++ b/src/northbridge/amd/pi/BiosCallOuts.h @@ -24,7 +24,7 @@ #include "Porting.h" #include "AGESA.h" -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB +#if CONFIG_NORTHBRIDGE_AMD_PI_00630F01 || CONFIG_NORTHBRIDGE_AMD_PI_00730F01 #define BIOS_HEAP_START_ADDRESS 0x010000000 #define BIOS_HEAP_SIZE 0x30000 diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 8af4872..8aa6cce 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -31,6 +31,7 @@ config S3_VGA_ROM_RUN bool default n +source src/northbridge/amd/pi/00630F01/Kconfig source src/northbridge/amd/pi/00730F01/Kconfig endif # NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index 294673c..26c7ed9 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 romstage-y += def_callouts.c diff --git a/src/northbridge/amd/pi/agesawrapper.h b/src/northbridge/amd/pi/agesawrapper.h index eefde35..d62e766 100644 --- a/src/northbridge/amd/pi/agesawrapper.h +++ b/src/northbridge/amd/pi/agesawrapper.h @@ -33,6 +33,7 @@ enum { PICK_WHEA_CMC, /* WHEA CMV table */ PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ + PICK_CRAT, }; AGESA_STATUS agesawrapper_amdinitreset(void); diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index 225bf53..2caf183 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -110,8 +110,8 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt pVbiosImageInfo->ImagePtr = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM, NULL); - /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ - return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; + printk(BIOS_DEBUG, "agesa_GfxGetVbiosImage: IMGptr=%p\n", pVbiosImageInfo->ImagePtr); + return (pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING); } AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)

1 0

Patch set updated for coreboot: 4516fc9 AMD Bald Eagle: Add CPU subdirectory files for new AMD processor
by Dave Frodin 22 Jan '15

22 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7248 -gerrit commit 4516fc96cd9cb98ba6e5370ff08e7e412c8b49fd Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Wed Oct 22 03:37:57 2014 -0600 AMD Bald Eagle: Add CPU subdirectory files for new AMD processor Change-Id: Ifef55747a5d715b17937fc75ab9d35945b59f0e6 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/cpu/amd/pi/00630F01/Kconfig | 69 +++++++++++++++ src/cpu/amd/pi/00630F01/Makefile.inc | 32 +++++++ src/cpu/amd/pi/00630F01/acpi/cpu.asl | 111 +++++++++++++++++++++++ src/cpu/amd/pi/00630F01/chip_name.c | 24 +++++ src/cpu/amd/pi/00630F01/model_15_init.c | 150 ++++++++++++++++++++++++++++++++ src/cpu/amd/pi/00630F01/udelay.c | 45 ++++++++++ src/cpu/amd/pi/Kconfig | 2 + src/cpu/amd/pi/Makefile.inc | 1 + src/cpu/amd/pi/heapmanager.c | 4 +- 9 files changed, 436 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig new file mode 100644 index 0000000..4c578d4 --- /dev/null +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -0,0 +1,69 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +config CPU_AMD_PI_00630F01 + bool + select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS + +if CPU_AMD_PI_00630F01 + +config CPU_ADDR_BITS + int + default 48 + +config CPU_SOCKET_TYPE + hex + default 0x10 + +# DDR2 and REG +config DIMM_SUPPORT + hex + default 0x0104 + +config EXT_RT_TBL_SUPPORT + bool + default n + +config EXT_CONF_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_BASE + hex + default 0xfff80000 + +config XIP_ROM_SIZE + hex + default 0x100000 + +config HIGH_SCRATCH_MEMORY_SIZE + hex + # Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000) + default 0x71000 + +endif diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc new file mode 100644 index 0000000..a8f644d --- /dev/null +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -0,0 +1,32 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +ramstage-y += chip_name.c +ramstage-y += model_15_init.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c + +subdirs-y += ../../mtrr +subdirs-y += ../../smm +subdirs-y += ../../../x86/tsc +subdirs-y += ../../../x86/lapic +subdirs-y += ../../../x86/cache +subdirs-y += ../../../x86/mtrr +subdirs-y += ../../../x86/pae +subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl new file mode 100644 index 0000000..c15e58c --- /dev/null +++ b/src/cpu/amd/pi/00630F01/acpi/cpu.asl @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + P000, /* name space name */ + 0, /* Unique core number for this processor within a socket */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + + Processor( + P001, /* name space name */ + 1, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P002, /* name space name */ + 2, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P003, /* name space name */ + 3, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P004, /* name space name */ + 4, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P005, /* name space name */ + 5, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P006, /* name space name */ + 6, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P007, /* name space name */ + 7, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P008, /* name space name */ + 8, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P009, /* name space name */ + 9, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P010, /* name space name */ + 10, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + Processor( + P011, /* name space name */ + 11, /* Unique core number for this processor within a socket */ + 0x0810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + } + } /* End _PR scope */ + diff --git a/src/cpu/amd/pi/00630F01/chip_name.c b/src/cpu/amd/pi/00630F01/chip_name.c new file mode 100644 index 0000000..fa2941a --- /dev/null +++ b/src/cpu/amd/pi/00630F01/chip_name.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +struct chip_operations cpu_amd_pi_00630F01_ops = { + CHIP_NAME("AMD CPU Family 15h Model 30") +}; diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c new file mode 100644 index 0000000..d100a35 --- /dev/null +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> +#include <cpu/amd/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/pae.h> +#include <pc80/mc146818rtc.h> +#include <cpu/x86/lapic.h> + +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/amd/amdfam15.h> +#include <arch/acpi.h> +#if CONFIG_HAVE_ACPI_RESUME +#include <cpu/amd/pi/s3_resume.h> +#endif + +static void model_15_init(device_t dev) +{ + printk(BIOS_DEBUG, "Model 15 Init.\n"); + + u8 i; + msr_t msr; + int msrno; + unsigned int cpu_idx; +#if CONFIG_LOGICAL_CPUS + u32 siblings; +#endif + + //x86_enable_cache(); + //amd_setup_mtrrs(); + //x86_mtrr_check(); + disable_cache (); + /* Enable access to AMD RdDram and WrDram extension bits */ + msr = rdmsr(SYSCFG_MSR); + msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; + msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + + // BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs + msr.lo = msr.hi = 0; + wrmsr (0x259, msr); + msr.lo = msr.hi = 0x1e1e1e1e; + wrmsr(0x250, msr); + wrmsr(0x258, msr); + for (msrno = 0x268; msrno <= 0x26f; msrno++) + wrmsr (msrno, msr); + + msr = rdmsr(SYSCFG_MSR); + msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + msr.lo |= SYSCFG_MSR_MtrrFixDramEn; + wrmsr(SYSCFG_MSR, msr); + +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type == 3) + restore_mtrr(); +#endif + + x86_mtrr_check(); + x86_enable_cache(); + + /* zero the machine check error status registers */ + msr.lo = 0; + msr.hi = 0; + for (i = 0; i < 6; i++) { + wrmsr(MCI_STATUS + (i * 4), msr); + } + + + /* Enable the local cpu apics */ + setup_lapic(); + +#if CONFIG_LOGICAL_CPUS + siblings = cpuid_ecx(0x80000008) & 0xff; + + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); +#endif + + /* DisableCf8ExtCfg */ + msr = rdmsr(NB_CFG_MSR); + msr.hi &= ~(1 << (46 - 32)); + wrmsr(NB_CFG_MSR, msr); + + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + cpu_idx = cpu_info()->index; + printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx); + + /* Set SMM base address for this CPU */ + msr = rdmsr(MSR_SMM_BASE); + msr.lo = SMM_BASE - (cpu_idx * 0x400); + wrmsr(MSR_SMM_BASE, msr); + + /* Enable the SMM memory window */ + msr = rdmsr(MSR_SMM_MASK); + msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */ + wrmsr(MSR_SMM_MASK, msr); + } + + /* Write protect SMM space with SMMLOCK. */ + msr = rdmsr(HWCR_MSR); + msr.lo |= (1 << 0); + wrmsr(HWCR_MSR, msr); +} + +static struct device_operations cpu_dev_ops = { + .init = model_15_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x630f00 }, /* KV-A0 */ + { X86_VENDOR_AMD, 0x630f01 }, /* KV-A1 */ + { 0, 0 }, +}; + +static const struct cpu_driver model_15 __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/cpu/amd/pi/00630F01/udelay.c b/src/cpu/amd/pi/00630F01/udelay.c new file mode 100644 index 0000000..5873237 --- /dev/null +++ b/src/cpu/amd/pi/00630F01/udelay.c @@ -0,0 +1,45 @@ +/* + * udelay() impementation for SMI handlers + * This is neat in that it never writes to hardware registers, and thus does not + * modify the state of the hardware while servicing SMIs. + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <delay.h> +#include <stdint.h> + +void udelay(uint32_t us) +{ + uint8_t fid, did, pstate_idx; + uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks; + msr_t msr; + const uint64_t tsc_base = 100000000; + + /* Get initial timestamp before we do the math */ + tsc_start = rdtscll(); + + /* Get the P-state. This determines which MSR to read */ + msr = rdmsr(0xc0010063); + pstate_idx = msr.lo & 0x07; + + /* Get FID and VID for current P-State */ + msr = rdmsr(0xc0010064 + pstate_idx); + + /* Extract the FID and VID values */ + fid = msr.lo & 0x3f; + did = (msr.lo >> 6) & 0x7; + + /* Calculate the CPU clock (from base freq of 100MHz) */ + tsc_clock = tsc_base * (fid + 0x10) / (1 << did); + + /* Now go on and wait */ + tsc_wait_ticks = (tsc_clock / 1000000) * us; + + do { + tsc_now = rdtscll(); + } while (tsc_now - tsc_wait_ticks < tsc_start); +} diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 366beb4..0cba97f 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -19,6 +19,7 @@ config CPU_AMD_PI bool + default y if CPU_AMD_PI_00630F01 default y if CPU_AMD_PI_00730F01 default n select ARCH_BOOTBLOCK_X86_32 @@ -73,4 +74,5 @@ config S3_DATA_SIZE endif # CPU_AMD_PI +source src/cpu/amd/pi/00630F01/Kconfig source src/cpu/amd/pi/00730F01/Kconfig diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 8228b12..4909e3e 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 romstage-y += s3_resume.c diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index aa251e0..22c72fb 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -28,7 +28,7 @@ void EmptyHeap(void) memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); } -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) #define AGESA_RUNTIME_SIZE 4096 @@ -74,7 +74,7 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) /* if the allocation is for runtime use simple CBMEM data */ if (Data == HEAP_CALLOUT_RUNTIME) return alloc_cbmem(AllocParams);

1 0

Patch set updated for coreboot: 3a19089 AMD Lamar: Add a new AMD FP3 socket mainboard
by Dave Frodin 22 Jan '15

22 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5968 -gerrit commit 3a19089a35d1c8789285b200c80e787952339e8f Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 10 05:10:19 2014 -0600 AMD Lamar: Add a new AMD FP3 socket mainboard Add a new mainboard based on AMD's Family 15 Model 30 processor. The board will boot DOS, Ubuntu 14.10 and Windows 7. Change-Id: I2f73c396247239d54f978846e8958950697d7464 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/amd/Kconfig | 3 + src/mainboard/amd/lamar/BiosCallOuts.c | 353 +++++++++++++++ src/mainboard/amd/lamar/Kconfig | 102 +++++ src/mainboard/amd/lamar/Makefile.inc | 26 ++ src/mainboard/amd/lamar/PlatformGnbPcie.c | 138 ++++++ src/mainboard/amd/lamar/acpi/AmdImc.asl | 115 +++++ src/mainboard/amd/lamar/acpi/gpe.asl | 77 ++++ src/mainboard/amd/lamar/acpi/mainboard.asl | 43 ++ src/mainboard/amd/lamar/acpi/routing.asl | 231 ++++++++++ src/mainboard/amd/lamar/acpi/sata.asl | 1 + src/mainboard/amd/lamar/acpi/si.asl | 28 ++ src/mainboard/amd/lamar/acpi/sleep.asl | 103 +++++ src/mainboard/amd/lamar/acpi/superio.asl | 1 + src/mainboard/amd/lamar/acpi/thermal.asl | 1 + src/mainboard/amd/lamar/acpi/usb_oc.asl | 31 ++ src/mainboard/amd/lamar/acpi_tables.c | 59 +++ src/mainboard/amd/lamar/agesawrapper.c | 679 +++++++++++++++++++++++++++++ src/mainboard/amd/lamar/board_info.txt | 5 + src/mainboard/amd/lamar/cmos.layout | 114 +++++ src/mainboard/amd/lamar/devicetree.cb | 118 +++++ src/mainboard/amd/lamar/dsdt.asl | 91 ++++ src/mainboard/amd/lamar/get_bus_conf.c | 150 +++++++ src/mainboard/amd/lamar/irq_tables.c | 112 +++++ src/mainboard/amd/lamar/mainboard.c | 208 +++++++++ src/mainboard/amd/lamar/mptable.c | 170 ++++++++ src/mainboard/amd/lamar/romstage.c | 138 ++++++ 26 files changed, 3097 insertions(+) diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig index cc5679a..8ae8be7 100644 --- a/src/mainboard/amd/Kconfig +++ b/src/mainboard/amd/Kconfig @@ -41,6 +41,8 @@ config BOARD_AMD_PARMER bool "Parmer" config BOARD_AMD_THATCHER bool "Thatcher" +config BOARD_AMD_LAMAR + bool "Lamar" config BOARD_AMD_OLIVEHILL bool "Olive Hill" config BOARD_AMD_OLIVEHILLPLUS @@ -66,6 +68,7 @@ source "src/mainboard/amd/torpedo/Kconfig" source "src/mainboard/amd/union_station/Kconfig" source "src/mainboard/amd/parmer/Kconfig" source "src/mainboard/amd/thatcher/Kconfig" +source "src/mainboard/amd/lamar/Kconfig" source "src/mainboard/amd/olivehill/Kconfig" source "src/mainboard/amd/olivehillplus/Kconfig" diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c new file mode 100644 index 0000000..f9d76ee --- /dev/null +++ b/src/mainboard/amd/lamar/BiosCallOuts.c @@ -0,0 +1,353 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/pi/BiosCallOuts.h> +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "cbfs.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif +#include "hudson.h" +#include <stdlib.h> +#include <device/azalia.h> + +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, + {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * Realtek ALC272 CODEC Verb Table + */ +static const CODEC_ENTRY Alc272_VerbTbl[] = { + { 0x11, 0x411111F0 }, /* - S/PDIF Output 2 */ + { 0x12, 0x411111F0 }, /* - Digital Mic 1/2 [GPIO0] */ + { 0x13, 0x411111F0 }, /* - Digital Mic 3/4 [GPIO1] */ + { 0x14, 0x411111F0 }, /* Port D - Front Panel headphone */ + { 0x15, 0x411111F0 }, /* Port A - Surround */ + { 0x17, 0x411111F0 }, /* Port H - Mono */ + { 0x18, /* Port B - MIC - pink jack */ + (AZALIA_PINCFG_PORT_JACK << 30) + | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) + | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) + | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) + | (AZALIA_PINCFG_COLOR_PINK << 12) + | (4 << 4) + | (0 << 0) + }, + { 0x19, 0x411111F0 }, /* Port F - Front Panel Mic */ + { 0x1A, /* Port C - LineIn1 - blue jack */ + (AZALIA_PINCFG_PORT_JACK << 30) + | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) + | (AZALIA_PINCFG_DEVICE_LINEIN << 20) + | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) + | (AZALIA_PINCFG_COLOR_BLUE << 12) + | (4 << 4) + | (0xF << 0) + }, + { 0x1B, 0x411111F0 }, /* Port E - Front Panel line-out */ + { 0x1D, 0x40251E05 }, /* PC Beep - (internal) */ + { 0x1E, /* S/PDIF - Internal Header */ + (AZALIA_PINCFG_PORT_JACK << 30) + | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) + | (AZALIA_PINCFG_DEVICE_SPDIF_OUT << 20) + | (AZALIA_PINCFG_CONN_RCA << 16) + | (AZALIA_PINCFG_COLOR_BLACK << 12) + | (1 << 4) + | (0 << 0) + }, + { 0x21, /* Port I - HPout - green jack */ + (AZALIA_PINCFG_PORT_JACK << 30) + | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) + | (AZALIA_PINCFG_DEVICE_HP_OUT << 20) + | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) + | (AZALIA_PINCFG_COLOR_GREEN << 12) + | (4 << 4) + | (0 << 0) + }, + { 0xFF, 0xFFFFFFFF }, +}; + +static const CODEC_TBL_LIST CodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF + +/* + * Hardware Monitor Fan Control + * Hardware limitation: + * HWM will fail to read the input temperature via I2C if other + * software switches the I2C address. AMD recommends using IMC + * to control fans, instead of HWM. + */ +static void oem_fan_control(FCH_DATA_BLOCK *FchParams) +{ + FCH_HWM_FAN_CTR oem_factl[5] = { + /*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ + /* FanOUT0 Fan header J32 */ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + /* FanOUT1 Fan header J31*/ + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, + }; + LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); + + /* Enable IMC fan control. the recommended way */ +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + + imc_reg_init(); + + /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */ + + FchParams->Imc.ImcEnable = TRUE; + FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ + FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ + + LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); + + /* Thermal Zone Parameter */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; //6 | BIT3; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02; + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; + + /* IMC Fan Policy temperature thresholds */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; + + /* IMC Fan Policy PWM Settings */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ + FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; + + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ + FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ + + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; + + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0; //BIT0 | BIT2 | BIT5; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ + FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; + + /* IMC Function */ + FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; + + /* NOTE: + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA put EcDefaultMessage as global data in ROM, so we can't override it. + * so we remove it from AGESA code. Please See FchInitLateHwm. + */ + +#else /* HWM fan control, using the alternative method */ + FchParams->Imc.ImcEnable = FALSE; + FchParams->Hwm.HwMonitorEnable = TRUE; + FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ + +#endif /* CONFIG_HUDSON_IMC_FWM */ +} + +/** + * Fch Oem setting callback + * + * Configure platform specific Hudson device, + * such Azalia, SATA, IMC etc. + */ +static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) +{ + AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; + if (StdHeader->Func == AMD_INIT_RESET) { + FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; + printk(BIOS_DEBUG, "\nFch OEM config in INIT RESET\n"); + //FchParams->EcChannel0 = TRUE; /* logical devicd 3 */ +#if CONFIG_HUDSON_LEGACY_FREE + FchParams->LegacyFree = 1; +#endif + + /* Turn on FCH GPP slots */ + FchParams->FchReset.GppEnable = TRUE; + FchParams->Gpp.GppFunctionEnable = TRUE; + FchParams->Gpp.GppLinkConfig = PortA1B1C1D1; + FchParams->Gpp.PortCfg[0].PortPresent = TRUE; + FchParams->Gpp.PortCfg[1].PortPresent = TRUE; + FchParams->Gpp.PortCfg[2].PortPresent = TRUE; + FchParams->Gpp.PortCfg[3].PortPresent = TRUE; + +#if CONFIG_HUDSON_SATA_IDE || CONFIG_HUDSON_SATA_AHCI + FchParams->FchReset.SataEnable = TRUE; +#else + FchParams->FchReset.SataEnable = FALSE; +#endif +#if CONFIG_HUDSON_SATA_IDE || CONFIG_HUDSON_SATA_LEGACY_IDE + FchParams->FchReset.IdeEnable = TRUE; +#else + FchParams->FchReset.IdeEnable = FALSE; +#endif + } else if (StdHeader->Func == AMD_INIT_ENV) { + FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV"); + + /* Turn on FCH GPP slots */ + FchParams->Gpp.GppFunctionEnable = TRUE; + FchParams->Gpp.GppLinkConfig = PortA1B1C1D1; + + /* Azalia Controller OEM Codec Table Pointer */ + FchParams->Azalia.AzaliaPinCfg = TRUE; + FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){ + .AzaliaSdin0 = (CONFIG_AZ_PIN>>0) & 0x03, + .AzaliaSdin1 = (CONFIG_AZ_PIN>>2) & 0x03, + .AzaliaSdin2 = (CONFIG_AZ_PIN>>4) & 0x03, + .AzaliaSdin3 = (CONFIG_AZ_PIN>>6) & 0x03 + }; + FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList; + /* Azalia Controller Front Panel OEM Table Pointer */ + + /* Fan Control */ + oem_fan_control(FchParams); + } + printk(BIOS_DEBUG, " Done\n"); + + return AGESA_SUCCESS; +} diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig new file mode 100644 index 0000000..4226e62 --- /dev/null +++ b/src/mainboard/amd/lamar/Kconfig @@ -0,0 +1,102 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_AMD_LAMAR + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_PI_00630F01 + select NORTHBRIDGE_AMD_PI_00630F01 + select SOUTHBRIDGE_AMD_PI_BOLTON + select SUPERIO_FINTEK_F81216H + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE +# select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config MAINBOARD_DIR + string + default amd/lamar + +config MAINBOARD_PART_NUMBER + string + default "DB-FP3" + +config MAINBOARD_SERIAL_NUMBER + string + default "52198A" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + + +config RAMBASE + hex + default 0x200000 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_XHCI_FWM_FILE + string + default "3rdparty/southbridge/amd/bolton/xhci.bin" + +config AZ_PIN + hex + default 0x02 + +config ENABLE_DP3_DAUGHTER_CARD_IN_J120 + bool "Use J120 as an additional graphics port" + default n + help + The PCI Express slot at J120 can be configured as an additional + DisplayPort connector using an adapter card from AMD or as a normal + PCI Express (x4) slot. + + By default, the connector is configured as a PCI Express (x4) slot. + + Select this option to enable the slot for use with one of AMD's + passive graphics port expander cards (only available from AMD). + +endif # BOARD_AMD_LAMAR diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc new file mode 100644 index 0000000..ec584cb --- /dev/null +++ b/src/mainboard/amd/lamar/Makefile.inc @@ -0,0 +1,26 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += agesawrapper.c +romstage-y += BiosCallOuts.c +romstage-y += PlatformGnbPcie.c + +ramstage-y += agesawrapper.c +ramstage-y += BiosCallOuts.c +ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/lamar/PlatformGnbPcie.c b/src/mainboard/amd/lamar/PlatformGnbPcie.c new file mode 100644 index 0000000..0d65ad5 --- /dev/null +++ b/src/mainboard/amd/lamar/PlatformGnbPcie.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +const PCIe_PORT_DESCRIPTOR PortList [] = { + + /* + * Lanes to pins to PCI device mapping can be found in section 2.12 of the + * BIOS and Kernel Developer's Guide for AMD Family 15h Models 30h-3Fh + */ + + { /* PCIe x16 Connector J119, DP4/5/6, GFX[15:0], Lanes [31:16], PCI 00:02.1 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 31), + PCIE_PORT_DATA_INITIALIZER_V2 ( + PortEnabled, + ChannelTypeExt6db, 0, 0, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 175, + 0 + ) + }, + + { /* PCIe x4 Connector J118, GPP[3:0], Lanes [11:8], PCI 00:03.2 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 11), + PCIE_PORT_DATA_INITIALIZER_V2 ( + PortEnabled, + ChannelTypeExt6db, 0, 0, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 176, + 0 + ) + }, + + { /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER ( + IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine, + 12, 15 + ), + PCIE_PORT_DATA_INITIALIZER_V2 ( + PortEnabled, + ChannelTypeExt6db, 0, 0, + HotplugDisabled, + PcieGenMaxSupported, PcieGenMaxSupported, + AspmDisabled, + 177, + 0 + ) + }, + +}; + +static const PCIe_DDI_DESCRIPTOR DdiList [] = { + { /* DP3 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER ( + IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine, + 12, 15 + ), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux4, Hdp4) + }, + + { /* DP2 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 36, 39), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) + }, + + { /* DP1 */ + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + }, + + { /* DP0 */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 4, 7), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) + }, +}; + +const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID +OemCustomizeInitEarly ( + IN OUT AMD_EARLY_PARAMS *InitEarly + ) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} diff --git a/src/mainboard/amd/lamar/acpi/AmdImc.asl b/src/mainboard/amd/lamar/acpi/AmdImc.asl new file mode 100644 index 0000000..81dfb46 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/AmdImc.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Store(0, Local0) + Store(50, Local1) + While (LAnd (LNotEqual(Local0, 0xFA), LGreater(Local1,0))) { + Store(MRG0, Local0) + Sleep(10) + Decrement(Local1) + } +} + +//Init +Method (ITZE, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(1, MRG1) + Store(0, MRG2) + Store(0x98, MSTI) + WACK() + + Store(0, MRG0) + Store(0xB4, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() +} + +//Wake +Method (IMWK, 0) +{ + Store(0, MRG0) + Store(0xB5, MRG1) + Store(0, MRG2) + Store(0x96, MSTI) + WACK() + + Store(0, MRG0) + Store(0, MRG1) + Store(0, MRG2) + Store(0x80, MSTI) + WACK() + + Or(MRG2, 0x01, Local0) + + Store(0, MRG0) + Store(0, MRG1) + Store(Local0, MRG2) + Store(0x81, MSTI) + WACK() +} diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl new file mode 100644 index 0000000..3ea1764 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/gpe.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/lamar/acpi/mainboard.asl b/src/mainboard/amd/lamar/acpi/mainboard.asl new file mode 100644 index 0000000..33be113 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/mainboard.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* AcpiGpe0Blk */ + OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, + } diff --git a/src/mainboard/amd/lamar/acpi/routing.asl b/src/mainboard/amd/lamar/acpi/routing.asl new file mode 100644 index 0000000..6b2bae6 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/routing.asl @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0x0C, 0 }, + Package(){0x0001FFFF, 1, INTH, 0 }, + Package(){0x0001FFFF, 2, INTG, 0 }, + Package(){0x0001FFFF, 3, INTF, 0 }, + + /* Bus 0, Dev 2 - NB PCIe Gfx Bridge */ + Package(){0x0002FFFF, 0, INTE, 0 }, + Package(){0x0002FFFF, 1, INTF, 0 }, + Package(){0x0002FFFF, 2, INTG, 0 }, + Package(){0x0002FFFF, 3, INTH, 0 }, + + /* Bus 0, Dev 3 - NB GPP PCIe bridge */ + Package(){0x0003FFFF, 0, INTE, 0 }, + Package(){0x0003FFFF, 1, INTF, 0 }, + Package(){0x0003FFFF, 2, INTG, 0 }, + Package(){0x0003FFFF, 3, INTH, 0 }, + + /* Bus 0, Dev 4 - UMI Bridge */ + Package(){0x0004FFFF, 0, INTE, 0 }, + Package(){0x0004FFFF, 1, INTF, 0 }, + Package(){0x0004FFFF, 2, INTG, 0 }, + Package(){0x0004FFFF, 3, INTH, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: xHCI @ func 0 + * xHCI @ func 2 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 1, INTB, 0 }, /* IDE Controller */ + Package(){0x0014FFFF, 0, INTA, 0 }, /* Azalia Audio Controller */ + Package(){0x0014FFFF, 2, INTC, 0 }, /* USB #4 OHCI Controller */ + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 2, INTB, 0 }, + + /* Bus 0, Dev 21 SB GPP Pcie Bridge */ + Package(){0x0015FFFF, 0, INTE, 0 }, + Package(){0x0015FFFF, 1, INTF, 0 }, + Package(){0x0015FFFF, 2, INTG, 0 }, + Package(){0x0015FFFF, 3, INTH, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 12 }, + Package(){0x0001FFFF, 1, 0, 5 }, + + /* Bus 0, Dev 2 - PCIe Bridge for GFX slots */ + Package(){0x0002FFFF, 0, 0, 20 }, + Package(){0x0002FFFF, 1, 0, 21 }, + Package(){0x0002FFFF, 2, 0, 22 }, + Package(){0x0002FFFF, 3, 0, 23 }, + + /* Bus 0, Dev 3 - PCIe Bridge for NB GPP slots */ + Package(){0x0003FFFF, 0, 0, 20 }, + Package(){0x0003FFFF, 1, 0, 21 }, + Package(){0x0003FFFF, 2, 0, 22 }, + Package(){0x0003FFFF, 3, 0, 23 }, + + /* Bus 0, Dev 4 - UMI Bridge */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 1, 0, 17 }, /* IDE Controller */ + Package(){0x0014FFFF, 0, 0, 16 }, /* Azalia Audio Controller */ + Package(){0x0014FFFF, 2, 0, 18 }, /* USB #4 OHCI Controller */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 18}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 20 }, + Package(){0x0015FFFF, 1, 0, 21 }, + Package(){0x0015FFFF, 2, 0, 22 }, + Package(){0x0015FFFF, 3, 0, 23 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to NB Gfx PCIe slots */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to NB Gfx PCIe slots */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS3, Package(){ + /* PCIe slot - Hooked to NB GPP PCIe slots */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS3, Package(){ + /* PCIe slot - Hooked to NB GPP PCIe slots */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE0, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 0*/ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APE0, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 0*/ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PE1, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 1*/ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APE1, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 1*/ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PE2, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 2*/ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APE2, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 2*/ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PE3, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 3 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APE3, Package(){ + /* PCIe slot - Hooked to PCIe Bridge 3*/ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/amd/lamar/acpi/sata.asl b/src/mainboard/amd/lamar/acpi/sata.asl new file mode 100644 index 0000000..f675323 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/sata.asl @@ -0,0 +1 @@ +/* No SATA functionality */ diff --git a/src/mainboard/amd/lamar/acpi/si.asl b/src/mainboard/amd/lamar/acpi/si.asl new file mode 100644 index 0000000..aa49616 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/si.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl new file mode 100644 index 0000000..fcce35e --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/sleep.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,USBS) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/lamar/acpi/superio.asl b/src/mainboard/amd/lamar/acpi/superio.asl new file mode 100644 index 0000000..69c6108 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/superio.asl @@ -0,0 +1 @@ +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/amd/lamar/acpi/thermal.asl b/src/mainboard/amd/lamar/acpi/thermal.asl new file mode 100644 index 0000000..edb1daf --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/thermal.asl @@ -0,0 +1 @@ +/* No thermal zone functionality */ diff --git a/src/mainboard/amd/lamar/acpi/usb_oc.asl b/src/mainboard/amd/lamar/acpi/usb_oc.asl new file mode 100644 index 0000000..394f201 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi/usb_oc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/amd/lamar/acpi_tables.c b/src/mainboard/amd/lamar/acpi_tables.c new file mode 100644 index 0000000..1de3df9 --- /dev/null +++ b/src/mainboard/amd/lamar/acpi_tables.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <northbridge/amd/pi/agesawrapper.h> + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam15.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write southbridge IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1, + 0xFEC20000, 24); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/amd/lamar/agesawrapper.c b/src/mainboard/amd/lamar/agesawrapper.c new file mode 100644 index 0000000..e857de7 --- /dev/null +++ b/src/mainboard/amd/lamar/agesawrapper.c @@ -0,0 +1,679 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/pi/s3_resume.h> +#include <cbmem.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + +#define FILECODE UNASSIGNED_FILE_FILECODE + +#ifndef __PRE_RAM__ +/* ACPI table pointers returned by AmdInitLate */ +static void *DmiTable = NULL; +static void *AcpiPstate = NULL; +static void *AcpiSrat = NULL; +static void *AcpiSlit = NULL; + +static void *AcpiWheaMce = NULL; +static void *AcpiWheaCmc = NULL; +static void *AcpiAlib = NULL; +static void *AcpiIvrs = NULL; +static void *AcpiCrat = NULL; +#endif + +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of southbridge legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciData = (UINT32)MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + Status = AGESA_SUCCESS; + return Status; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + + /* For serial port */ + PciData = 0xFF03FFD5; + PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return Status; +} + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill (&AmdResetParams, + 0, + sizeof (AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResetParams.FchInterface.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + AmdResetParams.FchInterface.Xhci1Enable = TRUE; + + AmdResetParams.FchInterface.SataEnable = !(IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + AmdResetParams.FchInterface.IdeEnable = (IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + + status = AmdInitReset(&AmdResetParams); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly (AmdEarlyParamsPtr); + + status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = NULL; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + + // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow + // the compiler to flag the error if CONFIG_GFXUMA is not set. + PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; + PostParams->MemConfig.UmaSize = 0; + status = AmdInitPost (PostParams); + printk( + BIOS_SPEW, + "setup_uma_memory: umamode %s\n", + (PostParams->MemConfig.UmaMode == UMA_AUTO) ? "UMA_AUTO" : + (PostParams->MemConfig.UmaMode == UMA_SPECIFIED) ? "UMA_SPECIFIED" : + (PostParams->MemConfig.UmaMode == UMA_NONE) ? "UMA_NONE" : + "unknown" + ); + printk( + BIOS_SPEW, + "setup_uma_memory: syslimit 0x%08llX, bottomio 0x%08lx\n", + (unsigned long long)(PostParams->MemConfig.SysLimit) << 16, + (unsigned long)(PostParams->MemConfig.BottomIo) << 16 + ); + printk( + BIOS_SPEW, + "setup_uma_memory: uma size %luMB, uma start 0x%08lx\n", + (unsigned long)(PostParams->MemConfig.UmaSize) >> (20 - 16), + (unsigned long)(PostParams->MemConfig.UmaBase) << 16 + ); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + /* Initialize heap space */ + EmptyHeap(); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct (&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + + EnvParam->FchInterface.AzaliaController = AzEnable; + EnvParam->FchInterface.SataClass = CONFIG_HUDSON_SATA_MODE; + EnvParam->FchInterface.SataEnable = !(IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + EnvParam->FchInterface.IdeEnable = (IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + EnvParam->FchInterface.SataIdeMode = IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE); + EnvParam->GnbEnvConfiguration.IommuSupport = FALSE; + + status = AmdInitEnv (EnvParam); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return status; +} + +#ifndef __PRE_RAM__ +VOID* agesawrapper_getlateinitptr (int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + case PICK_CRAT: + return AcpiCrat; + default: + return NULL; + } +} +#endif + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_MID_PARAMS *MidParam; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio (); + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + MidParam = (AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr; + + MidParam->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + MidParam->GnbMidConfiguration.GnbIoapicAddress = 0xFEC20000; + + MidParam->FchInterface.AzaliaController = AzEnable; + MidParam->FchInterface.SataClass = CONFIG_HUDSON_SATA_MODE; + MidParam->FchInterface.SataEnable = !(IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + MidParam->FchInterface.IdeEnable = (IS_ENABLED(CONFIG_HUDSON_SATA_IDE) || IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE)); + MidParam->FchInterface.SataIdeMode = IS_ENABLED(CONFIG_HUDSON_SATA_LEGACY_IDE); + + status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return status; +} + +#ifndef __PRE_RAM__ +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; + Status = AmdInitLate(AmdLateParams); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + AcpiCrat = AmdLateParams->AcpiCrat; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return Status; +} +#endif + +AGESA_STATUS agesawrapper_amdlaterunaptask ( + UINT32 Func, + UINT32 Data, + VOID *ConfigPtr + ) +{ + AGESA_STATUS Status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill (&ApExeParams, + 0, + sizeof (AP_EXE_PARAMS), + &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + Status = AmdLateRunApTask (&ApExeParams); + if (Status != AGESA_SUCCESS) { + /* agesawrapper_amdreadeventlog(); */ + ASSERT(Status == AGESA_SUCCESS); + } + + return Status; +} + +#if CONFIG_HAVE_ACPI_RESUME + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct (&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); + + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct (&AmdParamStruct); + + return status; +} + +#ifndef __PRE_RAM__ +AGESA_STATUS agesawrapper_fchs3earlyrestore(void) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + LibAmdMemFill (&FchParams, + 0, + sizeof (FchParams), + &StdHeader); + + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + + FchInitS3EarlyRestore(&FchParams); + + return status; +} +#endif + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill (&AmdS3LateParams, + 0, + sizeof (AMD_S3LATE_PARAMS), + &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); + + AmdCreateStruct (&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info (S3DataType, + (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore (AmdS3LateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + return Status; +} + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_fchs3laterestore(void) +{ + AGESA_STATUS status = AGESA_SUCCESS; + + AMD_CONFIG_PARAMS StdHeader; + FCH_DATA_BLOCK FchParams; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + LibAmdMemFill (&FchParams, + 0, + sizeof (FchParams), + &StdHeader); + + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + + return status; +} +#endif + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill (&AmdInterfaceParams, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info ( + S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct (&AmdInterfaceParams); + + return Status; +} + +#endif /* #ifndef __PRE_RAM__ */ +#endif /* CONFIG_HAVE_ACPI_RESUME */ + +AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill (&AmdEventParams, + 0, + sizeof (EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog (&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog (&AmdEventParams); + } + + return Status; +} diff --git a/src/mainboard/amd/lamar/board_info.txt b/src/mainboard/amd/lamar/board_info.txt new file mode 100644 index 0000000..8bce92e --- /dev/null +++ b/src/mainboard/amd/lamar/board_info.txt @@ -0,0 +1,5 @@ +Board name: DB-FP3 (Lamar) +Category: eval +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/amd/lamar/cmos.layout b/src/mainboard/amd/lamar/cmos.layout new file mode 100644 index 0000000..5520564 --- /dev/null +++ b/src/mainboard/amd/lamar/cmos.layout @@ -0,0 +1,114 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb new file mode 100644 index 0000000..eb41942 --- /dev/null +++ b/src/mainboard/amd/lamar/devicetree.cb @@ -0,0 +1,118 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# 2013 - 2014 Sage Electronic Engineering, LLC +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/pi/00630F01/root_complex + device cpu_cluster 0 on + chip cpu/amd/pi/00630F01 + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00630F01 # CPU side of HT root complex + + chip northbridge/amd/pi/00630F01 # PCI side of HT root complex + device pci 0.0 on end # 0x1422 Root Complex + device pci 0.2 off end # 0x1423 IOMMU + device pci 1.0 on end # 0x13XX Internal Graphics + device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio + device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge + device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) + device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 + device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge + device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) + device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) + device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 + device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 + device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 + device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge +# device pci 4.1 on end # 0x1426 P2P bridge for UMI link +# device pci 4.2 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 3 +# device pci 4.3 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 2 +# device pci 4.4 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 1 +# device pci 4.5 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 0 + end #chip northbridge/amd/pi/00630F01 + + chip southbridge/amd/pi/hudson + device pci 10.0 on end # 0x7814 XHCI HC0 + device pci 10.1 on end # 0x7814 XHCI HC1 + device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) + device pci 12.0 on end # 0x7807 USB OHCI + device pci 12.2 on end # 0x7808 USB EHCI + device pci 13.0 on end # 0x7807 USB OHCI + device pci 13.2 on end # 0x7808 USB EHCI + device pci 14.0 on # 0x780B SMBus + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # 0x780C IDE + device pci 14.2 on end # 0x780D HDA + device pci 14.3 on # 0x780E LPC + chip superio/fintek/f81216h + device pnp 4e.0 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 3 + end + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 4 + end + device pnp 4e.2 off end # COM3 + device pnp 4e.3 off end # COM4 + device pnp 4e.8 off end # WDT + end # f81865f + end #LPC + device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. + device pci 14.5 on end # 0x7809 USB OHCI + device pci 14.7 on end # 0x7806 SD Flash Controller + register "sd_mode" = "3" + device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) + device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) + device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) + device pci 15.3 off end # 0x43A3 SB GPP Port 3 + register "gpp_configuration" = "4" + device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) + end #southbridge/amd/pi/hudson + + device pci 18.0 on end # 0x141A HT Configuration + device pci 18.1 on end # 0x141B Address Maps + device pci 18.2 on end # 0x141C DRAM Configuration + device pci 18.3 on end # 0x141D Miscellaneous + device pci 18.4 on end # 0x141E Power Management + device pci 18.5 on end # 0x141F Northbridge + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + }" + + end #chip northbridge/amd/pi/00630F01 # CPU side of HT root complex + end #domain +end #northbridge/amd/pi/00630F01/root_complex diff --git a/src/mainboard/amd/lamar/dsdt.asl b/src/mainboard/amd/lamar/dsdt.asl new file mode 100644 index 0000000..dcf164b --- /dev/null +++ b/src/mainboard/amd/lamar/dsdt.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu/amd/pi/00630F01/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/pi/00630F01/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/pi/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/lamar/get_bus_conf.c b/src/mainboard/amd/lamar/get_bus_conf.c new file mode 100644 index 0000000..5d03cb5 --- /dev/null +++ b/src/mainboard/amd/lamar/get_bus_conf.c @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include <cpu/amd/amdfam15.h> +#include <northbridge/amd/pi/agesawrapper.h> +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include "imc.h" +#endif + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sb[16]; +u32 apicid_sb, apicid_nb; + +/* + * Here you only need to set value in pci1234 for HT-IO that could be installed or not + * You may need to preset pci1234 for HTIO board, + * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail + */ +u32 pci1234x[] = { + 0x0000ff0, +}; + +u32 bus_type[256]; +u32 sbdn_sb; + +static u32 get_bus_conf_done = 0; + +#if CONFIG_HAVE_ACPI_RESUME +extern u8 acpi_slp_type; +#endif +void get_bus_conf(void) +{ + u32 apicid_base; + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ +#if CONFIG_HAVE_ACPI_RESUME + if (acpi_slp_type != 3) { + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + status = agesawrapper_amdS3Save(); + if (status) { + printk(BIOS_DEBUG, "agesawrapper_amds3save failed: %x \n", status); + } + } +#else + status = agesawrapper_amdinitlate(); + if (status) + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); +#endif + +// setup_ioapic(0xFEC20000, 5); +// dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ +// pci_write_config32(dev, 0xF8, 0); +// pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + sbdn_sb = 0; + + memset(bus_sb, 0, sizeof(bus_sb)); + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_sb[0] = (pci1234x[0] >> 16) & 0xff; + + /* Hudson */ + dev = dev_find_slot(bus_sb[0], PCI_DEVFN(sbdn_sb + 0x14, 4)); + + if (dev) { + bus_sb[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + for (i = 0; i < 12; i++) { + dev = dev_find_slot(bus_sb[0], PCI_DEVFN(sbdn_sb + 0x14, i)); + if (dev) { + bus_sb[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sb[2]; j < bus_isa; j++) + bus_type[j] = 1; + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + apicid_base = CONFIG_MAX_CPUS; + apicid_sb = apicid_base; + +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* AMD AGESA does not enable thermal zone, so we enable it here. */ + enable_imc_thermal_zone(); +#endif +} diff --git a/src/mainboard/amd/lamar/irq_tables.c b/src/mainboard/amd/lamar/irq_tables.c new file mode 100644 index 0000000..dc457cc --- /dev/null +++ b/src/mainboard/amd/lamar/irq_tables.c @@ -0,0 +1,112 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam15.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +extern u8 bus_isa; +extern u8 bus_sb[6]; +extern unsigned long sbdn_sb; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb[0]; + pirq->rtr_devfn = ((sbdn_sb + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb[0], ((sbdn_sb + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c new file mode 100644 index 0000000..4bde7a6 --- /dev/null +++ b/src/mainboard/amd/lamar/mainboard.c @@ -0,0 +1,208 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <arch/acpi.h> +#include <northbridge/amd/pi/BiosCallOuts.h> +#include <cpu/amd/pi/s3_resume.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <northbridge/amd/pi/00630F01/pci_devs.h> +#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <southbridge/amd/pi/hudson/pci_devs.h> +#include <southbridge/amd/amd_pci_util.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { +#if defined(__GNUC__) + [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, +#endif + /* + * [80..81] Northbridge devices (these indicies are beyond + * the southbridge C00/C01 range) + */ + [PIRQ_GFX] = 0x0C, + [PIRQ_ACTL] = 0x1F, + /* [00..07] INTA# - INTH# */ + [PIRQ_A] = 0x0A, + [PIRQ_B] = 0x0B, + [PIRQ_C] = 0x0A, + [PIRQ_D] = 0x0B, + [PIRQ_E] = 0x0A, + [PIRQ_F] = 0x0B, + [PIRQ_G] = 0x0A, + [PIRQ_H] = 0x0B, + /* [08..0B] MISC, MISC0, MISC1 (HPET lower bits), MISC2 (HPET upper bits) */ + [PIRQ_MISC] = 0xFA, + [PIRQ_MISC0] = 0xF1, + [PIRQ_MISC1] = 0x00, /* HPET lower bits */ + [PIRQ_MISC2] = 0x00, /* HPET upper bits */ + /* [0C..0F] INT from Serial irq */ + /* [10..1F] SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ +// [PIRQ_SD] = 0x0E, + /* [20..25] IMC INT0 - 5 */ + /* [30..37] USB Devs 18/19/22/20 INTA-C */ + [PIRQ_EHCI1] = 0x0A, + [PIRQ_OHCI1] = 0x0B, + [PIRQ_EHCI2] = 0x0A, + [PIRQ_OHCI2] = 0x0B, + [PIRQ_EHCI3] = 0x0A, + [PIRQ_OHCI3] = 0x0B, + [PIRQ_OHCI4] = 0x0B, + /* [40..41] IDE, SATA */ + [PIRQ_IDE] = 0x0A, + [PIRQ_SATA] = 0x09, + /* [50..57] GPPInt0 - 3 */ + [PIRQ_GPP0] = 0x0A, + [PIRQ_GPP1] = 0x0B, + [PIRQ_GPP2] = 0x0A, + [PIRQ_GPP3] = 0x0B, +}; + +const u8 mainboard_intr_data[] = { +#if defined(__GNUC__) + [0 ... FCH_INT_TABLE_SIZE-1] = 0x1F, +#endif + /* [80..81] Northbridge devices (indicies above C00/C01 range) */ + [PIRQ_GFX] = 0x0C, + [PIRQ_ACTL] = 0x10, + /* [00..07] INTA# - INTH# */ + [PIRQ_A] = 0x10, + [PIRQ_B] = 0x11, + [PIRQ_C] = 0x12, + [PIRQ_D] = 0x13, + [PIRQ_E] = 0x14, + [PIRQ_F] = 0x15, + [PIRQ_G] = 0x16, + [PIRQ_H] = 0x17, + /* [08..0B] Misc-nil,0,1,2, INT from Serial irq */ + [PIRQ_MISC] = 0x00, + [PIRQ_MISC0] = 0x00, + [PIRQ_MISC1] = 0x00, /* HPET lower bits */ + [PIRQ_MISC2] = 0x00, /* HPET upper bits */ + /* [0C..0F] INT from Serial irq */ + /* [10..1F] SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [PIRQ_SCI] = 0x09, + [PIRQ_HDA] = 0x10, +// [PIRQ_SD] = 0x12, + /* [20..25] IMC INT0 - 5 */ + /* [30..37] USB Devs 18/19/22/20 INTA-C */ + [PIRQ_EHCI1] = 0x11, + [PIRQ_OHCI1] = 0x12, + [PIRQ_EHCI2] = 0x11, + [PIRQ_OHCI2] = 0x12, + [PIRQ_EHCI3] = 0x11, + [PIRQ_OHCI3] = 0x12, + [PIRQ_OHCI4] = 0x12, + /* [40..41] IDE, SATA */ + [PIRQ_IDE] = 0x11, + [PIRQ_SATA] = 0x13, + /* [50..57] GPPInt0 - 3 */ + [PIRQ_GPP0] = 0x10, + [PIRQ_GPP1] = 0x11, + [PIRQ_GPP2] = 0x12, + [PIRQ_GPP3] = 0x13, +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ +// {GFX_DEVFN, {PIRQ_GFX, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ +// {ACTL_DEVFN, {PIRQ_NC, PIRQ_ACTL, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J119: 02.1 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J118: 03.1 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* PCIe J120: 03.2 */ + {XHCI_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {XHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.1 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {IDE_DEVFN, {PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}}, /* IDE: 14.1 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCI: 14.4 */ + {OHCI4_DEVFN, {PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}}, /* OHCI4: 14.5 */ +// {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ + {SB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* LAN: 15.0 */ + {SB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe J122: 15.1 */ + {SB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* mPCIe J123: 15.2 */ + {SB_PCIE_PORT4_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* unused 15.3 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 (same device as xHCI 10.0) */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 (same device as xHCI 10.1) */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = FCH_INT_TABLE_SIZE /* FIXME sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct) */; + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/************************************************* + * enable the dedicated function in lamar board. + *************************************************/ +static void mainboard_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* + * The mainboard is the first place that we get control in ramstage. Check + * for S3 resume and call the approriate AGESA/CIMx resume functions. + */ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = acpi_get_sleep_type(); + if (acpi_slp_type == 3) + agesawrapper_fchs3earlyrestore(); +#endif + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c new file mode 100644 index 0000000..e4e0d17 --- /dev/null +++ b/src/mainboard/amd/lamar/mptable.c @@ -0,0 +1,170 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <cpu/amd/amdfam15.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> +#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/pi/hudson/pci_devs.h> +#include <northbridge/amd/pi/00630F01/pci_devs.h> + +extern u8 bus_sb[16]; +extern u32 bus_type[256]; +extern u32 sbdn_sb; +extern u32 apicid_nb, apicid_sb; + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u32 apicver_nb, apicver_sb; + + /* Intialize the MP_Table */ + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); + + /* Get Bus Configuration */ + get_bus_conf(); + + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + +#define NB_APIC_ADDR 0xFEC20000 + + apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24); /* Get the GNB IOAPIC ID */ + apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF); /* Get the GNB IOAPIC version */ + + smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR); + + apicid_sb = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); /* Get the southbridge IOAPIC ID */ + apicver_sb = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); /* Get the southbridge IOAPIC version */ + + smp_write_ioapic(mc, apicid_sb, apicver_sb, IO_APIC_ADDR); + + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0); + mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, fn, apic, pin) \ + if (((pin) != 0x00) && ((pin) != 0x1F)) \ + { \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \ + } + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]); + PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]); + PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]); + PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]); + + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]); + + /* PCI slots */ + /* NB Gfx PCIe Bridges */ + PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); + + /* NB GPP PCIe Bridges */ + PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]); + PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]); + + /* PCI slots */ + PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]); + + /* FCH GPP PCIe Bridges */ + PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); /* ADDR, Enable Virtual Wire */ + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c new file mode 100644 index 0000000..04d7d9c --- /dev/null +++ b/src/mainboard/amd/lamar/romstage.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <console/console.h> +#include <console/loglevel.h> +#include <cpu/amd/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <cpu/amd/pi/s3_resume.h> +#include "src/drivers/pc80/i8254.c" +#include "src/drivers/pc80/i8259.c" +#include "cbmem.h" +#include "superio/fintek/f81216h/f81216h.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + AGESA_STATUS status = AGESA_UNSUPPORTED; + + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + /* + * The following should be a call to AGESAWRAPPER() macro, but + * that would use console output before it is initialized. + */ + status = agesawrapper_amdinitmmio(); + if (AGESA_SUCCESS != status) { + printk(BIOS_WARNING, "AmdInitMmio reported %s\n", decodeAGESA_STATUS(status)); + } + + outb(0x24, 0xCD6); + outb(0x01, 0xCD7); + *(volatile u32 *) (0xFED80000 + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ + *(volatile u32 *) (0xFED80000 + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ + hudson_lpc_port80(); + + if (!cpu_init_detectedx) { + post_code(0x30); + f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); + post_code(0x31); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + post_code(0x38); + printk(BIOS_DEBUG, "Got past hudson_early_setup\n"); + + post_code(0x39); + AGESAWRAPPER(amdinitearly); + int s3resume = acpi_is_wakeup_s3(); + if (!s3resume) { + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); + } +#if CONFIG_HAVE_ACPI_RESUME + else { /* S3 detect */ + printk(BIOS_INFO, "S3 detected\n"); + + post_code(0x60); + AGESAWRAPPER(amdinitresume); + + AGESAWRAPPER(amds3laterestore); + + post_code(0x61); + prepare_for_resume(); + } +#endif + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x50); + copy_and_run(); + + post_code(0x54); /* Should never see this post code. */ +}

1 0

Patch set updated for coreboot: 131438b x86: Add amd/pi to the list of excluded .illegal_globals
by Dave Frodin 22 Jan '15

22 Jan '15

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8256 -gerrit commit 131438b6b321703a3c2d55e9e1dcb8cd7cfa22db Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Tue Jan 20 18:00:57 2015 -0700 x86: Add amd/pi to the list of excluded .illegal_globals Change-Id: I5167910ff790a3152a4ad8e5af0a4a3b17894f0f Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/arch/x86/init/romstage.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 99bcc8e..9468cfe 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -72,7 +72,7 @@ SECTIONS . = 0xffffff00; .illegal_globals . : { - *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */cpu/amd/agesa/*.romstage.o */vendorcode/amd/agesa/* */vendorcode/amd/cimx/*) .data) + *(EXCLUDE_FILE (*/libagesa.*.a: */buildOpts.romstage.o */agesawrapper.romstage.o */cpu/amd/agesa/*.romstage.o */vendorcode/amd/agesa/* */cpu/amd/pi/*.romstage.o */vendorcode/amd/pi/* */vendorcode/amd/cimx/*) .data) *(.data.*) *(.bss) *(.bss.*)

1 0

Patch set updated for coreboot: ab0b3aa vboot2: copy tlcl from vboot_reference as a preparation for vboot2 integration
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8164 -gerrit commit ab0b3aa7a82828d76059f91a8673ef027d41ec6a Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Wed Jul 2 08:37:23 2014 -0700 vboot2: copy tlcl from vboot_reference as a preparation for vboot2 integration vboot2 abtracts tpm storage as some 'secure' space. Thus, it's firmware's responsibility to handle vboot specific operations with tpm. This CL just copies related files from vboot_reference so that we can see how code was modified in the next CL. Note rollback_index.c/h were renamed to antirollback.c/h. TEST=none BUG=none Branch=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I1792a622058f70a8fcd3c4037547539ad2870420 Original-Reviewed-on: https://chromium-review.googlesource.com/206462 Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> (cherry picked from commit 2ae188b29242bf09c5e79e31f98b330a30bf7b93) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5fa5a636003e8472127194e961fea4309489b1d9 --- src/include/antirollback.h | 187 +++++++ src/include/tpm_lite/tlcl.h | 209 ++++++++ src/include/tpm_lite/tss_constants.h | 96 ++++ src/lib/tlcl.c | 466 ++++++++++++++++++ src/lib/tlcl_internal.h | 61 +++ src/lib/tlcl_structures.h | 138 ++++++ src/lib/tpm_error_messages.h | 250 ++++++++++ src/vendorcode/google/chromeos/antirollback.c | 676 ++++++++++++++++++++++++++ 8 files changed, 2083 insertions(+) diff --git a/src/include/antirollback.h b/src/include/antirollback.h new file mode 100644 index 0000000..dd0de32 --- /dev/null +++ b/src/include/antirollback.h @@ -0,0 +1,187 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Functions for querying, manipulating and locking rollback indices + * stored in the TPM NVRAM. + */ + +#ifndef VBOOT_REFERENCE_ROLLBACK_INDEX_H_ +#define VBOOT_REFERENCE_ROLLBACK_INDEX_H_ + +#include "sysincludes.h" +#include "tss_constants.h" + +/* TPM NVRAM location indices. */ +#define FIRMWARE_NV_INDEX 0x1007 +#define KERNEL_NV_INDEX 0x1008 +/* This is just an opaque space for backup purposes */ +#define BACKUP_NV_INDEX 0x1009 +#define BACKUP_NV_SIZE 16 + + +/* Structure definitions for TPM spaces */ + +/* Kernel space - KERNEL_NV_INDEX, locked with physical presence. */ +#define ROLLBACK_SPACE_KERNEL_VERSION 2 +#define ROLLBACK_SPACE_KERNEL_UID 0x4752574C /* 'GRWL' */ + +typedef struct RollbackSpaceKernel { + /* Struct version, for backwards compatibility */ + uint8_t struct_version; + /* Unique ID to detect space redefinition */ + uint32_t uid; + /* Kernel versions */ + uint32_t kernel_versions; + /* Reserved for future expansion */ + uint8_t reserved[3]; + /* Checksum (v2 and later only) */ + uint8_t crc8; +} __attribute__((packed)) RollbackSpaceKernel; + +/* Flags for firmware space */ +/* + * Last boot was developer mode. TPM ownership is cleared when transitioning + * to/from developer mode. + */ +#define FLAG_LAST_BOOT_DEVELOPER 0x01 +/* + * Some systems may not have a dedicated dev-mode switch, but enter and leave + * dev-mode through some recovery-mode magic keypresses. For those systems, the + * dev-mode "switch" state is in this bit (0=normal, 1=dev). To make it work, a + * new flag is passed to VbInit(), indicating that the system lacks a physical + * dev-mode switch. If a physical switch is present, this bit is ignored. + */ +#define FLAG_VIRTUAL_DEV_MODE_ON 0x02 + +/* Firmware space - FIRMWARE_NV_INDEX, locked with global lock. */ +#define ROLLBACK_SPACE_FIRMWARE_VERSION 2 + +typedef struct RollbackSpaceFirmware { + /* Struct version, for backwards compatibility */ + uint8_t struct_version; + /* Flags (see FLAG_* above) */ + uint8_t flags; + /* Firmware versions */ + uint32_t fw_versions; + /* Reserved for future expansion */ + uint8_t reserved[3]; + /* Checksum (v2 and later only) */ + uint8_t crc8; +} __attribute__((packed)) RollbackSpaceFirmware; + + +/* All functions return TPM_SUCCESS (zero) if successful, non-zero if error */ + +/* + * These functions are called from VbInit(). They cannot use global + * variables. + */ + +uint32_t RollbackS3Resume(void); + +/* + * These functions are callable from VbSelectFirmware(). They cannot use + * global variables. + */ + +/** + * This must be called. + */ +uint32_t RollbackFirmwareSetup(int is_hw_dev, + int disable_dev_request, + int clear_tpm_owner_request, + /* two outputs on success */ + int *is_virt_dev, uint32_t *tpm_version); + +/** + * Write may be called if the versions change. + */ +uint32_t RollbackFirmwareWrite(uint32_t version); + +/** + * Lock must be called. + */ +uint32_t RollbackFirmwareLock(void); + +/* + * These functions are callable from VbSelectAndLoadKernel(). They may use + * global variables. + */ + +/** + * Read stored kernel version. + */ +uint32_t RollbackKernelRead(uint32_t *version); + +/** + * Write stored kernel version. + */ +uint32_t RollbackKernelWrite(uint32_t version); + +/** + * Read backup data. + */ +uint32_t RollbackBackupRead(uint8_t *raw); + +/** + * Write backup data. + */ +uint32_t RollbackBackupWrite(uint8_t *raw); + +/** + * Lock must be called. Internally, it's ignored in recovery mode. + */ +uint32_t RollbackKernelLock(int recovery_mode); + +/****************************************************************************/ + +/* + * The following functions are internal apis, listed here for use by unit tests + * only. + */ + +/** + * Issue a TPM_Clear and reenable/reactivate the TPM. + */ +uint32_t TPMClearAndReenable(void); + +/** + * Like TlclWrite(), but checks for write errors due to hitting the 64-write + * limit and clears the TPM when that happens. This can only happen when the + * TPM is unowned, so it is OK to clear it (and we really have no choice). + * This is not expected to happen frequently, but it could happen. + */ +uint32_t SafeWrite(uint32_t index, const void *data, uint32_t length); + +/** + * Similarly to SafeWrite(), this ensures we don't fail a DefineSpace because + * we hit the TPM write limit. This is even less likely to happen than with + * writes because we only define spaces once at initialization, but we'd rather + * be paranoid about this. + */ +uint32_t SafeDefineSpace(uint32_t index, uint32_t perm, uint32_t size); + +/** + * Perform one-time initializations. + * + * Create the NVRAM spaces, and set their initial values as needed. Sets the + * nvLocked bit and ensures the physical presence command is enabled and + * locked. + */ +uint32_t OneTimeInitializeTPM(RollbackSpaceFirmware *rsf, + RollbackSpaceKernel *rsk); + +/** + * Start the TPM and establish the root of trust for the anti-rollback + * mechanism. + */ +uint32_t SetupTPM(int developer_mode, int disable_dev_request, + int clear_tpm_owner_request, RollbackSpaceFirmware *rsf); + +/** + * Utility function to turn the virtual dev-mode flag on or off. 0=off, 1=on. + */ +uint32_t SetVirtualDevMode(int val); + +#endif /* VBOOT_REFERENCE_ROLLBACK_INDEX_H_ */ diff --git a/src/include/tpm_lite/tlcl.h b/src/include/tpm_lite/tlcl.h new file mode 100644 index 0000000..5373120 --- /dev/null +++ b/src/include/tpm_lite/tlcl.h @@ -0,0 +1,209 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * TPM Lightweight Command Library. + * + * A low-level library for interfacing to TPM hardware or an emulator. + */ + +#ifndef TPM_LITE_TLCL_H_ +#define TPM_LITE_TLCL_H_ +#include <stdint.h> + +#include "tss_constants.h" + +/*****************************************************************************/ +/* Functions implemented in tlcl.c */ + +/** + * Call this first. Returns 0 if success, nonzero if error. + */ +uint32_t TlclLibInit(void); + +/** + * Call this on shutdown. Returns 0 if success, nonzero if error. + */ +uint32_t TlclLibClose(void); + +/* Low-level operations */ + +/** + * Perform a raw TPM request/response transaction. + */ +uint32_t TlclSendReceive(const uint8_t *request, uint8_t *response, + int max_length); + +/** + * Return the size of a TPM request or response packet. + */ +int TlclPacketSize(const uint8_t *packet); + +/* Commands */ + +/** + * Send a TPM_Startup(ST_CLEAR). The TPM error code is returned (0 for + * success). + */ +uint32_t TlclStartup(void); + +/** + * Save the TPM state. Normally done by the kernel before a suspend, included + * here for tests. The TPM error code is returned (0 for success). + */ +uint32_t TlclSaveState(void); + +/** + * Resume by sending a TPM_Startup(ST_STATE). The TPM error code is returned + * (0 for success). + */ +uint32_t TlclResume(void); + +/** + * Run the self test. + * + * Note---this is synchronous. To run this in parallel with other firmware, + * use ContinueSelfTest(). The TPM error code is returned. + */ +uint32_t TlclSelfTestFull(void); + +/** + * Run the self test in the background. + */ +uint32_t TlclContinueSelfTest(void); + +/** + * Define a space with permission [perm]. [index] is the index for the space, + * [size] the usable data size. The TPM error code is returned. + */ +uint32_t TlclDefineSpace(uint32_t index, uint32_t perm, uint32_t size); + +/** + * Write [length] bytes of [data] to space at [index]. The TPM error code is + * returned. + */ +uint32_t TlclWrite(uint32_t index, const void *data, uint32_t length); + +/** + * Read [length] bytes from space at [index] into [data]. The TPM error code + * is returned. + */ +uint32_t TlclRead(uint32_t index, void *data, uint32_t length); + +/** + * Read PCR at [index] into [data]. [length] must be TPM_PCR_DIGEST or + * larger. The TPM error code is returned. + */ +uint32_t TlclPCRRead(uint32_t index, void *data, uint32_t length); + +/** + * Write-lock space at [index]. The TPM error code is returned. + */ +uint32_t TlclWriteLock(uint32_t index); + +/** + * Read-lock space at [index]. The TPM error code is returned. + */ +uint32_t TlclReadLock(uint32_t index); + +/** + * Assert physical presence in software. The TPM error code is returned. + */ +uint32_t TlclAssertPhysicalPresence(void); + +/** + * Enable the physical presence command. The TPM error code is returned. + */ +uint32_t TlclPhysicalPresenceCMDEnable(void); + +/** + * Finalize the physical presence settings: sofware PP is enabled, hardware PP + * is disabled, and the lifetime lock is set. The TPM error code is returned. + */ +uint32_t TlclFinalizePhysicalPresence(void); + +uint32_t TlclAssertPhysicalPresenceResult(void); + +/** + * Turn off physical presence and locks it off until next reboot. The TPM + * error code is returned. + */ +uint32_t TlclLockPhysicalPresence(void); + +/** + * Set the nvLocked bit. The TPM error code is returned. + */ +uint32_t TlclSetNvLocked(void); + +/** + * Return 1 if the TPM is owned, 0 otherwise. + */ +int TlclIsOwned(void); + +/** + * Issue a ForceClear. The TPM error code is returned. + */ +uint32_t TlclForceClear(void); + +/** + * Issue a PhysicalEnable. The TPM error code is returned. + */ +uint32_t TlclSetEnable(void); + +/** + * Issue a PhysicalDisable. The TPM error code is returned. + */ +uint32_t TlclClearEnable(void); + +/** + * Issue a SetDeactivated. Pass 0 to activate. Returns result code. + */ +uint32_t TlclSetDeactivated(uint8_t flag); + +/** + * Get flags of interest. Pointers for flags you aren't interested in may + * be NULL. The TPM error code is returned. + */ +uint32_t TlclGetFlags(uint8_t *disable, uint8_t *deactivated, + uint8_t *nvlocked); + +/** + * Set the bGlobalLock flag, which only a reboot can clear. The TPM error + * code is returned. + */ +uint32_t TlclSetGlobalLock(void); + +/** + * Perform a TPM_Extend. + */ +uint32_t TlclExtend(int pcr_num, const uint8_t *in_digest, uint8_t *out_digest); + +/** + * Get the permission bits for the NVRAM space with |index|. + */ +uint32_t TlclGetPermissions(uint32_t index, uint32_t *permissions); + +/** + * Get the entire set of permanent flags. + */ +uint32_t TlclGetPermanentFlags(TPM_PERMANENT_FLAGS *pflags); + +/** + * Get the entire set of volatile (ST_CLEAR) flags. + */ +uint32_t TlclGetSTClearFlags(TPM_STCLEAR_FLAGS *pflags); + +/** + * Get the ownership flag. The TPM error code is returned. + */ +uint32_t TlclGetOwnership(uint8_t *owned); + +/** + * Request [length] bytes from TPM RNG to be stored in [data]. Actual number of + * bytes read is stored in [size]. The TPM error code is returned. + */ +uint32_t TlclGetRandom(uint8_t *data, uint32_t length, uint32_t *size); + +#endif /* TPM_LITE_TLCL_H_ */ diff --git a/src/include/tpm_lite/tss_constants.h b/src/include/tpm_lite/tss_constants.h new file mode 100644 index 0000000..883a5ad --- /dev/null +++ b/src/include/tpm_lite/tss_constants.h @@ -0,0 +1,96 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Some TPM constants and type definitions for standalone compilation for use + * in the firmware + */ +#ifndef VBOOT_REFERENCE_TSS_CONSTANTS_H_ +#define VBOOT_REFERENCE_TSS_CONSTANTS_H_ +#include <stdint.h> + +#define TPM_MAX_COMMAND_SIZE 4096 +#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256 /* saves space in the firmware */ +#define TPM_PUBEK_SIZE 256 +#define TPM_PCR_DIGEST 20 + +#define TPM_E_NON_FATAL 0x800 + +#define TPM_SUCCESS ((uint32_t)0x00000000) + +#define TPM_E_AREA_LOCKED ((uint32_t)0x0000003c) +#define TPM_E_BADINDEX ((uint32_t)0x00000002) +#define TPM_E_BAD_PRESENCE ((uint32_t)0x0000002d) +#define TPM_E_IOERROR ((uint32_t)0x0000001f) +#define TPM_E_INVALID_POSTINIT ((uint32_t)0x00000026) +#define TPM_E_MAXNVWRITES ((uint32_t)0x00000048) +#define TPM_E_OWNER_SET ((uint32_t)0x00000014) + +#define TPM_E_NEEDS_SELFTEST ((uint32_t)(TPM_E_NON_FATAL + 1)) +#define TPM_E_DOING_SELFTEST ((uint32_t)(TPM_E_NON_FATAL + 2)) + +#define TPM_E_ALREADY_INITIALIZED ((uint32_t)0x00005000) /* vboot local */ +#define TPM_E_INTERNAL_INCONSISTENCY ((uint32_t)0x00005001) /* vboot local */ +#define TPM_E_MUST_REBOOT ((uint32_t)0x00005002) /* vboot local */ +#define TPM_E_CORRUPTED_STATE ((uint32_t)0x00005003) /* vboot local */ +#define TPM_E_COMMUNICATION_ERROR ((uint32_t)0x00005004) /* vboot local */ +#define TPM_E_RESPONSE_TOO_LARGE ((uint32_t)0x00005005) /* vboot local */ +#define TPM_E_NO_DEVICE ((uint32_t)0x00005006) /* vboot local */ +#define TPM_E_INPUT_TOO_SMALL ((uint32_t)0x00005007) /* vboot local */ +#define TPM_E_WRITE_FAILURE ((uint32_t)0x00005008) /* vboot local */ +#define TPM_E_READ_EMPTY ((uint32_t)0x00005009) /* vboot local */ +#define TPM_E_READ_FAILURE ((uint32_t)0x0000500a) /* vboot local */ + +#define TPM_NV_INDEX0 ((uint32_t)0x00000000) +#define TPM_NV_INDEX_LOCK ((uint32_t)0xffffffff) +#define TPM_NV_PER_GLOBALLOCK (((uint32_t)1)<<15) +#define TPM_NV_PER_PPWRITE (((uint32_t)1)<<0) +#define TPM_NV_PER_READ_STCLEAR (((uint32_t)1)<<31) +#define TPM_NV_PER_WRITE_STCLEAR (((uint32_t)1)<<14) + +#define TPM_TAG_RQU_COMMAND ((uint16_t) 0xc1) +#define TPM_TAG_RQU_AUTH1_COMMAND ((uint16_t) 0xc2) +#define TPM_TAG_RQU_AUTH2_COMMAND ((uint16_t) 0xc3) + +#define TPM_TAG_RSP_COMMAND ((uint16_t) 0xc4) +#define TPM_TAG_RSP_AUTH1_COMMAND ((uint16_t) 0xc5) +#define TPM_TAG_RSP_AUTH2_COMMAND ((uint16_t) 0xc6) + +typedef uint8_t TSS_BOOL; +typedef uint16_t TPM_STRUCTURE_TAG; + +typedef struct tdTPM_PERMANENT_FLAGS +{ + TPM_STRUCTURE_TAG tag; + TSS_BOOL disable; + TSS_BOOL ownership; + TSS_BOOL deactivated; + TSS_BOOL readPubek; + TSS_BOOL disableOwnerClear; + TSS_BOOL allowMaintenance; + TSS_BOOL physicalPresenceLifetimeLock; + TSS_BOOL physicalPresenceHWEnable; + TSS_BOOL physicalPresenceCMDEnable; + TSS_BOOL CEKPUsed; + TSS_BOOL TPMpost; + TSS_BOOL TPMpostLock; + TSS_BOOL FIPS; + TSS_BOOL Operator; + TSS_BOOL enableRevokeEK; + TSS_BOOL nvLocked; + TSS_BOOL readSRKPub; + TSS_BOOL tpmEstablished; + TSS_BOOL maintenanceDone; + TSS_BOOL disableFullDALogicInfo; +} TPM_PERMANENT_FLAGS; + +typedef struct tdTPM_STCLEAR_FLAGS{ + TPM_STRUCTURE_TAG tag; + TSS_BOOL deactivated; + TSS_BOOL disableForceClear; + TSS_BOOL physicalPresence; + TSS_BOOL physicalPresenceLock; + TSS_BOOL bGlobalLock; +} TPM_STCLEAR_FLAGS; + +#endif /* VBOOT_REFERENCE_TSS_CONSTANTS_H_ */ diff --git a/src/lib/tlcl.c b/src/lib/tlcl.c new file mode 100644 index 0000000..bf2d27f --- /dev/null +++ b/src/lib/tlcl.c @@ -0,0 +1,466 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* A lightweight TPM command library. + * + * The general idea is that TPM commands are array of bytes whose + * fields are mostly compile-time constant. The goal is to build much + * of the commands at compile time (or build time) and change some of + * the fields at run time as needed. The code in + * utility/tlcl_generator.c builds structures containing the commands, + * as well as the offsets of the fields that need to be set at run + * time. + */ + +#include "sysincludes.h" + +#include "tlcl.h" +#include "tlcl_internal.h" +#include "tlcl_structures.h" +#include "utility.h" +#include "vboot_api.h" + +#ifdef FOR_TEST +/* Allow unit testing implementation of TlclSendReceive() */ +#undef CHROMEOS_ENVIRONMENT +#endif + +/* Sets the size field of a TPM command. */ +static inline void SetTpmCommandSize(uint8_t* buffer, uint32_t size) { + ToTpmUint32(buffer + sizeof(uint16_t), size); +} + +/* Gets the size field of a TPM command. */ +__attribute__((unused)) +static inline int TpmCommandSize(const uint8_t* buffer) { + uint32_t size; + FromTpmUint32(buffer + sizeof(uint16_t), &size); + return (int) size; +} + +/* Gets the size field of a TPM request or response. */ +int TlclPacketSize(const uint8_t* packet) { + return TpmCommandSize(packet); +} + +/* Gets the code field of a TPM command. */ +static inline int TpmCommandCode(const uint8_t* buffer) { + uint32_t code; + FromTpmUint32(buffer + sizeof(uint16_t) + sizeof(uint32_t), &code); + return code; +} + +/* Gets the return code field of a TPM result. */ +static inline int TpmReturnCode(const uint8_t* buffer) { + return TpmCommandCode(buffer); +} + +/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or + * DOING_SELFTEST errors are returned. + */ +static uint32_t TlclSendReceiveNoRetry(const uint8_t* request, + uint8_t* response, int max_length) { + + uint32_t response_length = max_length; + uint32_t result; + +#ifdef EXTRA_LOGGING + VBDEBUG(("TPM: command: %x%x %x%x%x%x %x%x%x%x\n", + request[0], request[1], + request[2], request[3], request[4], request[5], + request[6], request[7], request[8], request[9])); +#endif + + result = VbExTpmSendReceive(request, TpmCommandSize(request), + response, &response_length); + if (0 != result) { + /* Communication with TPM failed, so response is garbage */ + VBDEBUG(("TPM: command 0x%x send/receive failed: 0x%x\n", + TpmCommandCode(request), result)); + return result; + } + /* Otherwise, use the result code from the response */ + result = TpmReturnCode(response); + + /* TODO: add paranoia about returned response_length vs. max_length + * (and possibly expected length from the response header). See + * crosbug.com/17017 */ + +#ifdef EXTRA_LOGGING + VBDEBUG(("TPM: response: %x%x %x%x%x%x %x%x%x%x\n", + response[0], response[1], + response[2], response[3], response[4], response[5], + response[6], response[7], response[8], response[9])); +#endif + + VBDEBUG(("TPM: command 0x%x returned 0x%x\n", + TpmCommandCode(request), result)); + + return result; +} + + +/* Sends a TPM command and gets a response. Returns 0 if success or the TPM + * error code if error. In the firmware, waits for the self test to complete + * if needed. In the host, reports the first error without retries. */ +uint32_t TlclSendReceive(const uint8_t* request, uint8_t* response, + int max_length) { + uint32_t result = TlclSendReceiveNoRetry(request, response, max_length); + /* When compiling for the firmware, hide command failures due to the self + * test not having run or completed. */ +#ifndef CHROMEOS_ENVIRONMENT + /* If the command fails because the self test has not completed, try it + * again after attempting to ensure that the self test has completed. */ + if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) { + result = TlclContinueSelfTest(); + if (result != TPM_SUCCESS) { + return result; + } +#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE) + /* Retry only once */ + result = TlclSendReceiveNoRetry(request, response, max_length); +#else + /* This needs serious testing. The TPM specification says: "iii. The + * caller MUST wait for the actions of TPM_ContinueSelfTest to complete + * before reissuing the command C1." But, if ContinueSelfTest is + * non-blocking, how do we know that the actions have completed other than + * trying again? */ + do { + result = TlclSendReceiveNoRetry(request, response, max_length); + } while (result == TPM_E_DOING_SELFTEST); +#endif + } +#endif /* ! defined(CHROMEOS_ENVIRONMENT) */ + return result; +} + +/* Sends a command and returns the error code. */ +static uint32_t Send(const uint8_t* command) { + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + return TlclSendReceive(command, response, sizeof(response)); +} + +/* Exported functions. */ + +uint32_t TlclLibInit(void) { + return VbExTpmInit(); +} + +uint32_t TlclLibClose(void) { + return VbExTpmClose(); +} + +uint32_t TlclStartup(void) { + VBDEBUG(("TPM: Startup\n")); + return Send(tpm_startup_cmd.buffer); +} + +uint32_t TlclSaveState(void) { + VBDEBUG(("TPM: SaveState\n")); + return Send(tpm_savestate_cmd.buffer); +} + +uint32_t TlclResume(void) { + VBDEBUG(("TPM: Resume\n")); + return Send(tpm_resume_cmd.buffer); +} + +uint32_t TlclSelfTestFull(void) { + VBDEBUG(("TPM: Self test full\n")); + return Send(tpm_selftestfull_cmd.buffer); +} + +uint32_t TlclContinueSelfTest(void) { + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + VBDEBUG(("TPM: Continue self test\n")); + /* Call the No Retry version of SendReceive to avoid recursion. */ + return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer, + response, sizeof(response)); +} + +uint32_t TlclDefineSpace(uint32_t index, uint32_t perm, uint32_t size) { + struct s_tpm_nv_definespace_cmd cmd; + VBDEBUG(("TPM: TlclDefineSpace(0x%x, 0x%x, %d)\n", index, perm, size)); + Memcpy(&cmd, &tpm_nv_definespace_cmd, sizeof(cmd)); + ToTpmUint32(cmd.buffer + tpm_nv_definespace_cmd.index, index); + ToTpmUint32(cmd.buffer + tpm_nv_definespace_cmd.perm, perm); + ToTpmUint32(cmd.buffer + tpm_nv_definespace_cmd.size, size); + return Send(cmd.buffer); +} + +uint32_t TlclWrite(uint32_t index, const void* data, uint32_t length) { + struct s_tpm_nv_write_cmd cmd; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + const int total_length = + kTpmRequestHeaderLength + kWriteInfoLength + length; + + VBDEBUG(("TPM: TlclWrite(0x%x, %d)\n", index, length)); + Memcpy(&cmd, &tpm_nv_write_cmd, sizeof(cmd)); + VbAssert(total_length <= TPM_LARGE_ENOUGH_COMMAND_SIZE); + SetTpmCommandSize(cmd.buffer, total_length); + + ToTpmUint32(cmd.buffer + tpm_nv_write_cmd.index, index); + ToTpmUint32(cmd.buffer + tpm_nv_write_cmd.length, length); + Memcpy(cmd.buffer + tpm_nv_write_cmd.data, data, length); + + return TlclSendReceive(cmd.buffer, response, sizeof(response)); +} + +uint32_t TlclRead(uint32_t index, void* data, uint32_t length) { + struct s_tpm_nv_read_cmd cmd; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint32_t result_length; + uint32_t result; + + VBDEBUG(("TPM: TlclRead(0x%x, %d)\n", index, length)); + Memcpy(&cmd, &tpm_nv_read_cmd, sizeof(cmd)); + ToTpmUint32(cmd.buffer + tpm_nv_read_cmd.index, index); + ToTpmUint32(cmd.buffer + tpm_nv_read_cmd.length, length); + + result = TlclSendReceive(cmd.buffer, response, sizeof(response)); + if (result == TPM_SUCCESS && length > 0) { + uint8_t* nv_read_cursor = response + kTpmResponseHeaderLength; + FromTpmUint32(nv_read_cursor, &result_length); + nv_read_cursor += sizeof(uint32_t); + Memcpy(data, nv_read_cursor, result_length); + } + + return result; +} + +uint32_t TlclPCRRead(uint32_t index, void* data, uint32_t length) { + struct s_tpm_pcr_read_cmd cmd; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint32_t result; + + VBDEBUG(("TPM: TlclPCRRead(0x%x, %d)\n", index, length)); + if (length < kPcrDigestLength) { + return TPM_E_IOERROR; + } + Memcpy(&cmd, &tpm_pcr_read_cmd, sizeof(cmd)); + ToTpmUint32(cmd.buffer + tpm_pcr_read_cmd.pcrNum, index); + + result = TlclSendReceive(cmd.buffer, response, sizeof(response)); + if (result == TPM_SUCCESS) { + uint8_t* pcr_read_cursor = response + kTpmResponseHeaderLength; + Memcpy(data, pcr_read_cursor, kPcrDigestLength); + } + + return result; +} + +uint32_t TlclWriteLock(uint32_t index) { + VBDEBUG(("TPM: Write lock 0x%x\n", index)); + return TlclWrite(index, NULL, 0); +} + +uint32_t TlclReadLock(uint32_t index) { + VBDEBUG(("TPM: Read lock 0x%x\n", index)); + return TlclRead(index, NULL, 0); +} + +uint32_t TlclAssertPhysicalPresence(void) { + VBDEBUG(("TPM: Asserting physical presence\n")); + return Send(tpm_ppassert_cmd.buffer); +} + +uint32_t TlclPhysicalPresenceCMDEnable(void) { + VBDEBUG(("TPM: Enable the physical presence command\n")); + return Send(tpm_ppenable_cmd.buffer); +} + +uint32_t TlclFinalizePhysicalPresence(void) { + VBDEBUG(("TPM: Enable PP cmd, disable HW pp, and set lifetime lock\n")); + return Send(tpm_finalizepp_cmd.buffer); +} + +uint32_t TlclAssertPhysicalPresenceResult(void) { + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + return TlclSendReceive(tpm_ppassert_cmd.buffer, response, sizeof(response)); +} + +uint32_t TlclLockPhysicalPresence(void) { + VBDEBUG(("TPM: Lock physical presence\n")); + return Send(tpm_pplock_cmd.buffer); +} + +uint32_t TlclSetNvLocked(void) { + VBDEBUG(("TPM: Set NV locked\n")); + return TlclDefineSpace(TPM_NV_INDEX_LOCK, 0, 0); +} + +int TlclIsOwned(void) { + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE + TPM_PUBEK_SIZE]; + uint32_t result; + result = TlclSendReceive(tpm_readpubek_cmd.buffer, + response, sizeof(response)); + return (result != TPM_SUCCESS); +} + +uint32_t TlclForceClear(void) { + VBDEBUG(("TPM: Force clear\n")); + return Send(tpm_forceclear_cmd.buffer); +} + +uint32_t TlclSetEnable(void) { + VBDEBUG(("TPM: Enabling TPM\n")); + return Send(tpm_physicalenable_cmd.buffer); +} + +uint32_t TlclClearEnable(void) { + VBDEBUG(("TPM: Disabling TPM\n")); + return Send(tpm_physicaldisable_cmd.buffer); +} + +uint32_t TlclSetDeactivated(uint8_t flag) { + struct s_tpm_physicalsetdeactivated_cmd cmd; + VBDEBUG(("TPM: SetDeactivated(%d)\n", flag)); + Memcpy(&cmd, &tpm_physicalsetdeactivated_cmd, sizeof(cmd)); + *(cmd.buffer + cmd.deactivated) = flag; + return Send(cmd.buffer); +} + +uint32_t TlclGetPermanentFlags(TPM_PERMANENT_FLAGS* pflags) { + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint32_t size; + uint32_t result = + TlclSendReceive(tpm_getflags_cmd.buffer, response, sizeof(response)); + if (result != TPM_SUCCESS) + return result; + FromTpmUint32(response + kTpmResponseHeaderLength, &size); + /* TODO(crbug.com/379255): This fails. Find out why. + * VbAssert(size == sizeof(TPM_PERMANENT_FLAGS)); + */ + Memcpy(pflags, + response + kTpmResponseHeaderLength + sizeof(size), + sizeof(TPM_PERMANENT_FLAGS)); + return result; +} + +uint32_t TlclGetSTClearFlags(TPM_STCLEAR_FLAGS* vflags) { + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint32_t size; + uint32_t result = + TlclSendReceive(tpm_getstclearflags_cmd.buffer, response, sizeof(response)); + if (result != TPM_SUCCESS) + return result; + FromTpmUint32(response + kTpmResponseHeaderLength, &size); + /* Ugly assertion, but the struct is padded up by one byte. */ + /* TODO(crbug.com/379255): This fails. Find out why. + * VbAssert(size == 7 && sizeof(TPM_STCLEAR_FLAGS) - 1 == 7); + */ + Memcpy(vflags, + response + kTpmResponseHeaderLength + sizeof(size), + sizeof(TPM_STCLEAR_FLAGS)); + return result; +} + +uint32_t TlclGetFlags(uint8_t* disable, + uint8_t* deactivated, + uint8_t *nvlocked) { + TPM_PERMANENT_FLAGS pflags; + uint32_t result = TlclGetPermanentFlags(&pflags); + if (result == TPM_SUCCESS) { + if (disable) + *disable = pflags.disable; + if (deactivated) + *deactivated = pflags.deactivated; + if (nvlocked) + *nvlocked = pflags.nvLocked; + VBDEBUG(("TPM: Got flags disable=%d, deactivated=%d, nvlocked=%d\n", + pflags.disable, pflags.deactivated, pflags.nvLocked)); + } + return result; +} + +uint32_t TlclSetGlobalLock(void) { + uint32_t x; + VBDEBUG(("TPM: Set global lock\n")); + return TlclWrite(TPM_NV_INDEX0, (uint8_t*) &x, 0); +} + +uint32_t TlclExtend(int pcr_num, const uint8_t* in_digest, + uint8_t* out_digest) { + struct s_tpm_extend_cmd cmd; + uint8_t response[kTpmResponseHeaderLength + kPcrDigestLength]; + uint32_t result; + + Memcpy(&cmd, &tpm_extend_cmd, sizeof(cmd)); + ToTpmUint32(cmd.buffer + tpm_extend_cmd.pcrNum, pcr_num); + Memcpy(cmd.buffer + cmd.inDigest, in_digest, kPcrDigestLength); + + result = TlclSendReceive(cmd.buffer, response, sizeof(response)); + if (result != TPM_SUCCESS) + return result; + + Memcpy(out_digest, response + kTpmResponseHeaderLength, kPcrDigestLength); + return result; +} + +uint32_t TlclGetPermissions(uint32_t index, uint32_t* permissions) { + struct s_tpm_getpermissions_cmd cmd; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint8_t* nvdata; + uint32_t result; + uint32_t size; + + Memcpy(&cmd, &tpm_getpermissions_cmd, sizeof(cmd)); + ToTpmUint32(cmd.buffer + tpm_getpermissions_cmd.index, index); + result = TlclSendReceive(cmd.buffer, response, sizeof(response)); + if (result != TPM_SUCCESS) + return result; + + nvdata = response + kTpmResponseHeaderLength + sizeof(size); + FromTpmUint32(nvdata + kNvDataPublicPermissionsOffset, permissions); + return result; +} + +uint32_t TlclGetOwnership(uint8_t* owned) { + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint32_t size; + uint32_t result = + TlclSendReceive(tpm_getownership_cmd.buffer, response, sizeof(response)); + if (result != TPM_SUCCESS) + return result; + FromTpmUint32(response + kTpmResponseHeaderLength, &size); + /* TODO(crbug.com/379255): This fails. Find out why. + * VbAssert(size == sizeof(*owned)); + */ + Memcpy(owned, + response + kTpmResponseHeaderLength + sizeof(size), + sizeof(*owned)); + return result; +} + +uint32_t TlclGetRandom(uint8_t* data, uint32_t length, uint32_t *size) { + struct s_tpm_get_random_cmd cmd; + uint8_t response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; + uint32_t result; + + VBDEBUG(("TPM: TlclGetRandom(%d)\n", length)); + Memcpy(&cmd, &tpm_get_random_cmd, sizeof(cmd)); + ToTpmUint32(cmd.buffer + tpm_get_random_cmd.bytesRequested, length); + /* There must be room in the response buffer for the bytes. */ + if (length > TPM_LARGE_ENOUGH_COMMAND_SIZE - kTpmResponseHeaderLength + - sizeof(uint32_t)) { + return TPM_E_IOERROR; + } + + result = TlclSendReceive(cmd.buffer, response, sizeof(response)); + if (result == TPM_SUCCESS) { + uint8_t* get_random_cursor; + FromTpmUint32(response + kTpmResponseHeaderLength, size); + + /* There must be room in the target buffer for the bytes. */ + if (*size > length) { + return TPM_E_RESPONSE_TOO_LARGE; + } + get_random_cursor = response + kTpmResponseHeaderLength + + sizeof(uint32_t); + Memcpy(data, get_random_cursor, *size); + } + + return result; +} diff --git a/src/lib/tlcl_internal.h b/src/lib/tlcl_internal.h new file mode 100644 index 0000000..51fe6ef --- /dev/null +++ b/src/lib/tlcl_internal.h @@ -0,0 +1,61 @@ +/* Copyright (c) 2010 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef TPM_LITE_TLCL_INTERNAL_H_ +#define TPM_LITE_TLCL_INTERNAL_H_ + +/* + * These numbers derive from adding the sizes of command fields as shown in the + * TPM commands manual. + */ +#define kTpmRequestHeaderLength 10 +#define kTpmResponseHeaderLength 10 +#define kTpmReadInfoLength 12 +#define kEncAuthLength 20 +#define kPcrDigestLength 20 + + +/* + * Conversion functions. ToTpmTYPE puts a value of type TYPE into a TPM + * command buffer. FromTpmTYPE gets a value of type TYPE from a TPM command + * buffer into a variable. + */ +__attribute__((unused)) +static inline void ToTpmUint32(uint8_t *buffer, uint32_t x) { + buffer[0] = (uint8_t)(x >> 24); + buffer[1] = (uint8_t)((x >> 16) & 0xff); + buffer[2] = (uint8_t)((x >> 8) & 0xff); + buffer[3] = (uint8_t)(x & 0xff); +} + +/* + * See comment for above function. + */ +__attribute__((unused)) +static inline void FromTpmUint32(const uint8_t *buffer, uint32_t *x) { + *x = ((buffer[0] << 24) | + (buffer[1] << 16) | + (buffer[2] << 8) | + buffer[3]); +} + +/* + * See comment for above function. + */ +__attribute__((unused)) +static inline void ToTpmUint16(uint8_t *buffer, uint16_t x) { + buffer[0] = (uint8_t)(x >> 8); + buffer[1] = (uint8_t)(x & 0xff); +} + +/* + * See comment for above function. + */ +__attribute__((unused)) +static inline void FromTpmUint16(const uint8_t *buffer, uint16_t *x) { + *x = (buffer[0] << 8) | buffer[1]; +} + +#endif /* TPM_LITE_TLCL_INTERNAL_H_ */ diff --git a/src/lib/tlcl_structures.h b/src/lib/tlcl_structures.h new file mode 100644 index 0000000..36c1bb9 --- /dev/null +++ b/src/lib/tlcl_structures.h @@ -0,0 +1,138 @@ +/* This file is automatically generated */ + +const struct s_tpm_extend_cmd{ + uint8_t buffer[34]; + uint16_t pcrNum; + uint16_t inDigest; +} tpm_extend_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14, }, +10, 14, }; + +const struct s_tpm_get_random_cmd{ + uint8_t buffer[14]; + uint16_t bytesRequested; +} tpm_get_random_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x46, }, +10, }; + +const struct s_tpm_getownership_cmd{ + uint8_t buffer[22]; +} tpm_getownership_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x11, }, +}; + +const struct s_tpm_getpermissions_cmd{ + uint8_t buffer[22]; + uint16_t index; +} tpm_getpermissions_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x4, }, +18, }; + +const struct s_tpm_getstclearflags_cmd{ + uint8_t buffer[22]; +} tpm_getstclearflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x9, }, +}; + +const struct s_tpm_getflags_cmd{ + uint8_t buffer[22]; +} tpm_getflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x8, }, +}; + +const struct s_tpm_physicalsetdeactivated_cmd{ + uint8_t buffer[11]; + uint16_t deactivated; +} tpm_physicalsetdeactivated_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x72, }, +10, }; + +const struct s_tpm_physicalenable_cmd{ + uint8_t buffer[10]; +} tpm_physicalenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f, }, +}; + +const struct s_tpm_physicaldisable_cmd{ + uint8_t buffer[10]; +} tpm_physicaldisable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70, }, +}; + +const struct s_tpm_forceclear_cmd{ + uint8_t buffer[10]; +} tpm_forceclear_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d, }, +}; + +const struct s_tpm_readpubek_cmd{ + uint8_t buffer[30]; +} tpm_readpubek_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c, }, +}; + +const struct s_tpm_continueselftest_cmd{ + uint8_t buffer[10]; +} tpm_continueselftest_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53, }, +}; + +const struct s_tpm_selftestfull_cmd{ + uint8_t buffer[10]; +} tpm_selftestfull_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50, }, +}; + +const struct s_tpm_resume_cmd{ + uint8_t buffer[12]; +} tpm_resume_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2, }, +}; + +const struct s_tpm_savestate_cmd{ + uint8_t buffer[10]; +} tpm_savestate_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x98, }, +}; + +const struct s_tpm_startup_cmd{ + uint8_t buffer[12]; +} tpm_startup_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1, }, +}; + +const struct s_tpm_finalizepp_cmd{ + uint8_t buffer[12]; +} tpm_finalizepp_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x2, 0xa0, }, +}; + +const struct s_tpm_pplock_cmd{ + uint8_t buffer[12]; +} tpm_pplock_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x4, }, +}; + +const struct s_tpm_ppenable_cmd{ + uint8_t buffer[12]; +} tpm_ppenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x20, }, +}; + +const struct s_tpm_ppassert_cmd{ + uint8_t buffer[12]; +} tpm_ppassert_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x8, }, +}; + +const struct s_tpm_pcr_read_cmd{ + uint8_t buffer[14]; + uint16_t pcrNum; +} tpm_pcr_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x15, }, +10, }; + +const struct s_tpm_nv_read_cmd{ + uint8_t buffer[22]; + uint16_t index; + uint16_t length; +} tpm_nv_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf, }, +10, 18, }; + +const struct s_tpm_nv_write_cmd{ + uint8_t buffer[256]; + uint16_t index; + uint16_t length; + uint16_t data; +} tpm_nv_write_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, }, +10, 18, 22, }; + +const struct s_tpm_nv_definespace_cmd{ + uint8_t buffer[101]; + uint16_t index; + uint16_t perm; + uint16_t size; +} tpm_nv_definespace_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0xcc, 0x0, 0x18, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x17, }, +12, 70, 77, }; + +const int kWriteInfoLength = 12; +const int kNvDataPublicPermissionsOffset = 60; diff --git a/src/lib/tpm_error_messages.h b/src/lib/tpm_error_messages.h new file mode 100644 index 0000000..14cb86b --- /dev/null +++ b/src/lib/tpm_error_messages.h @@ -0,0 +1,250 @@ +/* Copyright (c) 2010 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* TPM error codes. + * + * Copy-pasted and lightly edited from TCG TPM Main Part 2 TPM Structures + * Version 1.2 Level 2 Revision 103 26 October 2006 Draft. + */ + +#ifndef TPM_ERROR_MESSAGES_H +#define TPM_ERROR_MESSAGES_H + +#define TPM_E_BASE 0x0 +#define TPM_E_NON_FATAL 0x800 + +typedef struct tpm_error_info { + const char* name; + uint32_t code; + const char* description; +} tpm_error_info; + +tpm_error_info tpm_error_table[] = { +{ "TPM_AUTHFAIL", TPM_E_BASE + 1, +"Authentication failed" }, +{ "TPM_BADINDEX", TPM_E_BASE + 2, +"The index to a PCR, DIR or other register is incorrect" }, +{ "TPM_BAD_PARAMETER", TPM_E_BASE + 3, +"One or more parameter is bad" }, +{ "TPM_AUDITFAILURE", TPM_E_BASE + 4, +"An operation completed successfully\n\ +but the auditing of that operation failed" }, +{ "TPM_CLEAR_DISABLED", TPM_E_BASE + 5, +"The clear disable flag is set and all clear operations now require\n\ +physical access" }, +{ "TPM_DEACTIVATED", TPM_E_BASE + 6, +"The TPM is deactivated" }, +{ "TPM_DISABLED", TPM_E_BASE + 7, +"The TPM is disabled" }, +{ "TPM_DISABLED_CMD", TPM_E_BASE + 8, +"The target command has been disabled" }, +{ "TPM_FAIL", TPM_E_BASE + 9, +"The operation failed" }, +{ "TPM_BAD_ORDINAL", TPM_E_BASE + 10, +"The ordinal was unknown or inconsistent" }, +{ "TPM_INSTALL_DISABLED", TPM_E_BASE + 11, +"The ability to install an owner is disabled" }, +{ "TPM_INVALID_KEYHANDLE", TPM_E_BASE + 12, +"The key handle can not be interpreted" }, +{ "TPM_KEYNOTFOUND", TPM_E_BASE + 13, +"The key handle points to an invalid key" }, +{ "TPM_INAPPROPRIATE_ENC", TPM_E_BASE + 14, +"Unacceptable encryption scheme" }, +{ "TPM_MIGRATEFAIL", TPM_E_BASE + 15, +"Migration authorization failed" }, +{ "TPM_INVALID_PCR_INFO", TPM_E_BASE + 16, +"PCR information could not be interpreted" }, +{ "TPM_NOSPACE", TPM_E_BASE + 17, +"No room to load key" }, +{ "TPM_NOSRK", TPM_E_BASE + 18, +"There is no SRK set" }, +{ "TPM_NOTSEALED_BLOB", TPM_E_BASE + 19, +"An encrypted blob is invalid or was not created by this TPM" }, +{ "TPM_OWNER_SET", TPM_E_BASE + 20, +"There is already an Owner" }, +{ "TPM_RESOURCES", TPM_E_BASE + 21, +"The TPM has insufficient internal resources to perform the requested action" }, +{ "TPM_SHORTRANDOM", TPM_E_BASE + 22, +"A random string was too short" }, +{ "TPM_SIZE", TPM_E_BASE + 23, +"The TPM does not have the space to perform the operation" }, +{ "TPM_WRONGPCRVAL", TPM_E_BASE + 24, +"The named PCR value does not match the current PCR value" }, +{ "TPM_BAD_PARAM_SIZE", TPM_E_BASE + 25, +"The paramSize argument to the command has the incorrect value" }, +{ "TPM_SHA_THREAD", TPM_E_BASE + 26, +"There is no existing SHA-1 thread" }, +{ "TPM_SHA_ERROR", TPM_E_BASE + 27, +"The calculation is unable to proceed because the existing SHA-1\n\ +thread has already encountered an error" }, +{ "TPM_FAILEDSELFTEST", TPM_E_BASE + 28, +"Self-test has failed and the TPM has shutdown" }, +{ "TPM_AUTH2FAIL", TPM_E_BASE + 29, +"The authorization for the second key in a 2 key function\n\ +failed authorization" }, +{ "TPM_BADTAG", TPM_E_BASE + 30, +"The tag value sent to for a command is invalid" }, +{ "TPM_IOERROR", TPM_E_BASE + 31, +"An IO error occurred transmitting information to the TPM" }, +{ "TPM_ENCRYPT_ERROR", TPM_E_BASE + 32, +"The encryption process had a problem" }, +{ "TPM_DECRYPT_ERROR", TPM_E_BASE + 33, +"The decryption process did not complete" }, +{ "TPM_INVALID_AUTHHANDLE", TPM_E_BASE + 34, +"An invalid handle was used" }, +{ "TPM_NO_ENDORSEMENT", TPM_E_BASE + 35, +"The TPM does not a EK installed" }, +{ "TPM_INVALID_KEYUSAGE", TPM_E_BASE + 36, +"The usage of a key is not allowed" }, +{ "TPM_WRONG_ENTITYTYPE", TPM_E_BASE + 37, +"The submitted entity type is not allowed" }, +{ "TPM_INVALID_POSTINIT", TPM_E_BASE + 38, +"The command was received in the wrong sequence relative to TPM_Init\n\ +and a subsequent TPM_Startup" }, +{ "TPM_INAPPROPRIATE_SIG", TPM_E_BASE + 39, +"Signed data cannot include additional DER information" }, +{ "TPM_BAD_KEY_PROPERTY", TPM_E_BASE + 40, +"The key properties in TPM_KEY_PARMs are not supported by this TPM" }, +{ "TPM_BAD_MIGRATION", TPM_E_BASE + 41, +"The migration properties of this key are incorrect" }, +{ "TPM_BAD_SCHEME", TPM_E_BASE + 42, +"The signature or encryption scheme for this key is incorrect or not\n\ +permitted in this situation" }, +{ "TPM_BAD_DATASIZE", TPM_E_BASE + 43, +"The size of the data (or blob) parameter is bad or inconsistent\n\ +with the referenced key" }, +{ "TPM_BAD_MODE", TPM_E_BASE + 44, +"A mode parameter is bad, such as capArea or subCapArea for\n\ +TPM_GetCapability, physicalPresence parameter for TPM_PhysicalPresence,\n\ +or migrationType for, TPM_CreateMigrationBlob" }, +{ "TPM_BAD_PRESENCE", TPM_E_BASE + 45, +"Either the physicalPresence or physicalPresenceLock bits\n\ +have the wrong value" }, +{ "TPM_BAD_VERSION", TPM_E_BASE + 46, +"The TPM cannot perform this version of the capability" }, +{ "TPM_NO_WRAP_TRANSPORT", TPM_E_BASE + 47, +"The TPM does not allow for wrapped transport sessions" }, +{ "TPM_AUDITFAIL_UNSUCCESSFUL", TPM_E_BASE + 48, +"TPM audit construction failed and the underlying command\n\ +was returning a failure code also" }, +{ "TPM_AUDITFAIL_SUCCESSFUL", TPM_E_BASE + 49, +"TPM audit construction failed and the underlying command\n\ +was returning success" }, +{ "TPM_NOTRESETABLE", TPM_E_BASE + 50, +"Attempt to reset a PCR register that does not have the resettable attribute" }, +{ "TPM_NOTLOCAL", TPM_E_BASE + 51, +"Attempt to reset a PCR register that requires locality\n\ +and locality modifier not part of command transport" }, +{ "TPM_BAD_TYPE", TPM_E_BASE + 52, +"Make identity blob not properly typed" }, +{ "TPM_INVALID_RESOURCE", TPM_E_BASE + 53, +"When saving context identified resource type does not match actual resource" }, +{ "TPM_NOTFIPS", TPM_E_BASE + 54, +"The TPM is attempting to execute a command only available when in FIPS mode" }, +{ "TPM_INVALID_FAMILY", TPM_E_BASE + 55, +"The command is attempting to use an invalid family ID" }, +{ "TPM_NO_NV_PERMISSION", TPM_E_BASE + 56, +"The permission to manipulate the NV storage is not available" }, +{ "TPM_REQUIRES_SIGN", TPM_E_BASE + 57, +"The operation requires a signed command" }, +{ "TPM_KEY_NOTSUPPORTED", TPM_E_BASE + 58, +"Wrong operation to load an NV key" }, +{ "TPM_AUTH_CONFLICT", TPM_E_BASE + 59, +"NV_LoadKey blob requires both owner and blob authorization" }, +{ "TPM_AREA_LOCKED", TPM_E_BASE + 60, +"The NV area is locked and not writable" }, +{ "TPM_BAD_LOCALITY", TPM_E_BASE + 61, +"The locality is incorrect for the attempted operation" }, +{ "TPM_READ_ONLY", TPM_E_BASE + 62, +"The NV area is read only and canât be written to" }, +{ "TPM_PER_NOWRITE", TPM_E_BASE + 63, +"There is no protection on the write to the NV area" }, +{ "TPM_FAMILYCOUNT", TPM_E_BASE + 64, +"The family count value does not match" }, +{ "TPM_WRITE_LOCKED", TPM_E_BASE + 65, +"The NV area has already been written to" }, +{ "TPM_BAD_ATTRIBUTES", TPM_E_BASE + 66, +"The NV area attributes conflict" }, +{ "TPM_INVALID_STRUCTURE", TPM_E_BASE + 67, +"The structure tag and version are invalid or inconsistent" }, +{ "TPM_KEY_OWNER_CONTROL", TPM_E_BASE + 68, +"The key is under control of the TPM Owner and can only be evicted\n\ +by the TPM Owner" }, +{ "TPM_BAD_COUNTER", TPM_E_BASE + 69, +"The counter handle is incorrect" }, +{ "TPM_NOT_FULLWRITE", TPM_E_BASE + 70, +"The write is not a complete write of the area" }, +{ "TPM_CONTEXT_GAP", TPM_E_BASE + 71, +"The gap between saved context counts is too large" }, +{ "TPM_MAXNVWRITES", TPM_E_BASE + 72, +"The maximum number of NV writes without an owner has been exceeded" }, +{ "TPM_NOOPERATOR", TPM_E_BASE + 73, +"No operator AuthData value is set" }, +{ "TPM_RESOURCEMISSING", TPM_E_BASE + 74, +"The resource pointed to by context is not loaded" }, +{ "TPM_DELEGATE_LOCK", TPM_E_BASE + 75, +"The delegate administration is locked" }, +{ "TPM_DELEGATE_FAMILY", TPM_E_BASE + 76, +"Attempt to manage a family other then the delegated family" }, +{ "TPM_DELEGATE_ADMIN", TPM_E_BASE + 77, +"Delegation table management not enabled" }, +{ "TPM_TRANSPORT_NOTEXCLUSIVE", TPM_E_BASE + 78, +"There was a command executed outside of an exclusive transport session" }, +{ "TPM_OWNER_CONTROL", TPM_E_BASE + 79, +"Attempt to context save a owner evict controlled key" }, +{ "TPM_DAA_RESOURCES", TPM_E_BASE + 80, +"The DAA command has no resources available to execute the command" }, +{ "TPM_DAA_INPUT_DATA0", TPM_E_BASE + 81, +"The consistency check on DAA parameter inputData0 has failed" }, +{ "TPM_DAA_INPUT_DATA1", TPM_E_BASE + 82, +"The consistency check on DAA parameter inputData1 has failed" }, +{ "TPM_DAA_ISSUER_SETTINGS", TPM_E_BASE + 83, +"The consistency check on DAA_issuerSettings has failed" }, +{ "TPM_DAA_TPM_SETTINGS", TPM_E_BASE + 84, +"The consistency check on DAA_tpmSpecific has failed" }, +{ "TPM_DAA_STAGE", TPM_E_BASE + 85, +"The atomic process indicated by the submitted DAA command is not\n\ +the expected process" }, +{ "TPM_DAA_ISSUER_VALIDITY", TPM_E_BASE + 86, +"The issuerâs validity check has detected an inconsistency" }, +{ "TPM_DAA_WRONG_W", TPM_E_BASE + 87, +"The consistency check on w has failed" }, +{ "TPM_BAD_HANDLE", TPM_E_BASE + 88, +"The handle is incorrect" }, +{ "TPM_BAD_DELEGATE", TPM_E_BASE + 89, +"Delegation is not correct" }, +{ "TPM_BADCONTEXT", TPM_E_BASE + 90, +"The context blob is invalid" }, +{ "TPM_TOOMANYCONTEXTS", TPM_E_BASE + 91, +"Too many contexts held by the TPM" }, +{ "TPM_MA_TICKET_SIGNATURE", TPM_E_BASE + 92, +"Migration authority signature validation failure" }, +{ "TPM_MA_DESTINATION", TPM_E_BASE + 93, +"Migration destination not authenticated" }, +{ "TPM_MA_SOURCE", TPM_E_BASE + 94, +"Migration source incorrect" }, +{ "TPM_MA_AUTHORITY", TPM_E_BASE + 95, +"Incorrect migration authority" }, +{ "TPM_PERMANENTEK", TPM_E_BASE + 97, +"Attempt to revoke the EK and the EK is not revocable" }, +{ "TPM_BAD_SIGNATURE", TPM_E_BASE + 98, +"Bad signature of CMK ticket" }, +{ "TPM_NOCONTEXTSPACE", TPM_E_BASE + 99, +"There is no room in the context list for additional contexts" }, +{ "TPM_RETRY", TPM_E_BASE + TPM_E_NON_FATAL, +"The TPM is too busy to respond to the command immediately, but\n\ +the command could be resubmitted at a later time. The TPM MAY\n\ +return TPM_RETRY for any command at any time" }, +{ "TPM_NEEDS_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 1, +"TPM_ContinueSelfTest has not been run" }, +{ "TPM_DOING_SELFTEST", TPM_E_BASE + TPM_E_NON_FATAL + 2, +"The TPM is currently executing the actions of TPM_ContinueSelfTest\n\ +because the ordinal required resources that have not been tested" }, +{ "TPM_DEFEND_LOCK_RUNNING", TPM_E_BASE + TPM_E_NON_FATAL + 3, +"The TPM is defending against dictionary attacks and is in some\n\ +time-out period" }, + }; + +#endif /* TPM_ERROR_MESSAGES_H */ diff --git a/src/vendorcode/google/chromeos/antirollback.c b/src/vendorcode/google/chromeos/antirollback.c new file mode 100644 index 0000000..306e903 --- /dev/null +++ b/src/vendorcode/google/chromeos/antirollback.c @@ -0,0 +1,676 @@ +/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Functions for querying, manipulating and locking rollback indices + * stored in the TPM NVRAM. + */ + +#include "sysincludes.h" + +#include "crc8.h" +#include "rollback_index.h" +#include "tlcl.h" +#include "tss_constants.h" +#include "utility.h" +#include "vboot_api.h" + +#ifndef offsetof +#define offsetof(A,B) __builtin_offsetof(A,B) +#endif + +/* + * Provide protoypes for functions not in the header file. These prototypes + * fix -Wmissing-prototypes warnings. + */ +uint32_t ReadSpaceFirmware(RollbackSpaceFirmware *rsf); +uint32_t WriteSpaceFirmware(RollbackSpaceFirmware *rsf); +uint32_t ReadSpaceKernel(RollbackSpaceKernel *rsk); +uint32_t WriteSpaceKernel(RollbackSpaceKernel *rsk); + +#ifdef FOR_TEST +/* + * Compiling for unit test, so we need the real implementations of + * rollback functions. The unit test mocks the underlying tlcl + * functions, so this is ok to run on the host. + */ +#undef CHROMEOS_ENVIRONMENT +#undef DISABLE_ROLLBACK_TPM +#endif + +#define RETURN_ON_FAILURE(tpm_command) do { \ + uint32_t result_; \ + if ((result_ = (tpm_command)) != TPM_SUCCESS) { \ + VBDEBUG(("Rollback: %08x returned by " #tpm_command \ + "\n", (int)result_)); \ + return result_; \ + } \ + } while (0) + + +uint32_t TPMClearAndReenable(void) +{ + VBDEBUG(("TPM: Clear and re-enable\n")); + RETURN_ON_FAILURE(TlclForceClear()); + RETURN_ON_FAILURE(TlclSetEnable()); + RETURN_ON_FAILURE(TlclSetDeactivated(0)); + + return TPM_SUCCESS; +} + +uint32_t SafeWrite(uint32_t index, const void *data, uint32_t length) +{ + uint32_t result = TlclWrite(index, data, length); + if (result == TPM_E_MAXNVWRITES) { + RETURN_ON_FAILURE(TPMClearAndReenable()); + return TlclWrite(index, data, length); + } else { + return result; + } +} + +uint32_t SafeDefineSpace(uint32_t index, uint32_t perm, uint32_t size) +{ + uint32_t result = TlclDefineSpace(index, perm, size); + if (result == TPM_E_MAXNVWRITES) { + RETURN_ON_FAILURE(TPMClearAndReenable()); + return TlclDefineSpace(index, perm, size); + } else { + return result; + } +} + +/* Functions to read and write firmware and kernel spaces. */ +uint32_t ReadSpaceFirmware(RollbackSpaceFirmware *rsf) +{ + uint32_t r; + int attempts = 3; + + while (attempts--) { + r = TlclRead(FIRMWARE_NV_INDEX, rsf, + sizeof(RollbackSpaceFirmware)); + if (r != TPM_SUCCESS) + return r; + + /* + * No CRC in this version, so we'll create one when we write + * it. Note that we're marking this as version 2, not + * ROLLBACK_SPACE_FIRMWARE_VERSION, because version 2 just + * added the CRC. Later versions will need to set default + * values for any extra fields explicitly (probably here). + */ + if (rsf->struct_version < 2) { + /* Danger Will Robinson! Danger! */ + rsf->struct_version = 2; + return TPM_SUCCESS; + } + + /* + * If the CRC is good, we're done. If it's bad, try a couple + * more times to see if it gets better before we give up. It + * could just be noise. + */ + if (rsf->crc8 == Crc8(rsf, + offsetof(RollbackSpaceFirmware, crc8))) + return TPM_SUCCESS; + + VBDEBUG(("TPM: %s() - bad CRC\n", __func__)); + } + + VBDEBUG(("TPM: %s() - too many bad CRCs, giving up\n", __func__)); + return TPM_E_CORRUPTED_STATE; +} + +uint32_t WriteSpaceFirmware(RollbackSpaceFirmware *rsf) +{ + RollbackSpaceFirmware rsf2; + uint32_t r; + int attempts = 3; + + /* All writes should use struct_version 2 or greater. */ + if (rsf->struct_version < 2) + rsf->struct_version = 2; + rsf->crc8 = Crc8(rsf, offsetof(RollbackSpaceFirmware, crc8)); + + while (attempts--) { + r = SafeWrite(FIRMWARE_NV_INDEX, rsf, + sizeof(RollbackSpaceFirmware)); + /* Can't write, not gonna try again */ + if (r != TPM_SUCCESS) + return r; + + /* Read it back to be sure it got the right values. */ + r = ReadSpaceFirmware(&rsf2); /* This checks the CRC */ + if (r == TPM_SUCCESS) + return r; + + VBDEBUG(("TPM: %s() - bad CRC\n", __func__)); + /* Try writing it again. Maybe it was garbled on the way out. */ + } + + VBDEBUG(("TPM: %s() - too many bad CRCs, giving up\n", __func__)); + return TPM_E_CORRUPTED_STATE; +} + +uint32_t SetVirtualDevMode(int val) +{ + RollbackSpaceFirmware rsf; + + VBDEBUG(("TPM: Entering %s()\n", __func__)); + if (TPM_SUCCESS != ReadSpaceFirmware(&rsf)) + return VBERROR_TPM_FIRMWARE_SETUP; + + VBDEBUG(("TPM: flags were 0x%02x\n", rsf.flags)); + if (val) + rsf.flags |= FLAG_VIRTUAL_DEV_MODE_ON; + else + rsf.flags &= ~FLAG_VIRTUAL_DEV_MODE_ON; + /* + * NOTE: This doesn't update the FLAG_LAST_BOOT_DEVELOPER bit. That + * will be done by SetupTPM() on the next boot. + */ + VBDEBUG(("TPM: flags are now 0x%02x\n", rsf.flags)); + + if (TPM_SUCCESS != WriteSpaceFirmware(&rsf)) + return VBERROR_TPM_SET_BOOT_MODE_STATE; + + VBDEBUG(("TPM: Leaving %s()\n", __func__)); + return VBERROR_SUCCESS; +} + +uint32_t ReadSpaceKernel(RollbackSpaceKernel *rsk) +{ + uint32_t r; + int attempts = 3; + + while (attempts--) { + r = TlclRead(KERNEL_NV_INDEX, rsk, sizeof(RollbackSpaceKernel)); + if (r != TPM_SUCCESS) + return r; + + /* + * No CRC in this version, so we'll create one when we write + * it. Note that we're marking this as version 2, not + * ROLLBACK_SPACE_KERNEL_VERSION, because version 2 just added + * the CRC. Later versions will need to set default values for + * any extra fields explicitly (probably here). + */ + if (rsk->struct_version < 2) { + /* Danger Will Robinson! Danger! */ + rsk->struct_version = 2; + return TPM_SUCCESS; + } + + /* + * If the CRC is good, we're done. If it's bad, try a couple + * more times to see if it gets better before we give up. It + * could just be noise. + */ + if (rsk->crc8 == Crc8(rsk, offsetof(RollbackSpaceKernel, crc8))) + return TPM_SUCCESS; + + VBDEBUG(("TPM: %s() - bad CRC\n", __func__)); + } + + VBDEBUG(("TPM: %s() - too many bad CRCs, giving up\n", __func__)); + return TPM_E_CORRUPTED_STATE; +} + +uint32_t WriteSpaceKernel(RollbackSpaceKernel *rsk) +{ + RollbackSpaceKernel rsk2; + uint32_t r; + int attempts = 3; + + /* All writes should use struct_version 2 or greater. */ + if (rsk->struct_version < 2) + rsk->struct_version = 2; + rsk->crc8 = Crc8(rsk, offsetof(RollbackSpaceKernel, crc8)); + + while (attempts--) { + r = SafeWrite(KERNEL_NV_INDEX, rsk, + sizeof(RollbackSpaceKernel)); + /* Can't write, not gonna try again */ + if (r != TPM_SUCCESS) + return r; + + /* Read it back to be sure it got the right values. */ + r = ReadSpaceKernel(&rsk2); /* This checks the CRC */ + if (r == TPM_SUCCESS) + return r; + + VBDEBUG(("TPM: %s() - bad CRC\n", __func__)); + /* Try writing it again. Maybe it was garbled on the way out. */ + } + + VBDEBUG(("TPM: %s() - too many bad CRCs, giving up\n", __func__)); + return TPM_E_CORRUPTED_STATE; +} + +uint32_t OneTimeInitializeTPM(RollbackSpaceFirmware *rsf, + RollbackSpaceKernel *rsk) +{ + static const RollbackSpaceFirmware rsf_init = { + .struct_version = ROLLBACK_SPACE_FIRMWARE_VERSION, + }; + static const RollbackSpaceKernel rsk_init = { + .struct_version = ROLLBACK_SPACE_KERNEL_VERSION, + .uid = ROLLBACK_SPACE_KERNEL_UID, + }; + TPM_PERMANENT_FLAGS pflags; + uint32_t result; + + VBDEBUG(("TPM: One-time initialization\n")); + + /* + * Do a full test. This only happens the first time the device is + * turned on in the factory, so performance is not an issue. This is + * almost certainly not necessary, but it gives us more confidence + * about some code paths below that are difficult to + * test---specifically the ones that set lifetime flags, and are only + * executed once per physical TPM. + */ + result = TlclSelfTestFull(); + if (result != TPM_SUCCESS) + return result; + + result = TlclGetPermanentFlags(&pflags); + if (result != TPM_SUCCESS) + return result; + + /* + * TPM may come from the factory without physical presence finalized. + * Fix if necessary. + */ + VBDEBUG(("TPM: physicalPresenceLifetimeLock=%d\n", + pflags.physicalPresenceLifetimeLock)); + if (!pflags.physicalPresenceLifetimeLock) { + VBDEBUG(("TPM: Finalizing physical presence\n")); + RETURN_ON_FAILURE(TlclFinalizePhysicalPresence()); + } + + /* + * The TPM will not enforce the NV authorization restrictions until the + * execution of a TPM_NV_DefineSpace with the handle of + * TPM_NV_INDEX_LOCK. Here we create that space if it doesn't already + * exist. */ + VBDEBUG(("TPM: nvLocked=%d\n", pflags.nvLocked)); + if (!pflags.nvLocked) { + VBDEBUG(("TPM: Enabling NV locking\n")); + RETURN_ON_FAILURE(TlclSetNvLocked()); + } + + /* Clear TPM owner, in case the TPM is already owned for some reason. */ + VBDEBUG(("TPM: Clearing owner\n")); + RETURN_ON_FAILURE(TPMClearAndReenable()); + + /* Initializes the firmware and kernel spaces */ + Memcpy(rsf, &rsf_init, sizeof(RollbackSpaceFirmware)); + Memcpy(rsk, &rsk_init, sizeof(RollbackSpaceKernel)); + + /* Define the backup space. No need to initialize it, though. */ + RETURN_ON_FAILURE(SafeDefineSpace( + BACKUP_NV_INDEX, TPM_NV_PER_PPWRITE, BACKUP_NV_SIZE)); + + /* Define and initialize the kernel space */ + RETURN_ON_FAILURE(SafeDefineSpace(KERNEL_NV_INDEX, TPM_NV_PER_PPWRITE, + sizeof(RollbackSpaceKernel))); + RETURN_ON_FAILURE(WriteSpaceKernel(rsk)); + + /* Do the firmware space last, so we retry if we don't get this far. */ + RETURN_ON_FAILURE(SafeDefineSpace( + FIRMWARE_NV_INDEX, + TPM_NV_PER_GLOBALLOCK | TPM_NV_PER_PPWRITE, + sizeof(RollbackSpaceFirmware))); + RETURN_ON_FAILURE(WriteSpaceFirmware(rsf)); + + return TPM_SUCCESS; +} + + +/* + * SetupTPM starts the TPM and establishes the root of trust for the + * anti-rollback mechanism. SetupTPM can fail for three reasons. 1 A bug. 2 a + * TPM hardware failure. 3 An unexpected TPM state due to some attack. In + * general we cannot easily distinguish the kind of failure, so our strategy is + * to reboot in recovery mode in all cases. The recovery mode calls SetupTPM + * again, which executes (almost) the same sequence of operations. There is a + * good chance that, if recovery mode was entered because of a TPM failure, the + * failure will repeat itself. (In general this is impossible to guarantee + * because we have no way of creating the exact TPM initial state at the + * previous boot.) In recovery mode, we ignore the failure and continue, thus + * giving the recovery kernel a chance to fix things (that's why we don't set + * bGlobalLock). The choice is between a knowingly insecure device and a + * bricked device. + * + * As a side note, observe that we go through considerable hoops to avoid using + * the STCLEAR permissions for the index spaces. We do this to avoid writing + * to the TPM flashram at every reboot or wake-up, because of concerns about + * the durability of the NVRAM. + */ +uint32_t SetupTPM(int developer_mode, int disable_dev_request, + int clear_tpm_owner_request, RollbackSpaceFirmware* rsf) +{ + uint8_t in_flags; + uint8_t disable; + uint8_t deactivated; + uint32_t result; + uint32_t versions; + + RETURN_ON_FAILURE(TlclLibInit()); + +#ifdef TEGRA_SOFT_REBOOT_WORKAROUND + result = TlclStartup(); + if (result == TPM_E_INVALID_POSTINIT) { + /* + * Some prototype hardware doesn't reset the TPM on a CPU + * reset. We do a hard reset to get around this. + */ + VBDEBUG(("TPM: soft reset detected\n", result)); + return TPM_E_MUST_REBOOT; + } else if (result != TPM_SUCCESS) { + VBDEBUG(("TPM: TlclStartup returned %08x\n", result)); + return result; + } +#else + RETURN_ON_FAILURE(TlclStartup()); +#endif + + /* + * Some TPMs start the self test automatically at power on. In that case we + * don't need to call ContinueSelfTest. On some (other) TPMs, + * ContinueSelfTest may block. In that case, we definitely don't want to + * call it here. For TPMs in the intersection of these two sets, we're + * screwed. (In other words: TPMs that require manually starting the + * self-test AND block will have poor performance until we split + * TlclSendReceive() into Send() and Receive(), and have a state machine to + * control setup.) + * + * This comment is likely to become obsolete in the near future, so don't + * trust it. It may have not been updated. + */ +#ifdef TPM_MANUAL_SELFTEST +#ifdef TPM_BLOCKING_CONTINUESELFTEST +#warning "lousy TPM!" +#endif + RETURN_ON_FAILURE(TlclContinueSelfTest()); +#endif + result = TlclAssertPhysicalPresence(); + if (result != TPM_SUCCESS) { + /* + * It is possible that the TPM was delivered with the physical + * presence command disabled. This tries enabling it, then + * tries asserting PP again. + */ + RETURN_ON_FAILURE(TlclPhysicalPresenceCMDEnable()); + RETURN_ON_FAILURE(TlclAssertPhysicalPresence()); + } + + /* Check that the TPM is enabled and activated. */ + RETURN_ON_FAILURE(TlclGetFlags(&disable, &deactivated, NULL)); + if (disable || deactivated) { + VBDEBUG(("TPM: disabled (%d) or deactivated (%d). Fixing...\n", + disable, deactivated)); + RETURN_ON_FAILURE(TlclSetEnable()); + RETURN_ON_FAILURE(TlclSetDeactivated(0)); + VBDEBUG(("TPM: Must reboot to re-enable\n")); + return TPM_E_MUST_REBOOT; + } + + /* Read the firmware space. */ + result = ReadSpaceFirmware(rsf); + if (TPM_E_BADINDEX == result) { + RollbackSpaceKernel rsk; + + /* + * This is the first time we've run, and the TPM has not been + * initialized. Initialize it. + */ + VBDEBUG(("TPM: Not initialized yet.\n")); + RETURN_ON_FAILURE(OneTimeInitializeTPM(rsf, &rsk)); + } else if (TPM_SUCCESS != result) { + VBDEBUG(("TPM: Firmware space in a bad state; giving up.\n")); + return TPM_E_CORRUPTED_STATE; + } + Memcpy(&versions, &rsf->fw_versions, sizeof(versions)); + VBDEBUG(("TPM: Firmware space sv%d f%x v%x\n", + rsf->struct_version, rsf->flags, versions)); + in_flags = rsf->flags; + + /* If we've been asked to clear the virtual dev-mode flag, do so now */ + if (disable_dev_request) { + rsf->flags &= ~FLAG_VIRTUAL_DEV_MODE_ON; + VBDEBUG(("TPM: Clearing virt dev-switch: f%x\n", rsf->flags)); + } + + /* + * The developer_mode value that's passed in is only set by a hardware + * dev-switch. We should OR it with the virtual switch, whether or not + * the virtual switch is used. If it's not used, it shouldn't change, + * so it doesn't matter. + */ + if (rsf->flags & FLAG_VIRTUAL_DEV_MODE_ON) + developer_mode = 1; + + /* + * Clear ownership if developer flag has toggled, or if an owner-clear + * has been requested. + */ + if ((developer_mode ? FLAG_LAST_BOOT_DEVELOPER : 0) != + (in_flags & FLAG_LAST_BOOT_DEVELOPER)) { + VBDEBUG(("TPM: Developer flag changed; clearing owner.\n")); + RETURN_ON_FAILURE(TPMClearAndReenable()); + } else if (clear_tpm_owner_request) { + VBDEBUG(("TPM: Clearing owner as specifically requested.\n")); + RETURN_ON_FAILURE(TPMClearAndReenable()); + } + + if (developer_mode) + rsf->flags |= FLAG_LAST_BOOT_DEVELOPER; + else + rsf->flags &= ~FLAG_LAST_BOOT_DEVELOPER; + + + /* If firmware space is dirty, flush it back to the TPM */ + if (rsf->flags != in_flags) { + VBDEBUG(("TPM: Updating firmware space.\n")); + RETURN_ON_FAILURE(WriteSpaceFirmware(rsf)); + } + + VBDEBUG(("TPM: SetupTPM() succeeded\n")); + return TPM_SUCCESS; +} + + +#ifdef DISABLE_ROLLBACK_TPM +/* Dummy implementations which don't support TPM rollback protection */ + +uint32_t RollbackS3Resume(void) +{ +#ifndef CHROMEOS_ENVIRONMENT + /* + * Initialize the TPM, but ignore return codes. In ChromeOS + * environment, don't even talk to the TPM. + */ + TlclLibInit(); + TlclResume(); +#endif + return TPM_SUCCESS; +} + +uint32_t RollbackFirmwareSetup(int is_hw_dev, + int disable_dev_request, + int clear_tpm_owner_request, + int *is_virt_dev, uint32_t *version) +{ +#ifndef CHROMEOS_ENVIRONMENT + /* + * Initialize the TPM, but ignores return codes. In ChromeOS + * environment, don't even talk to the TPM. + */ + TlclLibInit(); + TlclStartup(); + TlclContinueSelfTest(); +#endif + *is_virt_dev = 0; + *version = 0; + return TPM_SUCCESS; +} + +uint32_t RollbackFirmwareWrite(uint32_t version) +{ + return TPM_SUCCESS; +} + +uint32_t RollbackFirmwareLock(void) +{ + return TPM_SUCCESS; +} + +uint32_t RollbackKernelRead(uint32_t* version) +{ + *version = 0; + return TPM_SUCCESS; +} + +uint32_t RollbackKernelWrite(uint32_t version) +{ + return TPM_SUCCESS; +} + +uint32_t RollbackBackupRead(uint8_t *raw) +{ + return TPM_SUCCESS; +} + +uint32_t RollbackBackupWrite(uint8_t *raw) +{ + return TPM_SUCCESS; +} + +uint32_t RollbackKernelLock(int recovery_mode) +{ + return TPM_SUCCESS; +} + +#else + +uint32_t RollbackS3Resume(void) +{ + uint32_t result; + RETURN_ON_FAILURE(TlclLibInit()); + result = TlclResume(); + if (result == TPM_E_INVALID_POSTINIT) { + /* + * We're on a platform where the TPM maintains power in S3, so + * it's already initialized. + */ + return TPM_SUCCESS; + } + return result; +} + +uint32_t RollbackFirmwareSetup(int is_hw_dev, + int disable_dev_request, + int clear_tpm_owner_request, + int *is_virt_dev, uint32_t *version) +{ + RollbackSpaceFirmware rsf; + + /* Set version to 0 in case we fail */ + *version = 0; + + RETURN_ON_FAILURE(SetupTPM(is_hw_dev, disable_dev_request, + clear_tpm_owner_request, &rsf)); + Memcpy(version, &rsf.fw_versions, sizeof(*version)); + *is_virt_dev = (rsf.flags & FLAG_VIRTUAL_DEV_MODE_ON) ? 1 : 0; + VBDEBUG(("TPM: RollbackFirmwareSetup %x\n", (int)*version)); + return TPM_SUCCESS; +} + +uint32_t RollbackFirmwareWrite(uint32_t version) +{ + RollbackSpaceFirmware rsf; + uint32_t old_version; + + RETURN_ON_FAILURE(ReadSpaceFirmware(&rsf)); + Memcpy(&old_version, &rsf.fw_versions, sizeof(old_version)); + VBDEBUG(("TPM: RollbackFirmwareWrite %x --> %x\n", (int)old_version, + (int)version)); + Memcpy(&rsf.fw_versions, &version, sizeof(version)); + return WriteSpaceFirmware(&rsf); +} + +uint32_t RollbackFirmwareLock(void) +{ + return TlclSetGlobalLock(); +} + +uint32_t RollbackKernelRead(uint32_t* version) +{ + RollbackSpaceKernel rsk; + uint32_t perms, uid; + + /* + * Read the kernel space and verify its permissions. If the kernel + * space has the wrong permission, or it doesn't contain the right + * identifier, we give up. This will need to be fixed by the + * recovery kernel. We have to worry about this because at any time + * (even with PP turned off) the TPM owner can remove and redefine a + * PP-protected space (but not write to it). + */ + RETURN_ON_FAILURE(ReadSpaceKernel(&rsk)); + RETURN_ON_FAILURE(TlclGetPermissions(KERNEL_NV_INDEX, &perms)); + Memcpy(&uid, &rsk.uid, sizeof(uid)); + if (TPM_NV_PER_PPWRITE != perms || ROLLBACK_SPACE_KERNEL_UID != uid) + return TPM_E_CORRUPTED_STATE; + + Memcpy(version, &rsk.kernel_versions, sizeof(*version)); + VBDEBUG(("TPM: RollbackKernelRead %x\n", (int)*version)); + return TPM_SUCCESS; +} + +uint32_t RollbackKernelWrite(uint32_t version) +{ + RollbackSpaceKernel rsk; + uint32_t old_version; + RETURN_ON_FAILURE(ReadSpaceKernel(&rsk)); + Memcpy(&old_version, &rsk.kernel_versions, sizeof(old_version)); + VBDEBUG(("TPM: RollbackKernelWrite %x --> %x\n", + (int)old_version, (int)version)); + Memcpy(&rsk.kernel_versions, &version, sizeof(version)); + return WriteSpaceKernel(&rsk); +} + +/* + * We don't really care whether the TPM owner has been messing with this or + * not. We lock it along with the Kernel space just to avoid problems, but it's + * only useful in dev-mode and only when the battery has been drained + * completely. There aren't any security issues. It's just in the TPM because + * we don't have any other place to keep it. + */ +uint32_t RollbackBackupRead(uint8_t *raw) +{ + uint32_t r; + r = TlclRead(BACKUP_NV_INDEX, raw, BACKUP_NV_SIZE); + VBDEBUG(("TPM: %s returning 0x%x\n", __func__, r)); + return r; +} + +uint32_t RollbackBackupWrite(uint8_t *raw) +{ + uint32_t r; + r = TlclWrite(BACKUP_NV_INDEX, raw, BACKUP_NV_SIZE); + VBDEBUG(("TPM: %s returning 0x%x\n", __func__, r)); + return r; +} + +uint32_t RollbackKernelLock(int recovery_mode) +{ + if (recovery_mode) + return TPM_SUCCESS; + else + return TlclLockPhysicalPresence(); +} + +#endif /* DISABLE_ROLLBACK_TPM */

1 0

Patch set updated for coreboot: a4a3642 vboot_wrapper: handling VBERROR_TPM_REBOOT_REQUIRED from VbInit().
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8163 -gerrit commit a4a36429b329b2d8a1ac7f8faa88ed62dcbb57bf Author: Kevin Cheng <kevin.cheng(a)intel.com> Date: Mon Jun 30 17:51:48 2014 -0700 vboot_wrapper: handling VBERROR_TPM_REBOOT_REQUIRED from VbInit(). Doing reset while VBERROR_TPM_REBOOT_REQUIRED occured. BUG=chromium:389568 TEST=Manual force VBERROR_TPM_REBOOT_REQUIRED returned from VbInit() and system will reboot. Original-Change-Id: I9d7c4b3a380a931a728f792b4013b3b9bf65dfae Original-Signed-off-by: Kevin Cheng <kevin.cheng(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206337 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> (cherry picked from commit 32728dd9fc43a95d6f763a85f9cc7a660a66b175) Original-Reviewed-on: https://chromium-review.googlesource.com/206948 Original-Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> (cherry picked from commit 1ea5e233386d236ce20f3d1695fac3a1bc49d4bd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib93fdf7b22918f563d3e29207a75fc831bee186a --- src/vendorcode/google/chromeos/vboot_context.h | 1 + src/vendorcode/google/chromeos/vboot_loader.c | 6 ++++++ src/vendorcode/google/chromeos/vboot_wrapper.c | 7 ++++++- 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/vboot_context.h b/src/vendorcode/google/chromeos/vboot_context.h index 822fed4..cd82aac 100644 --- a/src/vendorcode/google/chromeos/vboot_context.h +++ b/src/vendorcode/google/chromeos/vboot_context.h @@ -57,6 +57,7 @@ struct vboot_context { void (*log_msg)(const char *fmt, va_list args); void (*fatal_error)(void); void *(*get_region)(uintptr_t offset_addr, size_t size, void *dest); + void (*reset)(void); }; #endif /* VBOOT_CONTEXT_H */ diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 80e2aea..daf5260 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -229,6 +229,11 @@ static void vboot_clean_up(struct vboot_context *context) cbmem_entry_remove(context->vblocks); } +static void reset(void) +{ + hard_reset(); +} + static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) { VbCommonParams cparams; @@ -298,6 +303,7 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) context.log_msg = &log_msg; context.fatal_error = &fatal_error; context.get_region = &vboot_get_region; + context.reset = &reset; vboot_run_stub(&context); diff --git a/src/vendorcode/google/chromeos/vboot_wrapper.c b/src/vendorcode/google/chromeos/vboot_wrapper.c index 5aa0066..dd6065c 100644 --- a/src/vendorcode/google/chromeos/vboot_wrapper.c +++ b/src/vendorcode/google/chromeos/vboot_wrapper.c @@ -43,8 +43,13 @@ static void vboot_wrapper(void *arg) res = VbInit(context->cparams, &context->handoff->init_params); VbExDebug("VbInit() returned 0x%08x\n", res); - if (res != VBERROR_SUCCESS) + if (res != VBERROR_SUCCESS) { + if(res == VBERROR_TPM_REBOOT_REQUIRED) { + VbExDebug("TPM Reboot Required. Proceeding reboot.\n"); + gcontext->reset(); + } return; + } VbExDebug("Calling VbSelectFirmware()\n"); res = VbSelectFirmware(context->cparams, context->fparams);

1 0

Patch set updated for coreboot: 024a959 vboot2: read dev and recovery switch
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8162 -gerrit commit 024a959967fe7f1a27ba705ad6d23b6ba7788d65 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jun 30 09:56:32 2014 -0700 vboot2: read dev and recovery switch TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=none Branch=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: Ia5353018a0db3dae2e0432b7e6a34d46f81b0ffa Original-Reviewed-on: https://chromium-review.googlesource.com/206064 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit b420451c71c86bc27784d920f53870ee56ddc0f2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I30c9f0ac44de0a5816b5b8d0ded2dc7d7e77c7a1 --- src/ec/google/chromeec/Makefile.inc | 7 +++++++ src/mainboard/google/nyan_blaze/Makefile.inc | 1 + src/vendorcode/google/chromeos/vboot_main.c | 12 ++++++------ 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 541bb13..0df6e8b 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -10,3 +10,10 @@ romstage-y += ec.c crosec_proto.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c +ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y) +verstage-y += ec.c crosec_proto.c +verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c +verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c +endif + diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index 02b3977..dec8f64 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -32,6 +32,7 @@ bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c +verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += reset.c romstage-y += reset.c diff --git a/src/vendorcode/google/chromeos/vboot_main.c b/src/vendorcode/google/chromeos/vboot_main.c index 907afd7..8251cfd 100644 --- a/src/vendorcode/google/chromeos/vboot_main.c +++ b/src/vendorcode/google/chromeos/vboot_main.c @@ -264,12 +264,12 @@ void __attribute__((noinline)) select_firmware(void) * invalid secdata and tell us what to do (=reboot). */ //antirollback_read_space_firmware(&ctx); - //if (get_developer_mode_switch()) - // ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; - //if (get_recovery_mode_switch()) { - // clear_recovery_mode_switch(); - // ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; - //} + if (get_developer_mode_switch()) + ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; + if (get_recovery_mode_switch()) { + clear_recovery_mode_switch(); + ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; + } /* Do early init */ VBDEBUG("Phase 1\n");

1 0

Patch set updated for coreboot: 96e0f2f vboot2: implement vb2ex_read_resource
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8161 -gerrit commit 96e0f2f24e79cd660abfd7a563c77bb32aef525d Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Jun 30 08:28:17 2014 -0700 vboot2: implement vb2ex_read_resource TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: I633f9dddbf8b2f25797aacc246bcebaafb02bea4 Original-Reviewed-on: https://chromium-review.googlesource.com/206063 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri(a)chromium.org> (cherry picked from commit 1f215672de31847cc647e83d2c04633b7f8dfa33) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I57f449b052132b300f7bca4351871c539a7a8694 --- src/vendorcode/google/chromeos/vboot_main.c | 55 +++++++++++++++++++---------- 1 file changed, 37 insertions(+), 18 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot_main.c b/src/vendorcode/google/chromeos/vboot_main.c index 9779d35..907afd7 100644 --- a/src/vendorcode/google/chromeos/vboot_main.c +++ b/src/vendorcode/google/chromeos/vboot_main.c @@ -31,6 +31,23 @@ struct vboot_region { int32_t size; }; +static void locate_region(const char *name, struct vboot_region *region) +{ + region->size = find_fmap_entry(name, (void **)&region->offset_addr); + VBDEBUG("Located %s @%x\n", name, region->offset_addr); +} + +static int is_slot_a(struct vb2_context *ctx) +{ + return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); +} + +static int in_ro(void) +{ + /* TODO: Implement */ + return 1; +} + /* exports */ void vb2ex_printf(const char *func, const char *fmt, ...) @@ -57,27 +74,29 @@ int vb2ex_read_resource(struct vb2_context *ctx, void *buf, uint32_t size) { - VBDEBUG("Reading resource\n"); - return VB2_ERROR_UNKNOWN; -} + struct vboot_region region; + + switch (index) { + case VB2_RES_GBB: + locate_region("GBB", &region); + break; + case VB2_RES_FW_VBLOCK: + if (is_slot_a(ctx)) + locate_region("VBLOCK_A", &region); + else + locate_region("VBLOCK_B", &region); + break; + default: + return VB2_ERROR_EX_READ_RESOURCE_INDEX; + } -/* locals */ + if (offset + size > region.size) + return VB2_ERROR_EX_READ_RESOURCE_SIZE; -static void locate_region(const char *name, struct vboot_region *region) -{ - region->size = find_fmap_entry(name, (void **)&region->offset_addr); - VBDEBUG("Located %s @%x\n", name, region->offset_addr); -} + if (vboot_get_region(region.offset_addr + offset, size, buf) == NULL) + return VB2_ERROR_UNKNOWN; -static int is_slot_a(struct vb2_context *ctx) -{ - return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); -} - -static int in_ro(void) -{ - /* TODO: Implement */ - return 1; + return VB2_SUCCESS; } static void reboot(void)

1 0

Patch set updated for coreboot: bfa24bc vboot2: add verstage
by Marc Jones 22 Jan '15

22 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8224 -gerrit commit bfa24bcaab9b6e6d39bcbd9937b7f5c348e89a79 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Jan 14 19:51:47 2015 +0100 vboot2: add verstage This reverts the revert commit 5780d6f3876723b94fbe3653c9d87dad6330862e and fixes the build issue that cuased it to be reverted. Verstage will host vboot2 for firmware verification. It's a stage in the sense that it has its own set of toolchains, compiler flags, and includes. This allows us to easily add object files as needed. But it's directly linked to bootblock. This allows us to avoid code duplication for stage loading and jumping (e.g. cbfs driver) for the boards where bootblock has to run in a different architecture (e.g. Tegra124). To avoid name space conflict, verstage symbols are prefixed with verstage_. TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze. BUG=None BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac Original-Reviewed-on: https://chromium-review.googlesource.com/204376 Original-Reviewed-by: Randall Spangler <rspangler(a)chromium.org> (cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf --- Makefile.inc | 9 ++++++++- src/arch/arm/Kconfig | 4 ++++ src/arch/arm/Makefile.inc | 2 +- src/arch/arm/armv4/Kconfig | 4 ++++ src/arch/arm/armv7/Kconfig | 4 ++++ src/arch/arm64/Kconfig | 4 ++++ src/arch/arm64/armv8/Kconfig | 3 +++ src/arch/riscv/Kconfig | 4 ++++ src/arch/x86/Kconfig | 4 ++++ src/cpu/allwinner/a10/Kconfig | 1 + src/cpu/amd/agesa/Kconfig | 1 + src/cpu/amd/geode_gx2/Kconfig | 1 + src/cpu/amd/geode_lx/Kconfig | 1 + src/cpu/amd/model_10xxx/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/cpu/amd/pi/Kconfig | 1 + src/cpu/armltd/cortex-a9/Kconfig | 1 + src/cpu/dmp/vortex86ex/Kconfig | 1 + src/cpu/intel/ep80579/Kconfig | 1 + src/cpu/intel/fsp_model_206ax/Kconfig | 1 + src/cpu/intel/fsp_model_406dx/Kconfig | 1 + src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/model_1067x/Kconfig | 1 + src/cpu/intel/model_106cx/Kconfig | 1 + src/cpu/intel/model_2065x/Kconfig | 1 + src/cpu/intel/model_206ax/Kconfig | 1 + src/cpu/intel/model_65x/Kconfig | 1 + src/cpu/intel/model_67x/Kconfig | 1 + src/cpu/intel/model_68x/Kconfig | 1 + src/cpu/intel/model_69x/Kconfig | 1 + src/cpu/intel/model_6bx/Kconfig | 1 + src/cpu/intel/model_6dx/Kconfig | 1 + src/cpu/intel/model_6ex/Kconfig | 1 + src/cpu/intel/model_6fx/Kconfig | 1 + src/cpu/intel/model_6xx/Kconfig | 1 + src/cpu/intel/model_f0x/Kconfig | 1 + src/cpu/intel/model_f1x/Kconfig | 1 + src/cpu/intel/model_f2x/Kconfig | 1 + src/cpu/intel/model_f3x/Kconfig | 1 + src/cpu/intel/model_f4x/Kconfig | 1 + src/cpu/qemu-x86/Kconfig | 1 + src/cpu/ti/am335x/Kconfig | 1 + src/cpu/via/c3/Kconfig | 1 + src/cpu/via/c7/Kconfig | 1 + src/cpu/via/nano/Kconfig | 1 + src/mainboard/bifferos/bifferboard/Kconfig | 1 + src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/broadwell/Kconfig | 1 + src/soc/intel/fsp_baytrail/Kconfig | 1 + src/soc/nvidia/tegra124/Kconfig | 1 + src/soc/nvidia/tegra124/Makefile.inc | 2 ++ src/soc/nvidia/tegra124/bootblock.c | 7 +++++-- src/soc/nvidia/tegra124/verstage.c | 9 +++++++++ src/soc/nvidia/tegra124/verstage.h | 2 ++ src/soc/qualcomm/ipq806x/Kconfig | 1 + src/soc/samsung/exynos5250/Kconfig | 1 + src/soc/samsung/exynos5420/Kconfig | 1 + src/soc/ucb/riscv/Kconfig | 1 + src/vendorcode/google/chromeos/Kconfig | 8 ++++++++ src/vendorcode/google/chromeos/Makefile.inc | 9 +++++++++ toolchain.inc | 2 +- 61 files changed, 117 insertions(+), 5 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index b0289c0..0c6aafa 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -75,7 +75,7 @@ subdirs-y += site-local ####################################################################### # Add source classes and their build options -classes-y := ramstage romstage bootblock smm smmstub cpu_microcode +classes-y := ramstage romstage bootblock smm smmstub cpu_microcode verstage # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ @@ -128,6 +128,8 @@ ramstage-postprocess=$(foreach d,$(sort $(dir $(1))), \ $(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(1)); $$(LD_ramstage) -o $$@ -r $$^ ) \ $(eval ramstage-objs:=$(d)ramstage.o $(filter-out $(call files-in-dir,$(d),$(1)),$(ramstage-objs)))) +verstage-c-ccopts:=-D__PRE_RAM__ -D__VER_STAGE__ +verstage-S-ccopts:=-D__PRE_RAM__ -D__VER_STAGE__ romstage-c-ccopts:=-D__PRE_RAM__ romstage-S-ccopts:=-D__PRE_RAM__ ifeq ($(CONFIG_TRACE),y) @@ -162,6 +164,7 @@ endif ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) +verstage-c-deps:=$$(OPTION_TABLE_H) bootblock-c-deps:=$$(OPTION_TABLE_H) smm-c-deps:=$$(OPTION_TABLE_H) @@ -374,6 +377,10 @@ $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $ @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_romstage) -MMD $(CFLAGS_romstage) $(CPPFLAGS_romstage) $(romstage-c-ccopts) -c -o $@ $< +$(obj)/%.verstage.o $(abspath $(obj))/%.verstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC_verstage) -MMD $(CFLAGS_verstage) $(verstage-c-ccopts) -c -o $@ $< + $(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) -MMD $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) $(bootblock-c-ccopts) -c -o $@ $< diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 156c8c2..1c3a339 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -3,6 +3,10 @@ config ARCH_BOOTBLOCK_ARM default n select ARCH_ARM +config ARCH_VERSTAGE_ARM + bool + default n + config ARCH_ROMSTAGE_ARM bool default n diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 5698f38..6f65a71 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -61,7 +61,7 @@ bootblock-y += memcpy.S bootblock-y += memmove.S bootblock-y += div0.c -$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) +$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $$(VERSTAGE_LIB) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm/bootblock.ld diff --git a/src/arch/arm/armv4/Kconfig b/src/arch/arm/armv4/Kconfig index e40a6e1..aa5fab9 100644 --- a/src/arch/arm/armv4/Kconfig +++ b/src/arch/arm/armv4/Kconfig @@ -2,6 +2,10 @@ config ARCH_BOOTBLOCK_ARMV4 def_bool n select ARCH_BOOTBLOCK_ARM +config ARCH_VERSTAGE_ARMV4 + def_bool n + select ARCH_VERSTAGE_ARM + config ARCH_ROMSTAGE_ARMV4 def_bool n select ARCH_ROMSTAGE_ARM diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig index f8e0205..aa188e2 100644 --- a/src/arch/arm/armv7/Kconfig +++ b/src/arch/arm/armv7/Kconfig @@ -2,6 +2,10 @@ config ARCH_BOOTBLOCK_ARMV7 def_bool n select ARCH_BOOTBLOCK_ARM +config ARCH_VERSTAGE_ARMV7 + def_bool n + select ARCH_VERSTAGE_ARM + config ARCH_ROMSTAGE_ARMV7 def_bool n select ARCH_ROMSTAGE_ARM diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index dc0e332..186dd44 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -3,6 +3,10 @@ config ARCH_BOOTBLOCK_ARM64 default n select ARCH_ARM64 +config ARCH_VERSTAGE_ARM64 + bool + default n + config ARCH_ROMSTAGE_ARM64 bool default n diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index fc2e668..5840e81 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -1,6 +1,9 @@ config ARCH_BOOTBLOCK_ARM_V8_64 def_bool n select ARCH_BOOTBLOCK_ARM64 +config ARCH_VERSTAGE_ARM_V8_64 + def_bool n + select ARCH_VERSTAGE_ARM64 config ARCH_ROMSTAGE_ARM_V8_64 def_bool n select ARCH_ROMSTAGE_ARM64 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 120203d..f2dc41e 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -3,6 +3,10 @@ config ARCH_BOOTBLOCK_RISCV default n select ARCH_RISCV +config ARCH_VERSTAGE_RISCV + bool + default n + config ARCH_ROMSTAGE_RISCV bool default n diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 56d8f88..edbc67a 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -3,6 +3,10 @@ config ARCH_BOOTBLOCK_X86_32 default n select ARCH_X86 +config ARCH_VERSTAGE_X86_32 + bool + default n + config ARCH_ROMSTAGE_X86_32 bool default n diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index b7b435f..58bf20d 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -7,6 +7,7 @@ if CPU_ALLWINNER_A10 config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index d539e19..2aeb8d7 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -28,6 +28,7 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY16_KB default n select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select TSC_SYNC_LFENCE diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index 88fdc8f..1e4f435 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -20,6 +20,7 @@ config CPU_AMD_GEODE_GX2 bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index b700e0c..e3e2d2e 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -1,6 +1,7 @@ config CPU_AMD_GEODE_LX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index 5e45b0d..cf5748c 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -1,6 +1,7 @@ config CPU_AMD_MODEL_10XXX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SSE diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index f577b55..bdcf5bb 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -1,6 +1,7 @@ config CPU_AMD_MODEL_FXX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select MMX diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 366beb4..88c4745 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -22,6 +22,7 @@ config CPU_AMD_PI default y if CPU_AMD_PI_00730F01 default n select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select TSC_SYNC_LFENCE diff --git a/src/cpu/armltd/cortex-a9/Kconfig b/src/cpu/armltd/cortex-a9/Kconfig index fb6cd0f..7ab3f55 100644 --- a/src/cpu/armltd/cortex-a9/Kconfig +++ b/src/cpu/armltd/cortex-a9/Kconfig @@ -1,6 +1,7 @@ config CPU_ARMLTD_CORTEX_A9 bool select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 default n diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index a7253e5..080bb64 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -20,6 +20,7 @@ config CPU_DMP_VORTEX86EX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index ec58428..5d90611 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_EP80579 bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SSE diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 9b0edfc..76b870e 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select PLATFORM_USES_FSP select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 2f891ad..7169c7e 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select PLATFORM_USES_FSP select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 0597363..e911b17 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -7,6 +7,7 @@ if CPU_INTEL_HASWELL config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 794c205..da8ddc5 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_1067X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 3b690cf..09acfd9 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_106CX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 8185d3a..4a85f09 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -6,6 +6,7 @@ if CPU_INTEL_MODEL_2065X config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index afd155a..490849b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -9,6 +9,7 @@ if CPU_INTEL_MODEL_206AX || CPU_INTEL_MODEL_306AX config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_65x/Kconfig b/src/cpu/intel/model_65x/Kconfig index 7af4ec9..4af7145 100644 --- a/src/cpu/intel/model_65x/Kconfig +++ b/src/cpu/intel/model_65x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_65X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_67x/Kconfig b/src/cpu/intel/model_67x/Kconfig index 1fd514b..2da200e 100644 --- a/src/cpu/intel/model_67x/Kconfig +++ b/src/cpu/intel/model_67x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_67X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_68x/Kconfig b/src/cpu/intel/model_68x/Kconfig index 8a8de0d..d77c9c9 100644 --- a/src/cpu/intel/model_68x/Kconfig +++ b/src/cpu/intel/model_68x/Kconfig @@ -21,6 +21,7 @@ config CPU_INTEL_MODEL_68X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_69x/Kconfig b/src/cpu/intel/model_69x/Kconfig index e1cd658..ff1d5e2 100644 --- a/src/cpu/intel/model_69x/Kconfig +++ b/src/cpu/intel/model_69x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_69X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_6bx/Kconfig b/src/cpu/intel/model_6bx/Kconfig index 46fbf1f..64f193a 100644 --- a/src/cpu/intel/model_6bx/Kconfig +++ b/src/cpu/intel/model_6bx/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_6BX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_6dx/Kconfig b/src/cpu/intel/model_6dx/Kconfig index b1a4c38..edbeac8 100644 --- a/src/cpu/intel/model_6dx/Kconfig +++ b/src/cpu/intel/model_6dx/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_6DX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 5c1b8de..08a5775 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_6EX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 0250397..baae196 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_6FX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_6xx/Kconfig b/src/cpu/intel/model_6xx/Kconfig index 546ac91..7cafb81 100644 --- a/src/cpu/intel/model_6xx/Kconfig +++ b/src/cpu/intel/model_6xx/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_6XX bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_f0x/Kconfig b/src/cpu/intel/model_f0x/Kconfig index bae4b0e..bfd8d3a 100644 --- a/src/cpu/intel/model_f0x/Kconfig +++ b/src/cpu/intel/model_f0x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_F0X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_f1x/Kconfig b/src/cpu/intel/model_f1x/Kconfig index 85bf5ad..cd4cdcf 100644 --- a/src/cpu/intel/model_f1x/Kconfig +++ b/src/cpu/intel/model_f1x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_F1X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 2871231..5ef1539 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_F2X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index cd3aa5b..7eaa820 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_F3X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/intel/model_f4x/Kconfig b/src/cpu/intel/model_f4x/Kconfig index cc23f04..4ef60b5 100644 --- a/src/cpu/intel/model_f4x/Kconfig +++ b/src/cpu/intel/model_f4x/Kconfig @@ -1,6 +1,7 @@ config CPU_INTEL_MODEL_F4X bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select SMP diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index ada6e23..46b0e00 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -20,5 +20,6 @@ config CPU_QEMU_X86 bool select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index eb60ad1..5ac629d 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -1,5 +1,6 @@ config CPU_TI_AM335X select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select HAVE_MONOTONIC_TIMER diff --git a/src/cpu/via/c3/Kconfig b/src/cpu/via/c3/Kconfig index 2e4d177..2a54603 100644 --- a/src/cpu/via/c3/Kconfig +++ b/src/cpu/via/c3/Kconfig @@ -6,6 +6,7 @@ if CPU_VIA_C3 config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig index 10b52bb..3507713 100644 --- a/src/cpu/via/c7/Kconfig +++ b/src/cpu/via/c7/Kconfig @@ -6,6 +6,7 @@ if CPU_VIA_C7 config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index 4242dd6..087f9f8 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -25,6 +25,7 @@ if CPU_VIA_NANO config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig index 9d00f5e..cf08ac8 100644 --- a/src/mainboard/bifferos/bifferboard/Kconfig +++ b/src/mainboard/bifferos/bifferboard/Kconfig @@ -3,6 +3,7 @@ if BOARD_BIFFEROS_BIFFERBOARD config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ROMCC diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index bcaa1ff..e7acbe3 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -8,6 +8,7 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index b93216e..1b073ea 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -8,6 +8,7 @@ if SOC_INTEL_BROADWELL config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ALT_CBFS_LOAD_PAYLOAD diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b61fac3..760bc72 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -28,6 +28,7 @@ if SOC_INTEL_FSP_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select DYNAMIC_CBMEM diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 195261e..f0cef82 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -2,6 +2,7 @@ config SOC_NVIDIA_TEGRA124 bool default n select ARCH_BOOTBLOCK_ARMV4 + select ARCH_VERSTAGE_ARMV4 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 792bb99..b306412 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -20,6 +20,8 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c endif +verstage-y += verstage.c + romstage-y += cbfs.c romstage-y += cbmem.c romstage-y += clock.c diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 2857a90..5f1e850 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -23,9 +23,9 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/nvidia/tegra/apbmisc.h> - #include "pinmux.h" #include "power.h" +#include "verstage.h" void main(void) { @@ -72,7 +72,10 @@ void main(void) power_enable_cpu_rail(); power_ungate_cpu(); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) + entry = (void *)verstage_vboot_main; + else + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); if (entry) clock_cpu0_config_and_reset(entry); diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c new file mode 100644 index 0000000..234a89d --- /dev/null +++ b/src/soc/nvidia/tegra124/verstage.c @@ -0,0 +1,9 @@ +#include "verstage.h" + +/** + * Stage entry point + */ +void vboot_main(void) +{ + for(;;); +} diff --git a/src/soc/nvidia/tegra124/verstage.h b/src/soc/nvidia/tegra124/verstage.h new file mode 100644 index 0000000..a0bac34 --- /dev/null +++ b/src/soc/nvidia/tegra124/verstage.h @@ -0,0 +1,2 @@ +void vboot_main(void); +void verstage_vboot_main(void); diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index ca7f5d4..395c329 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -2,6 +2,7 @@ config SOC_QC_IPQ806X bool default n select ARCH_BOOTBLOCK_ARMV4 + select ARCH_VERSTAGE_ARMV4 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select ARM_LPAE diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 8d7c867..476376b 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -1,5 +1,6 @@ config CPU_SAMSUNG_EXYNOS5250 select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select CPU_HAS_BOOTBLOCK_INIT diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 904091e..67926bc 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -1,5 +1,6 @@ config CPU_SAMSUNG_EXYNOS5420 select ARCH_BOOTBLOCK_ARMV7 + select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 select CPU_HAS_BOOTBLOCK_INIT diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index be4a675..e38ac29 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -1,6 +1,7 @@ config SOC_UCB_RISCV select ARCH_RISCV select ARCH_BOOTBLOCK_RISCV + select ARCH_VERSTAGE_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV select DYNAMIC_CBMEM diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 8156758..62d991b 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -85,6 +85,14 @@ config VBOOT_VERIFY_FIRMWARE Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the ramstage and boot loader. +config VBOOT2_VERIFY_FIRMWARE + bool "Firmware Verification with vboot2" + default n + depends on CHROMEOS + help + Enabling VBOOT2_VERIFY_FIRMWARE will use vboot2 to verify the romstage + and boot loader. + config EC_SOFTWARE_SYNC bool "Enable EC software sync" default n diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e17f50c..12d35b6 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -93,3 +93,12 @@ $(VB_LIB): fwlib endif + +ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y) +VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a +$(VERSTAGE_LIB): $$(verstage-objs) + @printf " AR $(subst $(obj)/,,$(@))\n" + $(AR_verstage) rc $@.tmp $(verstage-objs) + @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" + $(OBJCOPY_verstage) --prefix-symbols=verstage_ $@.tmp $@ +endif diff --git a/toolchain.inc b/toolchain.inc index 73f0832..f8c7ea4 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -51,7 +51,7 @@ HOSTCXX:=CCC_CXX="$(HOSTCXX)" $(CXX) ROMCC=CCC_CC="$(ROMCC_BIN)" $(CC) endif -COREBOOT_STANDARD_STAGES := bootblock romstage ramstage +COREBOOT_STANDARD_STAGES := bootblock verstage romstage ramstage ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86

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coreboot-gerrit January 2015