coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

1 participants
1236 discussions

New patch to review for coreboot: 3b0a7a5 Fix multiprocessor support not being compiled in when selected via Kconfig on AMD systems
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8268 -gerrit commit 3b0a7a5a2e1d83d95d3b179becca77ff124df5f1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:28:13 2015 -0600 Fix multiprocessor support not being compiled in when selected via Kconfig on AMD systems Change-Id: I44c22f2e11096247285b0fb469ccf51963eace2b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/ht_wrapper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 5742494..6a01e14 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -28,7 +29,7 @@ */ /* Single CPU system? */ -#if CONFIG_MAX_PHYSICAL_CPUS +#if (CONFIG_MAX_PHYSICAL_CPUS == 1) #define HT_BUILD_NC_ONLY 1 #endif

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New patch to review for coreboot: 02600b7 Fix uninitialized variable when manual non-coherent BUID selection is used
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8267 -gerrit commit 02600b7f957c0004e4b5a84234754c2309865d11 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:27:26 2015 -0600 Fix uninitialized variable when manual non-coherent BUID selection is used Change-Id: Id19745b29486aef5297fdbb3324ae36bf9b8f466 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdht/h3finit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index ff57033..88d5b6a 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -963,6 +964,7 @@ static void processLink(u8 node, u8 link, sMainData *pDat) && pDat->HtBlock->AMD_CB_ManualBUIDSwapList(node, link, &pSwapPtr)) { /* Manual non-coherent BUID assignment */ + currentBUID = 1; /* Assign BUID's per manual override */ while (*pSwapPtr != 0xFF)

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New patch to review for coreboot: cc73587 Enhance resource debugging when enabled
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8266 -gerrit commit cc73587c1a49734766a9f703939785c3486c0fee Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:26:31 2015 -0600 Enhance resource debugging when enabled Change-Id: Ie39652bded9a42d1d816ca5198db59a83e5c083a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/setup_resource_map.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index ca7f964..9d4088b 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -94,9 +96,15 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset dev = (register_values[i+1] & ~0xfff) + offset_pci_dev; where = register_values[i+1] & 0xfff; reg = pci_read_config32(dev, where); +#if RES_DEBUG + printk(BIOS_DEBUG, "WAS: %08x\n", reg); +#endif reg &= register_values[i+2]; reg |= register_values[i+3]; pci_write_config32(dev, where, reg); +#if RES_DEBUG + printk(BIOS_DEBUG, "NOW: %08x\n", reg); +#endif } break; case RES_PORT_IO_8: // io 8 @@ -105,9 +113,15 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset u32 reg; where = register_values[i+1] + offset_io_base; reg = inb(where); +#if RES_DEBUG + printk(BIOS_DEBUG, "WAS: %08x\n", reg); +#endif reg &= register_values[i+2]; reg |= register_values[i+3]; outb(reg, where); +#if RES_DEBUG + printk(BIOS_DEBUG, "NOW: %08x\n", reg); +#endif } break; case RES_PORT_IO_32: //io32 @@ -116,14 +130,19 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset u32 reg; where = register_values[i+1] + offset_io_base; reg = inl(where); +#if RES_DEBUG + printk(BIOS_DEBUG, "WAS: %08x\n", reg); +#endif reg &= register_values[i+2]; reg |= register_values[i+3]; outl(reg, where); +#if RES_DEBUG + printk(BIOS_DEBUG, "NOW: %08x\n", reg); +#endif } break; } // switch - } #if RES_DEBUG

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New patch to review for coreboot: 7488905 Fix FTBFS when CONFIG_PCI_64BIT_PREF_MEM is set
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8265 -gerrit commit 74889054eb6cd51175ea13e111ecb8988f590404 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:26:03 2015 -0600 Fix FTBFS when CONFIG_PCI_64BIT_PREF_MEM is set Change-Id: I750fc3a135f7634ad16c0f6a1a5bdb16ac702977 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a8a8155..51cfee7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -858,7 +859,7 @@ static void setup_uma_memory(void) static void amdfam10_domain_set_resources(device_t dev) { #if CONFIG_PCI_64BIT_PREF_MEM - struct resource *io, *mem1, *mem2; + struct resource *mem1, *mem2; struct resource *res; #endif unsigned long mmio_basek; @@ -914,7 +915,7 @@ static void amdfam10_domain_set_resources(device_t dev) mem2->base, mem2->limit, mem2->size, mem2->align); } - for(res = &dev->resource_list; res; res = res->next) + for(res = dev->resource_list; res; res = res->next) { res->flags |= IORESOURCE_ASSIGNED; res->flags |= IORESOURCE_STORED;

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New patch to review for coreboot: 44c04b5 Fix IASL warnings in AMD Family 10h ASL utility code
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8264 -gerrit commit 44c04b5928729068e74148a6569435d28f1fb8cb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:25:15 2015 -0600 Fix IASL warnings in AMD Family 10h ASL utility code Change-Id: Ia98088bea7e3e21c33252c98a675799d52edb809 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/amdfam10_util.asl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.asl b/src/northbridge/amd/amdfam10/amdfam10_util.asl index 8e02510..a0f4170 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.asl +++ b/src/northbridge/amd/amdfam10/amdfam10_util.asl @@ -1,6 +1,7 @@ // // This file is part of the coreboot project. // +// Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering // Copyright (C) 2007 Advanced Micro Devices, Inc. // // This program is free software; you can redistribute it and/or modify @@ -122,7 +123,7 @@ Scope (\_SB) Return (0x00) } - Method (GWBN, 2, NotSerialized) + Method (GWBN, 2, Serialized) { Name (BUF0, ResourceTemplate () { @@ -161,7 +162,7 @@ Scope (\_SB) Return (RTAG (BUF0)) } - Method (GMEM, 2, NotSerialized) + Method (GMEM, 2, Serialized) { Name (BUF0, ResourceTemplate () { @@ -222,7 +223,7 @@ Scope (\_SB) Return (Local3) } - Method (GIOR, 2, NotSerialized) + Method (GIOR, 2, Serialized) { Name (BUF0, ResourceTemplate () {

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New patch to review for coreboot: eb8e178 Add ability to configure background scrubbing rate and ECC redirection at compile time on AMD systems
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8263 -gerrit commit eb8e178bc5eb6e91bf29ad3920abec3decb43335 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:24:30 2015 -0600 Add ability to configure background scrubbing rate and ECC redirection at compile time on AMD systems Change-Id: Icbbba0037c19bdc279813e51c72f54a10e4dc55a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/Kconfig | 36 ++++++++++++++++++++++++++++ src/northbridge/amd/amdmct/wrappers/mcti_d.c | 8 +++++++ 2 files changed, 44 insertions(+) diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig index e9b3796..34388b2 100644 --- a/src/northbridge/amd/Kconfig +++ b/src/northbridge/amd/Kconfig @@ -98,4 +98,40 @@ config LIMIT_HT_UP_WIDTH_16 bool "16 bits" endchoice +config AMDMCT_ENABLE_ECC_REDIR + bool + default n + +config AMDMCT_BACKGROUND_SCRUB_RATE + hex + default 0x00 + help + This option sets the background ECC memory scub rate + + Permissible values are: + + 0x00; Disabled + 0x01; 40ns + 0x02; 80ns + 0x03; 160ns + 0x04; 320ns + 0x05; 640ns + 0x06; 1.28us + 0x07; 2.56us + 0x08; 5.12us + 0x09; 10.2us + 0x0a; 20.5us + 0x0b; 41us + 0x0c; 81.9us + 0x0d; 163.8us + 0x0e; 327.7us + 0x0f; 655.4us + 0x10; 1.31ms + 0x11; 2.62ms + 0x12; 5.24ms + 0x13; 10.49ms + 0x14; 20.97sms + 0x15; 42ms + 0x16; 84ms + endmenu diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index e127322..46873e5 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -167,10 +167,17 @@ static u16 mctGet_NVbits(u8 index) #endif break; case NV_ECCRedir: +#ifdef CONFIG_AMDMCT_ENABLE_ECC_REDIR + val = CONFIG_AMDMCT_ENABLE_ECC_REDIR; +#else val = 0; /* Disable */ //val = 1; /* Enable */ +#endif break; case NV_DramBKScrub: +#ifdef CONFIG_AMDMCT_BACKGROUND_SCRUB_RATE + val = CONFIG_AMDMCT_BACKGROUND_SCRUB_RATE; +#else val = 0x00; /* Disabled */ //val = 0x01; /* 40ns */ //val = 0x02; /* 80ns */ @@ -194,6 +201,7 @@ static u16 mctGet_NVbits(u8 index) //val = 0x14; /* 20.97sms */ //val = 0x15; /* 42ms */ //val = 0x16; /* 84ms */ +#endif break; case NV_L2BKScrub: val = 0; /* Disabled - See L2Scrub in BKDG */

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New patch to review for coreboot: 723406c Fix typo in comment
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8262 -gerrit commit 723406ca7d7305a25fc3585e7762c67a60659a0c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:22:56 2015 -0600 Fix typo in comment Change-Id: Ib63a8b6e7f4663926104426992f6dea9ee3510b0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/device/hypertransport.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index d9ab486..88a5fc6 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -512,7 +512,7 @@ unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS); /* - * If the devices has a unitid set and is at devfn 0 we are + * If the device has a unitid set and is at devfn 0 we are * done. This can happen with shadow hypertransport devices, * or if we have reached the bottom of a HT device chain. */

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New patch to review for coreboot: 5ca5f55 Fix incorrect PCI register space location causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems Tested with 8GB physical RAM
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8261 -gerrit commit 5ca5f55b182fdbb08bda646033c2fb80ed67b69d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:20:56 2015 -0600 Fix incorrect PCI register space location causing corruption with more than ~3.5GB physical RAM on AMD Family 10h systems Tested with 8GB physical RAM Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/device/device.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 00e323a..a251568 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -13,6 +13,7 @@ * (Written by Yinghai Lu <yhlu(a)tyan.com> for Tyan) * Copyright (C) 2005-2006 Stefan Reinauer <stepan(a)openbios.org> * Copyright (C) 2009 Myles Watson <mylesgw(a)gmail.com> + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering */ /* @@ -669,11 +670,14 @@ static void constrain_resources(struct device *dev, struct constraints* limits) * signed so that "negative" amounts of space are handled * correctly. */ + if ((signed long long)(lim->limit - (res->base + res->size -1)) - > (signed long long)(res->base - lim->base)) + > (signed long long)(res->base - lim->base)) { lim->base = res->base + res->size; - else + } + else { lim->limit = res->base -1; + } } /* Descend into every enabled child and look for fixed resources. */ @@ -712,6 +716,20 @@ static void avoid_fixed_resources(struct device *dev) if ((res->flags & MEM_MASK) == MEM_TYPE && (res->limit < limits.mem.limit)) limits.mem.limit = res->limit; + // Shrink possible PCI address space to the resource specified value + // Without this the PCI address space attempts to reserve roughly all 32-bit addressable RAM, + // leading to allocation below the AMD fixed resource window instead of above it. When allocated + // below the fixed resource window it is not protected by the e820 map and the PCI configuration + // is overwritten, causing all PCI devices to become unusable! + // This bug is only exposed when the top of system RAM touches the bottom of the fixed resource window. + // If less than ~3.5GB of memory is installed there is a gap between system RAM and the fixed resource window + // which protects the incorrectly allocated PCI configuration registers and hides this bug. + // On non-AMD systems this may not matter as much, but the code below is generic and should not harm other systems. + if ((res->flags & MEM_MASK) == MEM_TYPE && + (res->size < (limits.mem.limit - limits.mem.base + 1))) { + limits.mem.base = (limits.mem.limit - res->size + 1); + limits.mem.size = res->size; + } if ((res->flags & IO_MASK) == IO_TYPE && (res->limit < limits.io.limit)) limits.io.limit = res->limit;

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New patch to review for coreboot: 6699257 Fix reset during AMD Family 10h FID/VID setup due to invalid MSR access
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8260 -gerrit commit 66992572d5b64e871172d6499201f8a40482afe6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:19:44 2015 -0600 Fix reset during AMD Family 10h FID/VID setup due to invalid MSR access Change-Id: I943748a9a0389a75102675e1722ab3a7d1ce6a49 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_10xxx/fidvid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index d3c67a9..ad31b8d 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -322,7 +323,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* Get PSmax's index */ msr = rdmsr(0xC0010061); - bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3); + bValue = (u8) (((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3) - 1); /* Get PSmax's VID */ msr = rdmsr(0xC0010064 + bValue);

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New patch to review for coreboot: c9b0122 Fix corrupt SSDT table on multiprocessor AMD Family 10h systems
by Timothy Pearson 24 Jan '15

24 Jan '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8259 -gerrit commit c9b012220dfe72cf1beb0dbd16ac339d13536dbb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 23 20:18:56 2015 -0600 Fix corrupt SSDT table on multiprocessor AMD Family 10h systems Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Change-Id: I3175c8b29e94a27a2db6b11f8fc9e1d91bde11f9 --- src/arch/x86/boot/acpi.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 621df2f..6da6f31 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -4,6 +4,7 @@ * coreboot ACPI Table support * written by Stefan Reinauer <stepan(a)openbios.org> * + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2004 SUSE LINUX AG * Copyright (C) 2005-2009 coresystems GmbH * @@ -278,10 +279,36 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id) acpigen_set_current((char *) current); { #if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES) +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + char amd_cpu_ssdt_generated = 0; +#endif struct device *dev; for (dev = all_devices; dev; dev = dev->next) if (dev->ops && dev->ops->acpi_fill_ssdt_generator) { +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) + // HACK + // If more than one physical CPU is installed, northbridge_acpi_write_vars() is called more than once and the resultant SSDT table is corrupted (duplicated entries) + // This prevents Linux from booting, with log messages like these: + // ACPI Error: [BUSN] Namespace lookup failure, AE_ALREADY_EXISTS (20131115/dswload-353) + // ACPI Exception: AE_ALREADY_EXISTS, During name lookup/catalog (20131115/psobject-222) + // followed by a slew of ACPI method failures and a hang when the invalid PCI resource entries are used + // + // The code in northbridge_acpi_write_vars needs to be reworked to function correctly when called once per device + // The commit that broke multiple physical CPUs is GIT hash 2a19fb1d76c42cb516a4ab6f253de8c65d8cc3ad + if ((dev->vendor == 0x1022) && (dev->device == 0x1200)) { + // AMD K10 CPU... + if (!amd_cpu_ssdt_generated) { + dev->ops->acpi_fill_ssdt_generator(); + amd_cpu_ssdt_generated = 1; + } + } + else { + // Some other device, proceed normally + dev->ops->acpi_fill_ssdt_generator(); + } +#else dev->ops->acpi_fill_ssdt_generator(); +#endif } current = (unsigned long) acpigen_get_current(); #else

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coreboot-gerrit January 2015