the following patch was just integrated into master:
commit 8f993784ef71f451995dd67fc709b88399c8a7e9
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Sep 9 14:37:03 2013 -0700
ARMv7/Exynos: Fix memory location assumptions
This patch cleans out a lot of unused variables in the
ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE
which is similar to CONFIG_RAMBASE on x86.
This gets rid of the hard coded assumption that on ARM
coreboot is always executed at the lowest DRAM address.
But in fact, this might not be true because we might want
coreboot to live at the end of RAM, or in SRAM
Change-Id: I03e992645f9eb730e39a521aa21f702959311f74
Signed-off-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/168645
Reviewed-by: David Hendrix <dhendrix(a)chromium.org>
Tested-by: David Hendrix <dhendrix(a)chromium.org>
(cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6634 for details.
-gerrit
the following patch was just integrated into master:
commit fa938c7508627c0dfcf03960957ef8631fc53f02
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Aug 29 14:17:36 2013 -0700
exynos5: Refactor crazy old U-Boot base address macros away
All this samsung_get_base_address_of_device_with_a_really_long_name()
boilerplate makes my eyes bleed... I think there are so much cleaner
ways to do this. Unfortunately changing this ends up touching nearly
every Exynos5 file, but I hope you agree that it's worth it (and the
sooner we get it over with, the better... I can't bring myself to make
another device fit into that ugly scheme).
This also removes the redundant EXYNOS5 base address definitions from
the 5420 directory when there are EXYNOS5420 ones, to avoid complete
confusion. The new scheme tries to use EXYNOS5 for base addresses and
exynos5 for types that are common between the two processors, and
EXYNOS5420/exynos5420 for things that have changes (although I probably
didn't catch all differences).
Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167579
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: ron minnich <rminnich(a)chromium.org>
(cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/6632
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See http://review.coreboot.org/6632 for details.
-gerrit
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6659
-gerrit
commit fff92ac5d8649136e60b925fb3bd9a67fd25108b
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Oct 6 06:13:24 2013 -0700
tegra: Change how tegra124 and tegra include files from each other.
A problem with including the tegra124 directory directly in the include path
is that it makes all headers in that directory first level headers available
everywhere including places that have nothing to do with the SOC, even headers
which were only intended for local use by tegra124 code. This change modifies
things a bit to be more like the way the arch headers are chosen. In the
tegra124 directory, there's an include directory which has an soc subdirectory
in it. That include directory is added to the include path, making it possible
to have headers private to the tegra124. When files specific to whatever tegra
is being built for are needed, you can include <soc/foo.h> and get the version
specific to that particular soc.
Also, the soc.h header file was overhauled to use enums instead of defines, to
consistently name things as far as their prefix (the less cryptic TEGRA instead
of NV_PA) and suffixes like "BASE", and to get rid of values which were
specific to U-Boot which we don't need. Since the only thing in the file were
address constants, I also renamed the file addressmap.h. It would be included
as:
<soc/addressmap.h>
which I think is easy to remember, does what you'd think it does from the
name, and won't conflict with other header files just minding their own
business in some other directory.
Change-Id: I6a1be1ba28417b7103ad8584e6ec5024a7ff4e55
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/172080
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 2c554f58f9ee18e151e824f01c03eb3f0e907858)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/Makefile.inc | 2 +-
src/soc/nvidia/tegra124/clock.c | 9 ++--
src/soc/nvidia/tegra124/include/soc/addressmap.h | 60 ++++++++++++++++++++++
src/soc/nvidia/tegra124/soc.h | 64 ------------------------
4 files changed, 66 insertions(+), 69 deletions(-)
diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index 0037a69..b8541fb 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -13,7 +13,7 @@ ramstage-y += cbfs.c
ramstage-y += monotonic_timer.c
ramstage-y += timer.c
-INCLUDES += -Isrc/soc/nvidia/tegra124 -Isrc/soc/nvidia
+INCLUDES += -Isrc/soc/nvidia/tegra124/include/
# We want to grab the bootblock right before it goes into the image and wrap
# it inside a BCT, but ideally we would do that without making special, one
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index 691a6ee..af01b56 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -16,11 +16,12 @@
#include <delay.h>
#include <arch/io.h>
-#include <soc.h>
-#include <clk_rst.h>
-#include <clock.h>
+#include <soc/addressmap.h>
-static struct clk_rst_ctlr *clk_rst = (void *)NV_PA_CLK_RST_BASE;
+#include "clk_rst.h"
+#include "clock.h"
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
/*
* On poweron, AVP clock source (also called system clock) is set to PLLP_out0
* with frequency set at 1MHz. Before initializing PLLP, we need to move the
diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h
new file mode 100644
index 0000000..edacf15
--- /dev/null
+++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright 2013 Google Inc.
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__
+#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__
+
+enum {
+ TEGRA_SRAM_BASE = 0x40000000,
+ TEGRA_SRAM_SIZE = 0x20000
+};
+
+enum {
+ TEGRA_ARM_PERIPHBASE = 0x50040000,
+ TEGRA_PG_UP_BASE = 0x60000000,
+ TEGRA_TMRUS_BASE = 0x60005010,
+ TEGRA_CLK_RST_BASE = 0x60006000,
+ TEGRA_FLOW_BASE = 0x60007000,
+ TEGRA_GPIO_BASE = 0x6000D000,
+ TEGRA_EVP_BASE = 0x6000F000,
+ TEGRA_APB_MISC_BASE = 0x70000000,
+ TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800,
+ TEGRA_APB_UARTA_BASE = TEGRA_APB_MISC_BASE + 0x6000,
+ TEGRA_APB_UARTB_BASE = TEGRA_APB_MISC_BASE + 0x6040,
+ TEGRA_APB_UARTC_BASE = TEGRA_APB_MISC_BASE + 0x6200,
+ TEGRA_APB_UARTD_BASE = TEGRA_APB_MISC_BASE + 0x6300,
+ TEGRA_APB_UARTE_BASE = TEGRA_APB_MISC_BASE + 0x6400,
+ TEGRA_NAND_BASE = TEGRA_APB_MISC_BASE + 0x8000,
+ TEGRA_SPI_BASE = TEGRA_APB_MISC_BASE + 0xC380,
+ TEGRA_SLINK1_BASE = TEGRA_APB_MISC_BASE + 0xD400,
+ TEGRA_SLINK2_BASE = TEGRA_APB_MISC_BASE + 0xD600,
+ TEGRA_SLINK3_BASE = TEGRA_APB_MISC_BASE + 0xD800,
+ TEGRA_SLINK4_BASE = TEGRA_APB_MISC_BASE + 0xDA00,
+ TEGRA_SLINK5_BASE = TEGRA_APB_MISC_BASE + 0xDC00,
+ TEGRA_SLINK6_BASE = TEGRA_APB_MISC_BASE + 0xDE00,
+ TEGRA_DVC_BASE = TEGRA_APB_MISC_BASE + 0xD000,
+ TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400,
+ TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400,
+ TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800,
+ TEGRA_CSITE_BASE = 0x70040000,
+ TEGRA_USB_ADDR_MASK = 0xFFFFC000,
+};
+
+#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */
diff --git a/src/soc/nvidia/tegra124/soc.h b/src/soc/nvidia/tegra124/soc.h
deleted file mode 100644
index 7a164b0..0000000
--- a/src/soc/nvidia/tegra124/soc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
- * Copyright 2013 Google Inc.
- *
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _TEGRA124_SOC_H
-
-/* AP base physical address of internal SRAM */
-#define NV_PA_BASE_SRAM 0x40000000
-#define NV_PA_BASE_SRAM_SIZE 0x20000
-
-/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
-#define NV_WB_RUN_ADDRESS 0x40020000
-
-#define NV_PA_ARM_PERIPHBASE 0x50040000
-#define NV_PA_PG_UP_BASE 0x60000000
-#define NV_PA_TMRUS_BASE 0x60005010
-#define NV_PA_CLK_RST_BASE 0x60006000
-#define NV_PA_FLOW_BASE 0x60007000
-#define NV_PA_GPIO_BASE 0x6000D000
-#define NV_PA_EVP_BASE 0x6000F000
-#define NV_PA_APB_MISC_BASE 0x70000000
-#define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
-#define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
-#define NV_PA_APB_UARTB_BASE (NV_PA_APB_MISC_BASE + 0x6040)
-#define NV_PA_APB_UARTC_BASE (NV_PA_APB_MISC_BASE + 0x6200)
-#define NV_PA_APB_UARTD_BASE (NV_PA_APB_MISC_BASE + 0x6300)
-#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
-#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
-#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
-#define NV_PA_SLINK1_BASE (NV_PA_APB_MISC_BASE + 0xD400)
-#define NV_PA_SLINK2_BASE (NV_PA_APB_MISC_BASE + 0xD600)
-#define NV_PA_SLINK3_BASE (NV_PA_APB_MISC_BASE + 0xD800)
-#define NV_PA_SLINK4_BASE (NV_PA_APB_MISC_BASE + 0xDA00)
-#define NV_PA_SLINK5_BASE (NV_PA_APB_MISC_BASE + 0xDC00)
-#define NV_PA_SLINK6_BASE (NV_PA_APB_MISC_BASE + 0xDE00)
-#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
-#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
-#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
-#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
-#define NV_PA_CSITE_BASE 0x70040000
-#define TEGRA_USB_ADDR_MASK 0xFFFFC000
-
-#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
-
-#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
-#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
-
-#endif /* _TEGRA124_SOC_H_ */
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6658
-gerrit
commit a54acb166905b36c93428f1438626808df70a120
Author: Isaac Christensen <isaac.christensen(a)se-eng.com>
Date: Wed Aug 13 17:29:44 2014 -0600
tegra124: fix Kconfig ARCH settings
The initial commit for tegra124 was not updated for the new ARCH settings.
Change-Id: I147bdf289e91031bd0c0a61e6da43e9c1a438f84
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/soc/nvidia/tegra124/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig
index 8a0dee4..17e02e7 100644
--- a/src/soc/nvidia/tegra124/Kconfig
+++ b/src/soc/nvidia/tegra124/Kconfig
@@ -1,5 +1,7 @@
config SOC_NVIDIA_TEGRA124
- depends on ARCH_ARMV7
+ select ARCH_BOOTBLOCK_ARMV7
+ select ARCH_ROMSTAGE_ARMV7
+ select ARCH_RAMSTAGE_ARMV7
bool
default n
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6657
-gerrit
commit d29a34437638f956b205e19262fc96dd46f02e39
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Thu Sep 19 16:45:22 2013 -0700
Peppy graphics
Peppy had some issues with FUI. We decided it was time to create
peppy-specific gma.c and i915io.c files. Using yabel and the i915tool,
we generated a replay attack, then interpolated against the slippy
i915io.c to get something working.
Also, in preparation for moving code out of the mainboard gma.c to
generic driver code, we got rid of some hardcodes in the mainboard
gma.c that have no business being there. The worst were the
computation of gmch_[m,n] and it turns out that we had some
long-standing bugs related to confusion about 'bpp'. I've killed the
word bpp everywhere I could because there are at least 3 things that
correspond to bpp. We now have framebuffer, pipe, and panel bpp. The
names are long because I want to avoid all the mistakes we've all been
making in the last year :-) Sadly, that means a lot of changes not just
peppy-related, but they are simple and in a good cause.
The test pattern generation is driven by a global variable in
mainboard/peppy/gma.c. I've found in the past that it's very useful
to have a function like this available, as one can activate it while
using a jtag debugger: halt at the right place in ramstage, set the
variable to 1, continue. It's not enough code to worry about always
including.
The last hard-codes for M and N registers are gone, and the function
to set from generic intel_dp.c code works. To avoid screen trash on a
dev mode boot, which we liked but nobody else did :-), we now take the
time to put a pleasing background color that sort of doubles as a
power LED.
Rough timing is ramstage start is at 2.2, and dev setup is done at
3.3. These new platforms are depressingly slow to boot. Rom init alone
is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash
prompt. These CPUs are at least 10x faster and take much longer to get going.
Future work, once we get this through, is to move more functions to the
intel driver, and combine the mainboard i915io.c into the mainboard gma.c.
That separation only existed because i915io.c was generated by a tool, and it
had lots of ugliness. Most ugliness is gone.
Old-Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/170013
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh(a)gmail.com>
(cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d)
snow: Fix a typo in devicetree.cb that was breaking the snow build.
A typo in a recent change broke the snow build.
Old-Change-Id: I93074e68eb3d21510d974fd8e9c63b3947285afd
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/171014
Reviewed-by: Ronald Minnich <rminnich(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 154876c126a6690930141df178485658533096d2)
Squashed a fix into the initial patch.
Change-Id: I2f4342c610d87335411da1d6d405171dc80c1f14
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5250/chip.h | 2 +-
src/cpu/samsung/exynos5420/chip.h | 2 +-
src/drivers/intel/gma/i915.h | 3 +-
src/drivers/intel/gma/intel_ddi.c | 4 +-
src/drivers/intel/gma/intel_dp.c | 68 ++---
src/include/edid.h | 22 +-
src/include/vbe.h | 2 +-
src/lib/edid.c | 23 +-
src/mainboard/google/link/i915.c | 2 +-
src/mainboard/google/peppy/Kconfig | 3 +
src/mainboard/google/peppy/Makefile.inc | 2 +
src/mainboard/google/peppy/gma.c | 436 ++++++++++++++++++++++++++++++++
src/mainboard/google/peppy/i915io.c | 144 +++++++++++
src/mainboard/google/peppy/mainboard.h | 25 ++
src/mainboard/google/pit/devicetree.cb | 2 +-
src/mainboard/google/pit/mainboard.c | 2 +-
src/mainboard/google/slippy/gma.c | 6 +-
src/mainboard/google/snow/devicetree.cb | 2 +-
src/mainboard/google/snow/mainboard.c | 2 +-
src/northbridge/intel/haswell/gma.c | 15 +-
20 files changed, 699 insertions(+), 68 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h
index f244379..c2e7fb5 100644
--- a/src/cpu/samsung/exynos5250/chip.h
+++ b/src/cpu/samsung/exynos5250/chip.h
@@ -34,7 +34,7 @@ struct cpu_samsung_exynos5250_config {
int xres;
int yres;
- int bpp;
+ int framebuffer_bits_per_pixel;
int usb_vbus_gpio;
int usb_hsic_gpio;
diff --git a/src/cpu/samsung/exynos5420/chip.h b/src/cpu/samsung/exynos5420/chip.h
index f2c710d..220a315 100644
--- a/src/cpu/samsung/exynos5420/chip.h
+++ b/src/cpu/samsung/exynos5420/chip.h
@@ -34,7 +34,7 @@ struct cpu_samsung_exynos5420_config {
int xres;
int yres;
- int bpp;
+ int framebuffer_bits_per_pixel;
int usb_vbus_gpio;
int usb_hsic_gpio;
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 72301e1..e8940a3 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -139,7 +139,7 @@ struct intel_dp {
int port;
int pipe;
int plane;
- int bpp;
+ int pipe_bits_per_pixel;
/* i2c on aux is ... interesting.
* Before you do an i2c cycle, you need to set the address.
* This requires we remember it from one moment to the next.
@@ -272,6 +272,7 @@ int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
void intel_prepare_ddi(void);
void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp);
+int gtt_poll(u32 reg, u32 mask, u32 value);
void gtt_write(u32 reg, u32 data);
u32 gtt_read(u32 reg);
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index 2b27f6e..e51fb9c 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -253,7 +253,7 @@ void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
{
u32 val = TRANS_MSA_SYNC_CLK;
- switch (intel_dp->bpp) {
+ switch (intel_dp->pipe_bits_per_pixel) {
case 18:
val |= TRANS_MSA_6_BPC;
break;
@@ -267,7 +267,7 @@ void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
val |= TRANS_MSA_12_BPC;
break;
default:
- printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->bpp);
+ printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->pipe_bits_per_pixel);
}
gtt_write(TRANS_MSA_MISC(intel_dp->transcoder),val);
}
diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c
index 833a4d6..55e57e6 100644
--- a/src/drivers/intel/gma/intel_dp.c
+++ b/src/drivers/intel/gma/intel_dp.c
@@ -260,7 +260,7 @@ int intel_dp_set_bw(struct intel_dp *intel_dp)
int intel_dp_set_lane_count(struct intel_dp *intel_dp)
{
- printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
+ printk(BIOS_SPEW, "DP_LANE_COUNT_SET %d ", intel_dp->lane_count);
return intel_dp_aux_native_write_1(intel_dp,
DP_LANE_COUNT_SET,
intel_dp->lane_count);
@@ -471,7 +471,20 @@ unsigned int roundup_power_of_two(unsigned int n)
static void compute_m_n(unsigned int m, unsigned int n,
unsigned int *ret_m, unsigned int *ret_n)
{
- *ret_n = MIN(roundup_power_of_two(n), DATA_LINK_N_MAX);
+ /* We noticed in the IO operations that
+ * the VBIOS was setting N to DATA_LINK_N_MAX.
+ * This makes sense, actually: the bigger N is, i.e.
+ * the bigger the denominator is, the bigger
+ * the numerator can be, and the more
+ * bits of numerator you get, the better the result.
+ * So, first pick the max of the two powers of two.
+ * And, in the (unlikely) event that you end up with
+ * something bigger than DATA_LINK_N_MAX, catch that
+ * case with a MIN. Note the second case is unlikely,
+ * but we are best off being careful.
+ */
+ *ret_n = MAX(roundup_power_of_two(n), DATA_LINK_N_MAX);
+ *ret_n = MIN(*ret_n, DATA_LINK_N_MAX);
*ret_m = ( (unsigned long long)m * *ret_n) / n;
intel_reduce_m_n_ratio(ret_m, ret_n);
}
@@ -483,7 +496,6 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
struct intel_dp_m_n *m_n)
{
m_n->tu = 64;
-
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
&m_n->gmch_m, &m_n->gmch_n);
@@ -492,35 +504,6 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
&m_n->link_m, &m_n->link_n);
}
-/* not sure. */
-void intel_dp_set_m_n(struct intel_dp *intel_dp);
-
-void
-intel_dp_set_m_n(struct intel_dp *intel_dp)
-{
- int lane_count;
- struct intel_dp_m_n m_n;
- int pipe = intel_dp->pipe;
-
- lane_count = intel_dp->lane_count;
-
- /*
- * Compute the GMCH and Link ratios. The '3' here is
- * the number of bytes_per_pixel post-LUT, which we always
- * set up for 8-bits of R/G/B, or 3 bytes total.
- */
- intel_dp_compute_m_n(intel_dp->bpp, lane_count,
- intel_dp->clock, intel_dp->clock, &m_n);
-
- {
- gtt_write(TRANSDATA_M1(pipe),
- ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |m_n.gmch_m);
- gtt_write(TRANSDATA_N1(pipe),m_n.gmch_n);
- gtt_write(TRANSDPLINK_M1(pipe),m_n.link_m);
- gtt_write(TRANSDPLINK_N1(pipe),m_n.link_n);
- }
-}
-
static void ironlake_edp_pll_off(void);
void
@@ -1791,17 +1774,13 @@ intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread)
return 1;
}
-void intel_dp_set_m_n_regs(struct intel_dp *intel_dp)
+void intel_dp_set_m_n_regs(struct intel_dp *dp)
{
- gtt_write(PIPE_DATA_M1(intel_dp->transcoder),0x7e4a0000);
- /* gtt_write(0x6f034,0x00800000); */
- /* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important.
- However, with our formula we always see values 0x7e43yyyy (1366 panel) and
- 0x7e42yyy (1280 panel) */
- /* gtt_write(PIPE_DATA_M1(intel_dp->transcoder),TU_SIZE(intel_dp->m_n.tu) | intel_dp->m_n.gmch_m); */
- gtt_write(PIPE_DATA_N1(intel_dp->transcoder),intel_dp->m_n.gmch_n);
- gtt_write(PIPE_LINK_M1(intel_dp->transcoder),intel_dp->m_n.link_m);
- gtt_write(PIPE_LINK_N1(intel_dp->transcoder),intel_dp->m_n.link_n);
+ gtt_write(PIPE_DATA_M1(dp->transcoder),
+ TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+ gtt_write(PIPE_DATA_N1(dp->transcoder),dp->m_n.gmch_n);
+ gtt_write(PIPE_LINK_M1(dp->transcoder),dp->m_n.link_m);
+ gtt_write(PIPE_LINK_N1(dp->transcoder),dp->m_n.link_n);
}
void intel_dp_set_resolution(struct intel_dp *intel_dp)
@@ -1826,10 +1805,13 @@ int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
int intel_dp_get_lane_count(struct intel_dp *intel_dp,
u8 *recv)
{
- return intel_dp_aux_native_read_retry(intel_dp,
+ int val = intel_dp_aux_native_read_retry(intel_dp,
DP_LANE_COUNT_SET,
recv,
0);
+ *recv &= DP_LANE_COUNT_MASK;
+ printk(BIOS_SPEW, "Lane count %s:%d\n", val < 0 ? "fail" : "ok", *recv);
+ return val;
}
int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
diff --git a/src/include/edid.h b/src/include/edid.h
index 4a2f138..867a82f 100644
--- a/src/include/edid.h
+++ b/src/include/edid.h
@@ -35,7 +35,27 @@ struct edid {
unsigned int version[2];
unsigned int nonconformant;
unsigned int type;
- unsigned int bpp;
+ /* These next three things used to all be called bpp.
+ * Merriment ensued. The identifier
+ * 'bpp' is herewith banished from our
+ * Kingdom.
+ */
+ /* How many bits in the framebuffer per pixel.
+ * Under all reasonable circumstances, it's 32.
+ */
+ unsigned int framebuffer_bits_per_pixel;
+ /* On the panel, how many bits per color?
+ * In almost all cases, it's 6 or 8.
+ * The standard allows for much more!
+ */
+ unsigned int panel_bits_per_color;
+ /* On the panel, how many bits per pixel.
+ * On Planet Earth, there are three colors
+ * per pixel, but this is convenient to have here
+ * instead of having 3*panel_bits_per_color
+ * all over the place.
+ */
+ unsigned int panel_bits_per_pixel;
unsigned int xres;
unsigned int yres;
unsigned int voltage;
diff --git a/src/include/vbe.h b/src/include/vbe.h
index 8ad9d2e..009dabd 100644
--- a/src/include/vbe.h
+++ b/src/include/vbe.h
@@ -20,7 +20,7 @@ typedef struct {
u16 screen_width;
u16 screen_height;
u16 screen_linebytes; // bytes per line in framebuffer, may be more than screen_width
- u8 color_depth; // color depth in bpp
+ u8 color_depth; // color depth in bits per pixel
u32 framebuffer_address;
u8 edid_block_zero[128];
} __attribute__ ((__packed__)) screen_info_t;
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 5c2d964..1ad9fea 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -473,12 +473,18 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
* rgb888 (i.e. no alpha, but pixels on 32-bit boundaries)
* The mainboard can modify these if needed, though
* we have yet to see a case where that will happen.
+ * The existing ARM mainboards don't even call this function
+ * so this will not affect them.
*/
- out->bpp = 32;
+ out->framebuffer_bits_per_pixel = 32;
- out->x_resolution = ALIGN(out->ha * ((out->bpp + 7) / 8),64) / (out->bpp/8);
+ out->x_resolution = ALIGN(out->ha *
+ ((out->framebuffer_bits_per_pixel + 7) / 8),
+ 64) / (out->framebuffer_bits_per_pixel/8);
out->y_resolution = out->va;
- out->bytes_per_line = ALIGN(out->ha * ((out->bpp + 7) / 8),64);
+ out->bytes_per_line = ALIGN(out->ha *
+ ((out->framebuffer_bits_per_pixel + 7)/8),
+ 64);
printk(BIOS_SPEW, "Did detailed timing\n");
}
did_detailed_timing = 1;
@@ -1064,7 +1070,8 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
else
printk(BIOS_SPEW, "%d bits per primary color channel\n",
((edid[0x14] & 0x70) >> 3) + 4);
- out->bpp = ((edid[0x14] & 0x70) >> 3) + 4;
+ out->panel_bits_per_color = ((edid[0x14] & 0x70) >> 3) + 4;
+ out->panel_bits_per_pixel = 3*out->panel_bits_per_color;
switch (edid[0x14] & 0x0f) {
case 0x00: printk(BIOS_SPEW, "Digital interface is not defined\n"); break;
@@ -1423,7 +1430,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
edid_fb.x_resolution = edid->x_resolution;
edid_fb.y_resolution = edid->y_resolution;
edid_fb.bytes_per_line = edid->bytes_per_line;
- /* In the case of (e.g.) 24bpp, the convention nowadays
+ /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention nowadays
* seems to be to round it up to the nearest reasonable
* boundary, because otherwise the byte-packing is hideous.
* So, for example, in RGB with no alpha, the bytes are still
@@ -1434,8 +1441,8 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
* It's not clear we're covering all cases here, but
* I'm not sure with grahpics you ever can.
*/
- edid_fb.bits_per_pixel = edid->bpp;
- switch(edid->bpp){
+ edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel;
+ switch(edid->framebuffer_bits_per_pixel){
case 32:
case 24:
/* packed into 4-byte words */
@@ -1457,7 +1464,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
break;
default:
printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__,
- edid->bpp);
+ edid->framebuffer_bits_per_pixel);
return;
}
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 233148c..8d94d36 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -258,7 +258,7 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info,
edid_ok = decode_edid((unsigned char *)&link_edid_data,
sizeof(link_edid_data), &edid);
printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
- edid.bpp = 32;
+ edid.framebuffer_bits_per_pixel = 32;
htotal = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig
index cae34ff..548cd17 100644
--- a/src/mainboard/google/peppy/Kconfig
+++ b/src/mainboard/google/peppy/Kconfig
@@ -18,6 +18,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select MONOTONIC_TIMER_MSR
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_DP
+ select INTEL_DDI
config VBOOT_RAMSTAGE_INDEX
hex
diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc
index 21c4c96..193aa0f 100644
--- a/src/mainboard/google/peppy/Makefile.inc
+++ b/src/mainboard/google/peppy/Makefile.inc
@@ -21,6 +21,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += chromeos.c
ramstage-y += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
@@ -49,3 +50,4 @@ $(SPD_BIN): $(SPD_DEPS)
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := 0xab
+spd.bin-position := 0xfffec000
diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c
new file mode 100644
index 0000000..8e0a3e3
--- /dev/null
+++ b/src/mainboard/google/peppy/gma.c
@@ -0,0 +1,436 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <delay.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/google/chromeec/ec.h>
+#include <cbfs_core.h>
+
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <edid.h>
+#include <drivers/intel/gma/i915.h>
+#include "mainboard.h"
+
+/*
+ * Here is the rough outline of how we bring up the display:
+ * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
+ * 2. Source determines video mode by reading DPCD receiver capability field
+ * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
+ * 0000Dh).
+ * 3. Sink replies DPCD receiver capability field.
+ * 4. Source starts EDID read thru I2C-over-AUX.
+ * 5. Sink replies EDID thru I2C-over-AUX.
+ * 6. Source determines link configuration, such as MAX_LINK_RATE and
+ * MAX_LANE_COUNT. Source also determines which type of eDP Authentication
+ * method to use and writes DPCD link configuration field (DPCD 00100h to
+ * 0010Ah) including eDP configuration set (DPCD 0010Ah).
+ * 7. Source starts link training. Sink does clock recovery and equalization.
+ * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
+ * 9. Sink replies DPCD link status field. If main link is not stable, Source
+ * repeats Step 7.
+ * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
+ * parameters and recovers stream clock.
+ * 11. Source sends video data.
+ */
+
+/* how many bytes do we need for the framebuffer?
+ * Well, this gets messy. To get an exact answer, we have
+ * to ask the panel, but we'd rather zero the memory
+ * and set up the gtt while the panel powers up. So,
+ * we take a reasonable guess, secure in the knowledge that the
+ * MRC has to overestimate the number of bytes used.
+ * 8 MiB is a very safe guess. There may be a better way later, but
+ * fact is, the initial framebuffer is only very temporary. And taking
+ * a little long is ok; this is done much faster than the AUX
+ * channel is ready for IO.
+ */
+#define FRAME_BUFFER_BYTES (8*MiB)
+/* how many 4096-byte pages do we need for the framebuffer?
+ * There are hard ways to get this, and easy ways:
+ * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
+ * on this chip (and in fact every Intel graphics chip we've seen).
+ */
+#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
+
+static unsigned int *mmio;
+static unsigned int graphics;
+static unsigned int physbase;
+extern int oprom_is_loaded;
+
+/* GTT is the Global Translation Table for the graphics pipeline.
+ * It is used to translate graphics addresses to physical
+ * memory addresses. As in the CPU, GTTs map 4K pages.
+ * The setgtt function adds a further bit of flexibility:
+ * it allows you to set a range (the first two parameters) to point
+ * to a physical address (third parameter);the physical address is
+ * incremented by a count (fourth parameter) for each GTT in the
+ * range.
+ * Why do it this way? For ultrafast startup,
+ * we can point all the GTT entries to point to one page,
+ * and set that page to 0s:
+ * memset(physbase, 0, 4096);
+ * setgtt(0, 4250, physbase, 0);
+ * this takes about 2 ms, and is a win because zeroing
+ * the page takes a up to 200 ms.
+ * This call sets the GTT to point to a linear range of pages
+ * starting at physbase.
+ */
+
+#define GTT_PTE_BASE (2 << 20)
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw);
+
+static void
+setgtt(int start, int end, unsigned long base, int inc)
+{
+ int i;
+
+ for(i = start; i < end; i++){
+ u32 word = base + i*inc;
+ /* note: we've confirmed by checking
+ * the values that mrc does no
+ * useful setup before we run this.
+ */
+ gtt_write(GTT_PTE_BASE + i * 4, word|1);
+ gtt_read(GTT_PTE_BASE + i * 4);
+ }
+}
+
+static int i915_init_done = 0;
+
+/* fill the palette. */
+static void palette(void)
+{
+ int i;
+ unsigned long color = 0;
+
+ for(i = 0; i < 256; i++, color += 0x010101){
+ gtt_write(_LGC_PALETTE_A + (i<<2),color);
+ }
+}
+
+/* assumption: the dpcd in the dp is valid. The raw edid has been read
+ * and the translation has been done.
+ */
+void dp_init_dim_regs(struct intel_dp *dp);
+void dp_init_dim_regs(struct intel_dp *dp)
+{
+ struct edid *edid = &(dp->edid);
+
+ /* step 1: get the constants in the dp struct set up. */
+ dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
+
+ dp->link_bw = dp->dpcd[DP_MAX_LINK_RATE];
+ dp->clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+ dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+
+ /* step 2. Do some computation of other stuff. */
+ dp->bytes_per_pixel = dp->pipe_bits_per_pixel/8;
+
+ dp->stride = edid->bytes_per_line;
+
+ dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+
+ dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+
+ dp->hsync = (edid->ha + edid->hso - 1) |
+ ((edid->ha + edid->hso + edid->hspw - 1) << 16);
+
+ dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+
+ dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+
+ dp->vsync = (edid->va + edid->vso - 1) |
+ ((edid->va + edid->vso + edid->vspw - 1) << 16);
+
+ /* PIPEASRC is wid-1 x ht-1 */
+ dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
+
+ dp->pfa_pos = 0;
+
+ /* XXXXXXXXXXXXXX hard code */
+ dp->pfa_ctl = 0x80800000;
+
+ dp->pfa_sz = (edid->ha << 16) | (edid->va);
+
+ /* step 3. Call the linux code we pulled in. */
+ dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
+ dp->port,
+ dp->pipe,
+ dp->type,
+ dp->lane_count,
+ dp->pfa_sz,
+ dp->edid.phsync == '+'?1:0,
+ dp->edid.pvsync == '+'?1:0);
+
+ dp->transcoder = intel_ddi_get_transcoder(dp->port,
+ dp->pipe);
+
+ intel_dp_compute_m_n(edid->panel_bits_per_pixel,
+ dp->lane_count,
+ dp->edid.pixel_clock,
+ dp->edid.link_clock,
+ &dp->m_n);
+
+ printk(BIOS_SPEW, "dp->lane_count = 0x%08x\n",dp->lane_count);
+ printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
+ printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
+ printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
+ printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
+ printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
+ printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
+ printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
+ printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
+ printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
+ printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
+ printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
+ printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
+ printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
+ printk(BIOS_SPEW, "0x6f030 = 0x%08x\n",
+ TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+ printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
+ printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
+ printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
+}
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw)
+{
+ switch (link_bw) {
+ default:
+ printk(BIOS_ERR,
+ "ERROR: link_bw(%d) is bogus; must be one of 6, 0xa, or 0x14\n",
+ link_bw);
+ case DP_LINK_BW_1_62:
+ return 162000;
+ case DP_LINK_BW_2_7:
+ return 270000;
+ case DP_LINK_BW_5_4:
+ return 540000;
+ }
+}
+
+void mainboard_train_link(struct intel_dp *intel_dp)
+{
+ u8 read_val;
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ gtt_write(DP_TP_CTL(intel_dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_CTL_ENABLE|
+ DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011);
+
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp,
+ DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE |
+ DP_SYMBOL_ERROR_COUNT_BOTH);
+
+ intel_dp_set_training_lane0(intel_dp,
+ DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
+ intel_dp_get_link_status(intel_dp, link_status);
+
+ gtt_write(DP_TP_CTL(intel_dp->port),
+ DP_TP_CTL_ENABLE |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
+
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 |
+ DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+ intel_dp_get_link_status(intel_dp, link_status);
+ intel_dp_get_lane_align_status(intel_dp, &read_val);
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE |
+ DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+}
+
+/* This variable controls whether the test_gfx function below puts up
+ * color bars or not. In previous revs we ifdef'd the test_gfx function out
+ * but it's handy, especially when using a JTAG debugger
+ * to be able to enable and disable a test graphics.
+ */
+int show_test = 0;
+
+static void test_gfx(struct intel_dp *dp)
+{
+ int i;
+
+ if (!show_test)
+ return;
+ /* This is a sanity test code which fills the screen with two bands --
+ green and blue. It is very useful to ensure all the initializations
+ are made right. Thus, to be used only for testing, not otherwise
+ */
+ printk(BIOS_SPEW, "TEST: graphics %p, va %d, ha %d, stride %d\n",
+ (u32 *)graphics, dp->edid.va, dp->edid.ha, dp->stride);
+
+ for (i = 0; i < (dp->edid.va - 4); i++) {
+ u32 *l;
+ int j;
+ u32 tcolor = 0x0ff;
+ for (j = 0; j < (dp->edid.ha-4); j++) {
+ if (j == (dp->edid.ha/2)) {
+ tcolor = 0xff00;
+ }
+ l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
+ memcpy(l,&tcolor,sizeof(tcolor));
+ }
+ }
+ printk(BIOS_SPEW, "sleep 10\n");
+ delay(10);
+}
+
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
+{
+ u32 ddi_pll_sel = 0;
+
+ switch (intel_dp->link_bw) {
+ case DP_LINK_BW_1_62:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+ break;
+ case DP_LINK_BW_2_7:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+ break;
+ case DP_LINK_BW_5_4:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+ break;
+ default:
+ printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
+ return;
+ }
+
+ gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
+}
+
+int i915lightup(unsigned int pphysbase, unsigned int pmmio,
+ unsigned int pgfx, unsigned int init_fb)
+{
+ int must_cycle_power = 0;
+ struct intel_dp adp, *dp = &adp;
+ int i;
+ int edid_ok;
+ int pixels = FRAME_BUFFER_BYTES/64;
+
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
+ delay(1);
+ mmio = (void *)pmmio;
+ physbase = pphysbase;
+ graphics = pgfx;
+ printk(BIOS_SPEW,
+ "i915lightup: graphics %p mmio %p"
+ "physbase %08x\n",
+ (void *)graphics, mmio, physbase);
+
+ void runio(struct intel_dp *dp);
+ /* hard codes -- stuff you can only know from the mainboard */
+ dp->gen = 8; // This is gen 8 which we believe is Haswell
+ dp->is_haswell = 1;
+ dp->DP = 0x2;
+ dp->pipe = PIPE_A;
+ dp->port = PORT_A;
+ dp->plane = PLANE_A;
+ dp->pipe_bits_per_pixel = 24;
+ dp->type = INTEL_OUTPUT_EDP;
+ dp->output_reg = DP_A;
+ /* observed from YABEL. */
+ dp->aux_clock_divider = 0xe1;
+ dp->precharge = 3;
+
+ /* CRAP -- needs to be done elsewhere from the device tree. */
+ dp->panel_power_down_delay = 600;
+ dp->panel_power_up_delay = 200;
+ dp->panel_power_cycle_delay = 600;
+
+ /* 1. Normal mode: Set the first page to zero and make
+ all GTT entries point to the same page
+ 2. Developer/Recovery mode: Set up a tasteful color
+ so people know we are alive. */
+ if (init_fb || show_test) {
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
+ memset((void *)graphics, 0x55, FRAME_BUFFER_PAGES*4096);
+ } else {
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
+ memset((void*)graphics, 0, 4096);
+ }
+
+ dp->address = 0x50;
+
+ if ( !intel_dp_get_dpcd(dp) )
+ goto fail;
+
+ intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
+ for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
+ if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
+ 0x50, &dp->rawedid[i]) < 0)
+ break;
+ dp->edidlen++;
+ }
+
+ edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
+
+ printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
+
+ dp_init_dim_regs(dp);
+
+ printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
+ dp->edid.pixel_clock, dp->edid.link_clock);
+
+ intel_ddi_set_pipe_settings(dp);
+
+ runio(dp);
+
+ palette();
+
+ pixels = dp->edid.ha * (dp->edid.va-4) * 4;
+ printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
+ test_gfx(dp);
+
+ set_vbe_mode_info_valid(&dp->edid, graphics);
+ i915_init_done = 1;
+ oprom_is_loaded = 1;
+ return 1;
+
+fail:
+ printk(BIOS_SPEW, "Graphics could not be started;");
+ if (0 && must_cycle_power){
+ printk(BIOS_SPEW, "Turn off power and wait ...");
+ gtt_write(PCH_PP_CONTROL,0xabcd0000);
+ udelay(600000);
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
+ }
+ printk(BIOS_SPEW, "Returning.\n");
+ return 0;
+}
diff --git a/src/mainboard/google/peppy/i915io.c b/src/mainboard/google/peppy/i915io.c
new file mode 100644
index 0000000..693aed5
--- /dev/null
+++ b/src/mainboard/google/peppy/i915io.c
@@ -0,0 +1,144 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <stdint.h>
+#include <console/console.h>
+#include <delay.h>
+#include <drivers/intel/gma/i915.h>
+#include <arch/io.h>
+#include "mainboard.h"
+
+void runio(struct intel_dp *dp, int verbose);
+void runio(struct intel_dp *dp, int verbose)
+{
+ u8 read_val;
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
+ |0x00000091);
+
+ intel_prepare_ddi();
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
+
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+ gtt_write(DSPSTRIDE(dp->plane), dp->stride);
+ gtt_write(DSPADDR(dp->plane), 0x00000000);
+
+ printk(BIOS_SPEW, "DP_SET_POWER");
+
+ intel_dp_sink_dpms(dp, 0);
+
+ intel_dp_set_m_n_regs(dp);
+
+ intel_dp_get_max_downspread(dp, &read_val);
+
+ intel_dp_set_resolution(dp);
+
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+ gtt_write(PIPECONF(dp->transcoder),0x00000000);
+ gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
+
+ mainboard_set_port_clk_dp(dp);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
+
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ /* There is some reason we removed these three calls from
+ * slippy/gma.c -- I dont remember why!! */
+ gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos);
+ gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl);
+ gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz);
+
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
+ gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
+
+ /* what is this doing? Not sure yet. But we don't seem to be
+ * able to live without it.*/
+ intel_dp_i2c_write(dp, 0x0);
+ intel_dp_i2c_read(dp, &read_val);
+ intel_dp_i2c_write(dp, 0x04);
+ intel_dp_i2c_read(dp, &read_val);
+ intel_dp_i2c_write(dp, 0x7e);
+ intel_dp_i2c_read(dp, &read_val);
+
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_IS_IDLE|
+ DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
+ |0x00000091);
+
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001);
+ gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_CTL_ENABLE|
+ /* another undocumented setting. Surprised? */ 0x40000 |
+ DDI_BUF_IS_IDLE|DDI_A_4_LANES|
+ DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|
+ 0x80040091);
+
+ intel_dp_set_bw(dp);
+
+ intel_dp_set_lane_count(dp);
+
+ mainboard_train_link(dp);
+
+ gtt_write(DP_TP_CTL(dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_IDLE);
+
+ gtt_write(DP_TP_CTL(dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_NORMAL);
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
+
+ /* some of this is not needed. But with a total lack of docs, well ...*/
+ gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
+
+ gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+
+}
+
diff --git a/src/mainboard/google/peppy/mainboard.h b/src/mainboard/google/peppy/mainboard.h
new file mode 100644
index 0000000..f47fffd
--- /dev/null
+++ b/src/mainboard/google/peppy/mainboard.h
@@ -0,0 +1,25 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __MAINBOARD_H_
+#define __MAINBOARD_H_
+void mainboard_train_link(struct intel_dp *intel_dp);
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
+
+#endif
diff --git a/src/mainboard/google/pit/devicetree.cb b/src/mainboard/google/pit/devicetree.cb
index 3b6cdb9..687b750 100644
--- a/src/mainboard/google/pit/devicetree.cb
+++ b/src/mainboard/google/pit/devicetree.cb
@@ -21,7 +21,7 @@ chip cpu/samsung/exynos5420
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
- register "bpp" = "16"
+ register "framebuffer_bits_per_pixel" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 467b9d0..693857c 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -52,7 +52,7 @@
static struct edid edid = {
.ha = 1366,
.va = 768,
- .bpp = 16,
+ .framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
.bytes_per_line = 2 * 1366
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 839fa4d..1e19912 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -150,7 +150,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
{
struct edid *edid = &(dp->edid);
- dp->bytes_per_pixel = edid->bpp / 8;
+ dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8;
dp->stride = edid->bytes_per_line;
@@ -189,7 +189,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
dp->transcoder = intel_ddi_get_transcoder(dp->port,
dp->pipe);
- intel_dp_compute_m_n(dp->bpp,
+ intel_dp_compute_m_n(dp->pipe_bits_per_pixel,
dp->lane_count,
dp->edid.pixel_clock,
dp->edid.link_clock,
@@ -336,7 +336,7 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
dp->port = PORT_A;
dp->plane = PLANE_A;
dp->clock = 160000;
- dp->bpp = 32;
+ dp->pipe_bits_per_pixel = 32;
dp->type = INTEL_OUTPUT_EDP;
dp->output_reg = DP_A;
/* observed from YABEL. */
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index c14f374..e6ce49d 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -21,7 +21,7 @@ chip cpu/samsung/exynos5250
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
- register "bpp" = "16"
+ register "framebuffer_bits_per_pixel" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index dfaf81d..bcebac0 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -53,7 +53,7 @@
static struct edid edid = {
.ha = 1366,
.va = 768,
- .bpp = 16,
+ .framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
.bytes_per_line = 2 * 1366
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 9dfba9a..057d65a 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -28,6 +28,7 @@
#include <drivers/intel/gma/i915.h>
#include <cpu/intel/haswell/haswell.h>
#include <stdlib.h>
+#include <string.h>
#include "chip.h"
#include "haswell.h"
@@ -130,7 +131,10 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ u32 val;
+ val = read32(gtt_res->base + reg);
+ return val;
+
}
void gtt_write(u32 reg, u32 data)
@@ -157,7 +161,7 @@ static inline void gtt_write_regs(const struct gt_reg *gt)
}
#define GTT_RETRY 1000
-static int gtt_poll(u32 reg, u32 mask, u32 value)
+int gtt_poll(u32 reg, u32 mask, u32 value)
{
unsigned try = GTT_RETRY;
u32 data;
@@ -177,6 +181,13 @@ static void power_well_enable(void)
{
gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE);
gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE);
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+ /* In the native graphics case, we've got about 20 ms.
+ * after we power up the the AUX channel until we can talk to it.
+ * So get that going right now. We can't turn on the panel, yet, just VDD.
+ */
+ gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET);
+#endif
}
static void gma_pm_init_pre_vbios(struct device *dev)
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6656
-gerrit
commit 188728b150571d6080e848d908b5b7e10ea0225b
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Thu Sep 19 16:45:22 2013 -0700
Peppy graphics
Peppy had some issues with FUI. We decided it was time to create
peppy-specific gma.c and i915io.c files. Using yabel and the i915tool,
we generated a replay attack, then interpolated against the slippy
i915io.c to get something working.
Also, in preparation for moving code out of the mainboard gma.c to
generic driver code, we got rid of some hardcodes in the mainboard
gma.c that have no business being there. The worst were the
computation of gmch_[m,n] and it turns out that we had some
long-standing bugs related to confusion about 'bpp'. I've killed the
word bpp everywhere I could because there are at least 3 things that
correspond to bpp. We now have framebuffer, pipe, and panel bpp. The
names are long because I want to avoid all the mistakes we've all been
making in the last year :-) Sadly, that means a lot of changes not just
peppy-related, but they are simple and in a good cause.
The test pattern generation is driven by a global variable in
mainboard/peppy/gma.c. I've found in the past that it's very useful
to have a function like this available, as one can activate it while
using a jtag debugger: halt at the right place in ramstage, set the
variable to 1, continue. It's not enough code to worry about always
including.
The last hard-codes for M and N registers are gone, and the function
to set from generic intel_dp.c code works. To avoid screen trash on a
dev mode boot, which we liked but nobody else did :-), we now take the
time to put a pleasing background color that sort of doubles as a
power LED.
Rough timing is ramstage start is at 2.2, and dev setup is done at
3.3. These new platforms are depressingly slow to boot. Rom init alone
is taking 1.9 seconds. 13 years ago it was 3 seconds from power on to bash
prompt. These CPUs are at least 10x faster and take much longer to get going.
Future work, once we get this through, is to move more functions to the
intel driver, and combine the mainboard i915io.c into the mainboard gma.c.
That separation only existed because i915io.c was generated by a tool, and it
had lots of ugliness. Most ugliness is gone.
Change-Id: I6a6295b423a41e263f82cef33eacb92a14163321
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/170013
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
Commit-Queue: Ronald Minnich <rminnich(a)chromium.org>
Tested-by: Ronald Minnich <rminnich(a)chromium.org>
Reviewed-by: Furquan Shaikh <furquan.m.shaikh(a)gmail.com>
(cherry picked from commit 8cdaf73e3602e15925859866714db4d5ec6c947d)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/cpu/samsung/exynos5250/chip.h | 2 +-
src/cpu/samsung/exynos5420/chip.h | 2 +-
src/drivers/intel/gma/i915.h | 3 +-
src/drivers/intel/gma/intel_ddi.c | 4 +-
src/drivers/intel/gma/intel_dp.c | 68 ++---
src/include/edid.h | 22 +-
src/include/vbe.h | 2 +-
src/lib/edid.c | 23 +-
src/mainboard/google/link/i915.c | 2 +-
src/mainboard/google/peppy/Kconfig | 3 +
src/mainboard/google/peppy/Makefile.inc | 2 +
src/mainboard/google/peppy/gma.c | 436 ++++++++++++++++++++++++++++++++
src/mainboard/google/peppy/i915io.c | 144 +++++++++++
src/mainboard/google/peppy/mainboard.h | 25 ++
src/mainboard/google/pit/devicetree.cb | 2 +-
src/mainboard/google/pit/mainboard.c | 2 +-
src/mainboard/google/slippy/gma.c | 6 +-
src/mainboard/google/snow/devicetree.cb | 2 +-
src/mainboard/google/snow/mainboard.c | 2 +-
src/northbridge/intel/haswell/gma.c | 15 +-
20 files changed, 699 insertions(+), 68 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h
index f244379..c2e7fb5 100644
--- a/src/cpu/samsung/exynos5250/chip.h
+++ b/src/cpu/samsung/exynos5250/chip.h
@@ -34,7 +34,7 @@ struct cpu_samsung_exynos5250_config {
int xres;
int yres;
- int bpp;
+ int framebuffer_bits_per_pixel;
int usb_vbus_gpio;
int usb_hsic_gpio;
diff --git a/src/cpu/samsung/exynos5420/chip.h b/src/cpu/samsung/exynos5420/chip.h
index f2c710d..220a315 100644
--- a/src/cpu/samsung/exynos5420/chip.h
+++ b/src/cpu/samsung/exynos5420/chip.h
@@ -34,7 +34,7 @@ struct cpu_samsung_exynos5420_config {
int xres;
int yres;
- int bpp;
+ int framebuffer_bits_per_pixel;
int usb_vbus_gpio;
int usb_hsic_gpio;
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 72301e1..e8940a3 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -139,7 +139,7 @@ struct intel_dp {
int port;
int pipe;
int plane;
- int bpp;
+ int pipe_bits_per_pixel;
/* i2c on aux is ... interesting.
* Before you do an i2c cycle, you need to set the address.
* This requires we remember it from one moment to the next.
@@ -272,6 +272,7 @@ int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
void intel_prepare_ddi(void);
void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp);
+int gtt_poll(u32 reg, u32 mask, u32 value);
void gtt_write(u32 reg, u32 data);
u32 gtt_read(u32 reg);
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index 2b27f6e..e51fb9c 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -253,7 +253,7 @@ void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
{
u32 val = TRANS_MSA_SYNC_CLK;
- switch (intel_dp->bpp) {
+ switch (intel_dp->pipe_bits_per_pixel) {
case 18:
val |= TRANS_MSA_6_BPC;
break;
@@ -267,7 +267,7 @@ void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
val |= TRANS_MSA_12_BPC;
break;
default:
- printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->bpp);
+ printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->pipe_bits_per_pixel);
}
gtt_write(TRANS_MSA_MISC(intel_dp->transcoder),val);
}
diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c
index 833a4d6..55e57e6 100644
--- a/src/drivers/intel/gma/intel_dp.c
+++ b/src/drivers/intel/gma/intel_dp.c
@@ -260,7 +260,7 @@ int intel_dp_set_bw(struct intel_dp *intel_dp)
int intel_dp_set_lane_count(struct intel_dp *intel_dp)
{
- printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
+ printk(BIOS_SPEW, "DP_LANE_COUNT_SET %d ", intel_dp->lane_count);
return intel_dp_aux_native_write_1(intel_dp,
DP_LANE_COUNT_SET,
intel_dp->lane_count);
@@ -471,7 +471,20 @@ unsigned int roundup_power_of_two(unsigned int n)
static void compute_m_n(unsigned int m, unsigned int n,
unsigned int *ret_m, unsigned int *ret_n)
{
- *ret_n = MIN(roundup_power_of_two(n), DATA_LINK_N_MAX);
+ /* We noticed in the IO operations that
+ * the VBIOS was setting N to DATA_LINK_N_MAX.
+ * This makes sense, actually: the bigger N is, i.e.
+ * the bigger the denominator is, the bigger
+ * the numerator can be, and the more
+ * bits of numerator you get, the better the result.
+ * So, first pick the max of the two powers of two.
+ * And, in the (unlikely) event that you end up with
+ * something bigger than DATA_LINK_N_MAX, catch that
+ * case with a MIN. Note the second case is unlikely,
+ * but we are best off being careful.
+ */
+ *ret_n = MAX(roundup_power_of_two(n), DATA_LINK_N_MAX);
+ *ret_n = MIN(*ret_n, DATA_LINK_N_MAX);
*ret_m = ( (unsigned long long)m * *ret_n) / n;
intel_reduce_m_n_ratio(ret_m, ret_n);
}
@@ -483,7 +496,6 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
struct intel_dp_m_n *m_n)
{
m_n->tu = 64;
-
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
&m_n->gmch_m, &m_n->gmch_n);
@@ -492,35 +504,6 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
&m_n->link_m, &m_n->link_n);
}
-/* not sure. */
-void intel_dp_set_m_n(struct intel_dp *intel_dp);
-
-void
-intel_dp_set_m_n(struct intel_dp *intel_dp)
-{
- int lane_count;
- struct intel_dp_m_n m_n;
- int pipe = intel_dp->pipe;
-
- lane_count = intel_dp->lane_count;
-
- /*
- * Compute the GMCH and Link ratios. The '3' here is
- * the number of bytes_per_pixel post-LUT, which we always
- * set up for 8-bits of R/G/B, or 3 bytes total.
- */
- intel_dp_compute_m_n(intel_dp->bpp, lane_count,
- intel_dp->clock, intel_dp->clock, &m_n);
-
- {
- gtt_write(TRANSDATA_M1(pipe),
- ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |m_n.gmch_m);
- gtt_write(TRANSDATA_N1(pipe),m_n.gmch_n);
- gtt_write(TRANSDPLINK_M1(pipe),m_n.link_m);
- gtt_write(TRANSDPLINK_N1(pipe),m_n.link_n);
- }
-}
-
static void ironlake_edp_pll_off(void);
void
@@ -1791,17 +1774,13 @@ intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread)
return 1;
}
-void intel_dp_set_m_n_regs(struct intel_dp *intel_dp)
+void intel_dp_set_m_n_regs(struct intel_dp *dp)
{
- gtt_write(PIPE_DATA_M1(intel_dp->transcoder),0x7e4a0000);
- /* gtt_write(0x6f034,0x00800000); */
- /* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important.
- However, with our formula we always see values 0x7e43yyyy (1366 panel) and
- 0x7e42yyy (1280 panel) */
- /* gtt_write(PIPE_DATA_M1(intel_dp->transcoder),TU_SIZE(intel_dp->m_n.tu) | intel_dp->m_n.gmch_m); */
- gtt_write(PIPE_DATA_N1(intel_dp->transcoder),intel_dp->m_n.gmch_n);
- gtt_write(PIPE_LINK_M1(intel_dp->transcoder),intel_dp->m_n.link_m);
- gtt_write(PIPE_LINK_N1(intel_dp->transcoder),intel_dp->m_n.link_n);
+ gtt_write(PIPE_DATA_M1(dp->transcoder),
+ TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+ gtt_write(PIPE_DATA_N1(dp->transcoder),dp->m_n.gmch_n);
+ gtt_write(PIPE_LINK_M1(dp->transcoder),dp->m_n.link_m);
+ gtt_write(PIPE_LINK_N1(dp->transcoder),dp->m_n.link_n);
}
void intel_dp_set_resolution(struct intel_dp *intel_dp)
@@ -1826,10 +1805,13 @@ int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
int intel_dp_get_lane_count(struct intel_dp *intel_dp,
u8 *recv)
{
- return intel_dp_aux_native_read_retry(intel_dp,
+ int val = intel_dp_aux_native_read_retry(intel_dp,
DP_LANE_COUNT_SET,
recv,
0);
+ *recv &= DP_LANE_COUNT_MASK;
+ printk(BIOS_SPEW, "Lane count %s:%d\n", val < 0 ? "fail" : "ok", *recv);
+ return val;
}
int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
diff --git a/src/include/edid.h b/src/include/edid.h
index 4a2f138..867a82f 100644
--- a/src/include/edid.h
+++ b/src/include/edid.h
@@ -35,7 +35,27 @@ struct edid {
unsigned int version[2];
unsigned int nonconformant;
unsigned int type;
- unsigned int bpp;
+ /* These next three things used to all be called bpp.
+ * Merriment ensued. The identifier
+ * 'bpp' is herewith banished from our
+ * Kingdom.
+ */
+ /* How many bits in the framebuffer per pixel.
+ * Under all reasonable circumstances, it's 32.
+ */
+ unsigned int framebuffer_bits_per_pixel;
+ /* On the panel, how many bits per color?
+ * In almost all cases, it's 6 or 8.
+ * The standard allows for much more!
+ */
+ unsigned int panel_bits_per_color;
+ /* On the panel, how many bits per pixel.
+ * On Planet Earth, there are three colors
+ * per pixel, but this is convenient to have here
+ * instead of having 3*panel_bits_per_color
+ * all over the place.
+ */
+ unsigned int panel_bits_per_pixel;
unsigned int xres;
unsigned int yres;
unsigned int voltage;
diff --git a/src/include/vbe.h b/src/include/vbe.h
index 8ad9d2e..009dabd 100644
--- a/src/include/vbe.h
+++ b/src/include/vbe.h
@@ -20,7 +20,7 @@ typedef struct {
u16 screen_width;
u16 screen_height;
u16 screen_linebytes; // bytes per line in framebuffer, may be more than screen_width
- u8 color_depth; // color depth in bpp
+ u8 color_depth; // color depth in bits per pixel
u32 framebuffer_address;
u8 edid_block_zero[128];
} __attribute__ ((__packed__)) screen_info_t;
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 5c2d964..1ad9fea 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -473,12 +473,18 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
* rgb888 (i.e. no alpha, but pixels on 32-bit boundaries)
* The mainboard can modify these if needed, though
* we have yet to see a case where that will happen.
+ * The existing ARM mainboards don't even call this function
+ * so this will not affect them.
*/
- out->bpp = 32;
+ out->framebuffer_bits_per_pixel = 32;
- out->x_resolution = ALIGN(out->ha * ((out->bpp + 7) / 8),64) / (out->bpp/8);
+ out->x_resolution = ALIGN(out->ha *
+ ((out->framebuffer_bits_per_pixel + 7) / 8),
+ 64) / (out->framebuffer_bits_per_pixel/8);
out->y_resolution = out->va;
- out->bytes_per_line = ALIGN(out->ha * ((out->bpp + 7) / 8),64);
+ out->bytes_per_line = ALIGN(out->ha *
+ ((out->framebuffer_bits_per_pixel + 7)/8),
+ 64);
printk(BIOS_SPEW, "Did detailed timing\n");
}
did_detailed_timing = 1;
@@ -1064,7 +1070,8 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
else
printk(BIOS_SPEW, "%d bits per primary color channel\n",
((edid[0x14] & 0x70) >> 3) + 4);
- out->bpp = ((edid[0x14] & 0x70) >> 3) + 4;
+ out->panel_bits_per_color = ((edid[0x14] & 0x70) >> 3) + 4;
+ out->panel_bits_per_pixel = 3*out->panel_bits_per_color;
switch (edid[0x14] & 0x0f) {
case 0x00: printk(BIOS_SPEW, "Digital interface is not defined\n"); break;
@@ -1423,7 +1430,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
edid_fb.x_resolution = edid->x_resolution;
edid_fb.y_resolution = edid->y_resolution;
edid_fb.bytes_per_line = edid->bytes_per_line;
- /* In the case of (e.g.) 24bpp, the convention nowadays
+ /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention nowadays
* seems to be to round it up to the nearest reasonable
* boundary, because otherwise the byte-packing is hideous.
* So, for example, in RGB with no alpha, the bytes are still
@@ -1434,8 +1441,8 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
* It's not clear we're covering all cases here, but
* I'm not sure with grahpics you ever can.
*/
- edid_fb.bits_per_pixel = edid->bpp;
- switch(edid->bpp){
+ edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel;
+ switch(edid->framebuffer_bits_per_pixel){
case 32:
case 24:
/* packed into 4-byte words */
@@ -1457,7 +1464,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
break;
default:
printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__,
- edid->bpp);
+ edid->framebuffer_bits_per_pixel);
return;
}
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 233148c..8d94d36 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -258,7 +258,7 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info,
edid_ok = decode_edid((unsigned char *)&link_edid_data,
sizeof(link_edid_data), &edid);
printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
- edid.bpp = 32;
+ edid.framebuffer_bits_per_pixel = 32;
htotal = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig
index cae34ff..548cd17 100644
--- a/src/mainboard/google/peppy/Kconfig
+++ b/src/mainboard/google/peppy/Kconfig
@@ -18,6 +18,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select MONOTONIC_TIMER_MSR
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_DP
+ select INTEL_DDI
config VBOOT_RAMSTAGE_INDEX
hex
diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc
index 21c4c96..193aa0f 100644
--- a/src/mainboard/google/peppy/Makefile.inc
+++ b/src/mainboard/google/peppy/Makefile.inc
@@ -21,6 +21,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += chromeos.c
ramstage-y += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
@@ -49,3 +50,4 @@ $(SPD_BIN): $(SPD_DEPS)
cbfs-files-y += spd.bin
spd.bin-file := $(SPD_BIN)
spd.bin-type := 0xab
+spd.bin-position := 0xfffec000
diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c
new file mode 100644
index 0000000..8e0a3e3
--- /dev/null
+++ b/src/mainboard/google/peppy/gma.c
@@ -0,0 +1,436 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <delay.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/google/chromeec/ec.h>
+#include <cbfs_core.h>
+
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <edid.h>
+#include <drivers/intel/gma/i915.h>
+#include "mainboard.h"
+
+/*
+ * Here is the rough outline of how we bring up the display:
+ * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
+ * 2. Source determines video mode by reading DPCD receiver capability field
+ * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
+ * 0000Dh).
+ * 3. Sink replies DPCD receiver capability field.
+ * 4. Source starts EDID read thru I2C-over-AUX.
+ * 5. Sink replies EDID thru I2C-over-AUX.
+ * 6. Source determines link configuration, such as MAX_LINK_RATE and
+ * MAX_LANE_COUNT. Source also determines which type of eDP Authentication
+ * method to use and writes DPCD link configuration field (DPCD 00100h to
+ * 0010Ah) including eDP configuration set (DPCD 0010Ah).
+ * 7. Source starts link training. Sink does clock recovery and equalization.
+ * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
+ * 9. Sink replies DPCD link status field. If main link is not stable, Source
+ * repeats Step 7.
+ * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
+ * parameters and recovers stream clock.
+ * 11. Source sends video data.
+ */
+
+/* how many bytes do we need for the framebuffer?
+ * Well, this gets messy. To get an exact answer, we have
+ * to ask the panel, but we'd rather zero the memory
+ * and set up the gtt while the panel powers up. So,
+ * we take a reasonable guess, secure in the knowledge that the
+ * MRC has to overestimate the number of bytes used.
+ * 8 MiB is a very safe guess. There may be a better way later, but
+ * fact is, the initial framebuffer is only very temporary. And taking
+ * a little long is ok; this is done much faster than the AUX
+ * channel is ready for IO.
+ */
+#define FRAME_BUFFER_BYTES (8*MiB)
+/* how many 4096-byte pages do we need for the framebuffer?
+ * There are hard ways to get this, and easy ways:
+ * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
+ * on this chip (and in fact every Intel graphics chip we've seen).
+ */
+#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
+
+static unsigned int *mmio;
+static unsigned int graphics;
+static unsigned int physbase;
+extern int oprom_is_loaded;
+
+/* GTT is the Global Translation Table for the graphics pipeline.
+ * It is used to translate graphics addresses to physical
+ * memory addresses. As in the CPU, GTTs map 4K pages.
+ * The setgtt function adds a further bit of flexibility:
+ * it allows you to set a range (the first two parameters) to point
+ * to a physical address (third parameter);the physical address is
+ * incremented by a count (fourth parameter) for each GTT in the
+ * range.
+ * Why do it this way? For ultrafast startup,
+ * we can point all the GTT entries to point to one page,
+ * and set that page to 0s:
+ * memset(physbase, 0, 4096);
+ * setgtt(0, 4250, physbase, 0);
+ * this takes about 2 ms, and is a win because zeroing
+ * the page takes a up to 200 ms.
+ * This call sets the GTT to point to a linear range of pages
+ * starting at physbase.
+ */
+
+#define GTT_PTE_BASE (2 << 20)
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw);
+
+static void
+setgtt(int start, int end, unsigned long base, int inc)
+{
+ int i;
+
+ for(i = start; i < end; i++){
+ u32 word = base + i*inc;
+ /* note: we've confirmed by checking
+ * the values that mrc does no
+ * useful setup before we run this.
+ */
+ gtt_write(GTT_PTE_BASE + i * 4, word|1);
+ gtt_read(GTT_PTE_BASE + i * 4);
+ }
+}
+
+static int i915_init_done = 0;
+
+/* fill the palette. */
+static void palette(void)
+{
+ int i;
+ unsigned long color = 0;
+
+ for(i = 0; i < 256; i++, color += 0x010101){
+ gtt_write(_LGC_PALETTE_A + (i<<2),color);
+ }
+}
+
+/* assumption: the dpcd in the dp is valid. The raw edid has been read
+ * and the translation has been done.
+ */
+void dp_init_dim_regs(struct intel_dp *dp);
+void dp_init_dim_regs(struct intel_dp *dp)
+{
+ struct edid *edid = &(dp->edid);
+
+ /* step 1: get the constants in the dp struct set up. */
+ dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
+
+ dp->link_bw = dp->dpcd[DP_MAX_LINK_RATE];
+ dp->clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+ dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+
+ /* step 2. Do some computation of other stuff. */
+ dp->bytes_per_pixel = dp->pipe_bits_per_pixel/8;
+
+ dp->stride = edid->bytes_per_line;
+
+ dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+
+ dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+
+ dp->hsync = (edid->ha + edid->hso - 1) |
+ ((edid->ha + edid->hso + edid->hspw - 1) << 16);
+
+ dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+
+ dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+
+ dp->vsync = (edid->va + edid->vso - 1) |
+ ((edid->va + edid->vso + edid->vspw - 1) << 16);
+
+ /* PIPEASRC is wid-1 x ht-1 */
+ dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
+
+ dp->pfa_pos = 0;
+
+ /* XXXXXXXXXXXXXX hard code */
+ dp->pfa_ctl = 0x80800000;
+
+ dp->pfa_sz = (edid->ha << 16) | (edid->va);
+
+ /* step 3. Call the linux code we pulled in. */
+ dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
+ dp->port,
+ dp->pipe,
+ dp->type,
+ dp->lane_count,
+ dp->pfa_sz,
+ dp->edid.phsync == '+'?1:0,
+ dp->edid.pvsync == '+'?1:0);
+
+ dp->transcoder = intel_ddi_get_transcoder(dp->port,
+ dp->pipe);
+
+ intel_dp_compute_m_n(edid->panel_bits_per_pixel,
+ dp->lane_count,
+ dp->edid.pixel_clock,
+ dp->edid.link_clock,
+ &dp->m_n);
+
+ printk(BIOS_SPEW, "dp->lane_count = 0x%08x\n",dp->lane_count);
+ printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
+ printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
+ printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
+ printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
+ printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
+ printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
+ printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
+ printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
+ printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
+ printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
+ printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
+ printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
+ printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
+ printk(BIOS_SPEW, "0x6f030 = 0x%08x\n",
+ TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+ printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
+ printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
+ printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
+}
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw)
+{
+ switch (link_bw) {
+ default:
+ printk(BIOS_ERR,
+ "ERROR: link_bw(%d) is bogus; must be one of 6, 0xa, or 0x14\n",
+ link_bw);
+ case DP_LINK_BW_1_62:
+ return 162000;
+ case DP_LINK_BW_2_7:
+ return 270000;
+ case DP_LINK_BW_5_4:
+ return 540000;
+ }
+}
+
+void mainboard_train_link(struct intel_dp *intel_dp)
+{
+ u8 read_val;
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ gtt_write(DP_TP_CTL(intel_dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_CTL_ENABLE|
+ DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011);
+
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp,
+ DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE |
+ DP_SYMBOL_ERROR_COUNT_BOTH);
+
+ intel_dp_set_training_lane0(intel_dp,
+ DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
+ intel_dp_get_link_status(intel_dp, link_status);
+
+ gtt_write(DP_TP_CTL(intel_dp->port),
+ DP_TP_CTL_ENABLE |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
+
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 |
+ DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+ intel_dp_get_link_status(intel_dp, link_status);
+ intel_dp_get_lane_align_status(intel_dp, &read_val);
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE |
+ DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+}
+
+/* This variable controls whether the test_gfx function below puts up
+ * color bars or not. In previous revs we ifdef'd the test_gfx function out
+ * but it's handy, especially when using a JTAG debugger
+ * to be able to enable and disable a test graphics.
+ */
+int show_test = 0;
+
+static void test_gfx(struct intel_dp *dp)
+{
+ int i;
+
+ if (!show_test)
+ return;
+ /* This is a sanity test code which fills the screen with two bands --
+ green and blue. It is very useful to ensure all the initializations
+ are made right. Thus, to be used only for testing, not otherwise
+ */
+ printk(BIOS_SPEW, "TEST: graphics %p, va %d, ha %d, stride %d\n",
+ (u32 *)graphics, dp->edid.va, dp->edid.ha, dp->stride);
+
+ for (i = 0; i < (dp->edid.va - 4); i++) {
+ u32 *l;
+ int j;
+ u32 tcolor = 0x0ff;
+ for (j = 0; j < (dp->edid.ha-4); j++) {
+ if (j == (dp->edid.ha/2)) {
+ tcolor = 0xff00;
+ }
+ l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
+ memcpy(l,&tcolor,sizeof(tcolor));
+ }
+ }
+ printk(BIOS_SPEW, "sleep 10\n");
+ delay(10);
+}
+
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
+{
+ u32 ddi_pll_sel = 0;
+
+ switch (intel_dp->link_bw) {
+ case DP_LINK_BW_1_62:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+ break;
+ case DP_LINK_BW_2_7:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+ break;
+ case DP_LINK_BW_5_4:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+ break;
+ default:
+ printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
+ return;
+ }
+
+ gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
+}
+
+int i915lightup(unsigned int pphysbase, unsigned int pmmio,
+ unsigned int pgfx, unsigned int init_fb)
+{
+ int must_cycle_power = 0;
+ struct intel_dp adp, *dp = &adp;
+ int i;
+ int edid_ok;
+ int pixels = FRAME_BUFFER_BYTES/64;
+
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
+ delay(1);
+ mmio = (void *)pmmio;
+ physbase = pphysbase;
+ graphics = pgfx;
+ printk(BIOS_SPEW,
+ "i915lightup: graphics %p mmio %p"
+ "physbase %08x\n",
+ (void *)graphics, mmio, physbase);
+
+ void runio(struct intel_dp *dp);
+ /* hard codes -- stuff you can only know from the mainboard */
+ dp->gen = 8; // This is gen 8 which we believe is Haswell
+ dp->is_haswell = 1;
+ dp->DP = 0x2;
+ dp->pipe = PIPE_A;
+ dp->port = PORT_A;
+ dp->plane = PLANE_A;
+ dp->pipe_bits_per_pixel = 24;
+ dp->type = INTEL_OUTPUT_EDP;
+ dp->output_reg = DP_A;
+ /* observed from YABEL. */
+ dp->aux_clock_divider = 0xe1;
+ dp->precharge = 3;
+
+ /* CRAP -- needs to be done elsewhere from the device tree. */
+ dp->panel_power_down_delay = 600;
+ dp->panel_power_up_delay = 200;
+ dp->panel_power_cycle_delay = 600;
+
+ /* 1. Normal mode: Set the first page to zero and make
+ all GTT entries point to the same page
+ 2. Developer/Recovery mode: Set up a tasteful color
+ so people know we are alive. */
+ if (init_fb || show_test) {
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
+ memset((void *)graphics, 0x55, FRAME_BUFFER_PAGES*4096);
+ } else {
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
+ memset((void*)graphics, 0, 4096);
+ }
+
+ dp->address = 0x50;
+
+ if ( !intel_dp_get_dpcd(dp) )
+ goto fail;
+
+ intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
+ for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
+ if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
+ 0x50, &dp->rawedid[i]) < 0)
+ break;
+ dp->edidlen++;
+ }
+
+ edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
+
+ printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
+
+ dp_init_dim_regs(dp);
+
+ printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
+ dp->edid.pixel_clock, dp->edid.link_clock);
+
+ intel_ddi_set_pipe_settings(dp);
+
+ runio(dp);
+
+ palette();
+
+ pixels = dp->edid.ha * (dp->edid.va-4) * 4;
+ printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
+ test_gfx(dp);
+
+ set_vbe_mode_info_valid(&dp->edid, graphics);
+ i915_init_done = 1;
+ oprom_is_loaded = 1;
+ return 1;
+
+fail:
+ printk(BIOS_SPEW, "Graphics could not be started;");
+ if (0 && must_cycle_power){
+ printk(BIOS_SPEW, "Turn off power and wait ...");
+ gtt_write(PCH_PP_CONTROL,0xabcd0000);
+ udelay(600000);
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
+ }
+ printk(BIOS_SPEW, "Returning.\n");
+ return 0;
+}
diff --git a/src/mainboard/google/peppy/i915io.c b/src/mainboard/google/peppy/i915io.c
new file mode 100644
index 0000000..693aed5
--- /dev/null
+++ b/src/mainboard/google/peppy/i915io.c
@@ -0,0 +1,144 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <stdint.h>
+#include <console/console.h>
+#include <delay.h>
+#include <drivers/intel/gma/i915.h>
+#include <arch/io.h>
+#include "mainboard.h"
+
+void runio(struct intel_dp *dp, int verbose);
+void runio(struct intel_dp *dp, int verbose)
+{
+ u8 read_val;
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
+ |0x00000091);
+
+ intel_prepare_ddi();
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
+
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+ gtt_write(DSPSTRIDE(dp->plane), dp->stride);
+ gtt_write(DSPADDR(dp->plane), 0x00000000);
+
+ printk(BIOS_SPEW, "DP_SET_POWER");
+
+ intel_dp_sink_dpms(dp, 0);
+
+ intel_dp_set_m_n_regs(dp);
+
+ intel_dp_get_max_downspread(dp, &read_val);
+
+ intel_dp_set_resolution(dp);
+
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+ gtt_write(PIPECONF(dp->transcoder),0x00000000);
+ gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
+
+ mainboard_set_port_clk_dp(dp);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
+
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ /* There is some reason we removed these three calls from
+ * slippy/gma.c -- I dont remember why!! */
+ gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos);
+ gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl);
+ gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz);
+
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
+ gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
+
+ /* what is this doing? Not sure yet. But we don't seem to be
+ * able to live without it.*/
+ intel_dp_i2c_write(dp, 0x0);
+ intel_dp_i2c_read(dp, &read_val);
+ intel_dp_i2c_write(dp, 0x04);
+ intel_dp_i2c_read(dp, &read_val);
+ intel_dp_i2c_write(dp, 0x7e);
+ intel_dp_i2c_read(dp, &read_val);
+
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_IS_IDLE|
+ DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
+ |0x00000091);
+
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001);
+ gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_CTL_ENABLE|
+ /* another undocumented setting. Surprised? */ 0x40000 |
+ DDI_BUF_IS_IDLE|DDI_A_4_LANES|
+ DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|
+ 0x80040091);
+
+ intel_dp_set_bw(dp);
+
+ intel_dp_set_lane_count(dp);
+
+ mainboard_train_link(dp);
+
+ gtt_write(DP_TP_CTL(dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_IDLE);
+
+ gtt_write(DP_TP_CTL(dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_NORMAL);
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
+
+ /* some of this is not needed. But with a total lack of docs, well ...*/
+ gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
+
+ gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+
+}
+
diff --git a/src/mainboard/google/peppy/mainboard.h b/src/mainboard/google/peppy/mainboard.h
new file mode 100644
index 0000000..f47fffd
--- /dev/null
+++ b/src/mainboard/google/peppy/mainboard.h
@@ -0,0 +1,25 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __MAINBOARD_H_
+#define __MAINBOARD_H_
+void mainboard_train_link(struct intel_dp *intel_dp);
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
+
+#endif
diff --git a/src/mainboard/google/pit/devicetree.cb b/src/mainboard/google/pit/devicetree.cb
index 3b6cdb9..687b750 100644
--- a/src/mainboard/google/pit/devicetree.cb
+++ b/src/mainboard/google/pit/devicetree.cb
@@ -21,7 +21,7 @@ chip cpu/samsung/exynos5420
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
- register "bpp" = "16"
+ register "framebuffer_bits_per_pixel" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 467b9d0..693857c 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -52,7 +52,7 @@
static struct edid edid = {
.ha = 1366,
.va = 768,
- .bpp = 16,
+ .framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
.bytes_per_line = 2 * 1366
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 839fa4d..1e19912 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -150,7 +150,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
{
struct edid *edid = &(dp->edid);
- dp->bytes_per_pixel = edid->bpp / 8;
+ dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8;
dp->stride = edid->bytes_per_line;
@@ -189,7 +189,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
dp->transcoder = intel_ddi_get_transcoder(dp->port,
dp->pipe);
- intel_dp_compute_m_n(dp->bpp,
+ intel_dp_compute_m_n(dp->pipe_bits_per_pixel,
dp->lane_count,
dp->edid.pixel_clock,
dp->edid.link_clock,
@@ -336,7 +336,7 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
dp->port = PORT_A;
dp->plane = PLANE_A;
dp->clock = 160000;
- dp->bpp = 32;
+ dp->pipe_bits_per_pixel = 32;
dp->type = INTEL_OUTPUT_EDP;
dp->output_reg = DP_A;
/* observed from YABEL. */
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index c14f374..c49ccc0 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -21,7 +21,7 @@ chip cpu/samsung/exynos5250
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
- register "bpp" = "16"
+ register "framebuffer_pits_per_pixel" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index dfaf81d..bcebac0 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -53,7 +53,7 @@
static struct edid edid = {
.ha = 1366,
.va = 768,
- .bpp = 16,
+ .framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
.bytes_per_line = 2 * 1366
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 9dfba9a..057d65a 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -28,6 +28,7 @@
#include <drivers/intel/gma/i915.h>
#include <cpu/intel/haswell/haswell.h>
#include <stdlib.h>
+#include <string.h>
#include "chip.h"
#include "haswell.h"
@@ -130,7 +131,10 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ u32 val;
+ val = read32(gtt_res->base + reg);
+ return val;
+
}
void gtt_write(u32 reg, u32 data)
@@ -157,7 +161,7 @@ static inline void gtt_write_regs(const struct gt_reg *gt)
}
#define GTT_RETRY 1000
-static int gtt_poll(u32 reg, u32 mask, u32 value)
+int gtt_poll(u32 reg, u32 mask, u32 value)
{
unsigned try = GTT_RETRY;
u32 data;
@@ -177,6 +181,13 @@ static void power_well_enable(void)
{
gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE);
gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE);
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+ /* In the native graphics case, we've got about 20 ms.
+ * after we power up the the AUX channel until we can talk to it.
+ * So get that going right now. We can't turn on the panel, yet, just VDD.
+ */
+ gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET);
+#endif
}
static void gma_pm_init_pre_vbios(struct device *dev)
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6655
-gerrit
commit 007668a58e21757916b5c15e38396b834e9f8b58
Author: Gabe Black <gabeblack(a)google.com>
Date: Thu Sep 26 16:13:08 2013 -0700
libpayload: Change CONFIG_X86_SERIAL_CONSOLE to CONFIG_8250_SERIAL_CONSOLE
While the 8250 compatible serial port driver is primarily useful on x86
systems because it works with the legacy x86 com ports, some devices which
aren't x86 based have 8250 compatible UARTs as well. This change renames the
CONFIG_X86_SERIAL_CONSOLE option to the more general and direct
CONFIG_8250_SERIAL_CONSOLE and fixes up the dependencies so that non-x86
systems can enable the driver, although it will default to on on x86 and off
otherwise.
Also, the default IO port address that's added to the sysinfo structure on x86
and which is intended to be overwritten by a value in the coreboot tables is
not used on ARM. That variable is adjusted so that it's more clear it's a
default value, and made dependent on x86 since that's the only place its value
is actually used.
Change-Id: Ifeaade0e7bd76d382426e947275a9c933da4930e
Signed-off-by: Gabe Black <gabeblack(a)google.com>
Reviewed-on: https://chromium-review.googlesource.com/170834
Reviewed-by: Hung-Te Lin <hungte(a)chromium.org>
Commit-Queue: Gabe Black <gabeblack(a)chromium.org>
Tested-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 9a10e39a2da3cb0bfb316c0869cf5025078e287f)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
payloads/libpayload/Config.in | 14 ++++++++------
payloads/libpayload/configs/defconfig | 2 +-
payloads/libpayload/drivers/Makefile.inc | 2 +-
payloads/libpayload/tests/libpayload-config.h | 2 +-
4 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in
index f28f9b8..e3e064e 100644
--- a/payloads/libpayload/Config.in
+++ b/payloads/libpayload/Config.in
@@ -162,14 +162,16 @@ config SERIAL_CONSOLE
bool "See output on the serial port console"
default y
-config X86_SERIAL_CONSOLE
- bool
- depends on ARCH_X86 && SERIAL_CONSOLE
- default y
+config 8250_SERIAL_CONSOLE
+ bool "8250, 16450, 16550, 16550A compatible serial port driver"
+ depends on SERIAL_CONSOLE
+ default y if ARCH_X86
+ default n if !ARCH_X86
config SERIAL_IOBASE
- hex "I/O base for the serial port (default 0x3f8)"
- depends on X86_SERIAL_CONSOLE
+ ## This default is currently not used on non-x86 systems.
+ hex "Default I/O base for the serial port (default 0x3f8)"
+ depends on SERIAL_CONSOLE && ARCH_X86
default 0x3f8
config SERIAL_SET_SPEED
diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig
index 5804ed8..aef9fc3 100644
--- a/payloads/libpayload/configs/defconfig
+++ b/payloads/libpayload/configs/defconfig
@@ -36,7 +36,7 @@ CONFIG_LP_LZMA=y
# CONFIG_LP_SKIP_CONSOLE_INIT is not set
CONFIG_LP_CBMEM_CONSOLE=y
CONFIG_LP_SERIAL_CONSOLE=y
-CONFIG_LP_X86_SERIAL_CONSOLE=y
+CONFIG_LP_8250_SERIAL_CONSOLE=y
CONFIG_LP_SERIAL_IOBASE=0x3f8
# CONFIG_LP_SERIAL_SET_SPEED is not set
# CONFIG_LP_SERIAL_ACS_FALLBACK is not set
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
index b31e341..881c801 100644
--- a/payloads/libpayload/drivers/Makefile.inc
+++ b/payloads/libpayload/drivers/Makefile.inc
@@ -33,7 +33,7 @@ libc-$(CONFIG_LP_PCI) += pci.c
libc-$(CONFIG_LP_SPEAKER) += speaker.c
-libc-$(CONFIG_LP_X86_SERIAL_CONSOLE) += serial.c
+libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial.c
libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c
diff --git a/payloads/libpayload/tests/libpayload-config.h b/payloads/libpayload/tests/libpayload-config.h
index 68995b8..cce7c4c 100644
--- a/payloads/libpayload/tests/libpayload-config.h
+++ b/payloads/libpayload/tests/libpayload-config.h
@@ -15,7 +15,7 @@
#define CONFIG_LP_STORAGE_ATA 1
#define CONFIG_LP_ARCH_SPECIFIC_OPTIONS 1
#define CONFIG_LP_STORAGE_AHCI_ONLY_TESTED 1
-#define CONFIG_LP_X86_SERIAL_CONSOLE 1
+#define CONFIG_LP_8250_SERIAL_CONSOLE 1
#define CONFIG_LP_PDCURSES 1
#define CONFIG_LP_NVRAM 1
#define CONFIG_LP_PC_KEYBOARD_LAYOUT_US 1
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6651
-gerrit
commit 0af8035e39ded5687d2c35ecfd9c7ed0d36cfb78
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Wed Aug 13 23:04:46 2014 +0200
lenovo/x200: Fix black screen on quick boot.
Otherwise without USB when coreboot boots too quickly
EC is confused and thinks that LID is closed and so
powers off the backlight until user flaps the lid.
Change-Id: I14dfaa62582de83fd4c9f9518e9436b3a3035366
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/lenovo/x200/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index f46bf35..278b464 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -156,7 +156,7 @@ chip northbridge/intel/gm45
end
register "config0" = "0xa6"
- register "config1" = "0x05"
+ register "config1" = "0x04"
register "config2" = "0xa0"
register "config3" = "0x01"
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6654
-gerrit
commit 2c88cb5b52e0a6711db3d62383b446bd36fcb270
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Sep 25 13:54:57 2013 -0700
libpayload: usbmsc: Remove DETACHED state from MSC device structure
The USB MSC device structure contains a "ready" state that can be either
"ready", "not ready" or "detached". The last one can only be assigned
when the device is completely unresponsive and gets forcefully logically
detached via usb_detach_device(). This call (at least in the current
version) also calls all destructors and frees the complete usbdev_t
structure (including the MSC specific part), which unfortunately makes
storing the "detached" state in that very structure a little pointless.
This patch reduces the "ready" value to a simple boolean and makes sure
that all detachment cases immediately return from the MSC driver,
carefully avoiding any use-after-free opportunities.
Change-Id: Iff1c0849f9ce7c95d399bb9a1a0a94469951194d
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170667
(cherry picked from commit fd4529f37fdd1c93a8b902488ffeef7001b1a05a)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
payloads/libpayload/drivers/usb/usbmsc.c | 83 +++++++++-----------------------
1 file changed, 22 insertions(+), 61 deletions(-)
diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c
index 464d73d..037ead3 100644
--- a/payloads/libpayload/drivers/usb/usbmsc.c
+++ b/payloads/libpayload/drivers/usb/usbmsc.c
@@ -67,36 +67,6 @@ static const char *msc_protocol_strings[0x51] = {
"Bulk-Only Transport"
};
-static inline void
-usb_msc_mark_ready (usbdev_t *dev)
-{
- MSC_INST (dev)->ready = USB_MSC_READY;
-}
-
-static inline void
-usb_msc_mark_not_ready (usbdev_t *dev)
-{
- MSC_INST (dev)->ready = USB_MSC_NOT_READY;
-}
-
-static inline void
-usb_msc_mark_detached (usbdev_t *dev)
-{
- MSC_INST (dev)->ready = USB_MSC_DETACHED;
-}
-
-static inline int
-usb_msc_is_detached (usbdev_t *dev)
-{
- return MSC_INST (dev)->ready == USB_MSC_DETACHED;
-}
-
-static inline int
-usb_msc_is_ready (usbdev_t *dev)
-{
- return MSC_INST (dev)->ready == USB_MSC_READY;
-}
-
static void
usb_msc_create_disk (usbdev_t *dev)
{
@@ -156,7 +126,8 @@ enum {
* MSC commands can be
* successful,
* fail with proper response or
- * fail totally, which results in detaching of the usb device.
+ * fail totally, which results in detaching of the usb device
+ * and immediate cleanup of the usbdev_t structure.
* In the latter case the caller has to make sure, that he won't
* use the device any more.
*/
@@ -468,7 +439,7 @@ static int request_sense_no_media (usbdev_t *dev)
/* No media is present. Return MSC_COMMAND_OK while marking the disk
* not ready. */
usb_debug ("Empty media found.\n");
- usb_msc_mark_not_ready (dev);
+ MSC_INST (dev)->ready = USB_MSC_NOT_READY;
return MSC_COMMAND_OK;
}
@@ -533,7 +504,7 @@ read_capacity (usbdev_t *dev)
return MSC_COMMAND_OK;
}
-static void
+static int
usb_msc_test_unit_ready (usbdev_t *dev)
{
int i;
@@ -547,7 +518,7 @@ usb_msc_test_unit_ready (usbdev_t *dev)
usb_debug (" Waiting for device to become ready...");
/* Initially mark the device ready. */
- usb_msc_mark_ready (dev);
+ MSC_INST (dev)->ready = USB_MSC_READY;
gettimeofday (&tv, NULL);
start_time_secs = tv.tv_sec;
@@ -561,22 +532,21 @@ usb_msc_test_unit_ready (usbdev_t *dev)
gettimeofday (&tv, NULL);
continue;
default:
- usb_debug ("detached. Device not ready.\n");
- usb_msc_mark_detached (dev);
- return;
+ /* Device detached, return immediately */
+ return USB_MSC_DETACHED;
}
break;
}
if (!(tv.tv_sec - start_time_secs < timeout_secs)) {
usb_debug ("timeout. Device not ready.\n");
- usb_msc_mark_not_ready (dev);
+ MSC_INST (dev)->ready = USB_MSC_NOT_READY;
}
/* Don't bother spinning up the stroage device if the device is not
* ready. This can happen when empty card readers are present.
* Polling will pick it back up if readiness changes. */
- if (!usb_msc_is_ready (dev))
- return;
+ if (!MSC_INST (dev)->ready)
+ return MSC_INST (dev)->ready;
usb_debug ("ok.\n");
@@ -591,16 +561,17 @@ usb_msc_test_unit_ready (usbdev_t *dev)
mdelay (100);
continue;
default:
- /* Device is no longer ready. */
- usb_msc_mark_detached (dev);
- return;
+ /* Device detached, return immediately */
+ return USB_MSC_DETACHED;
}
break;
}
usb_debug ("\n");
- if (read_capacity (dev) != MSC_COMMAND_OK)
- usb_msc_mark_not_ready (dev);
+ if (read_capacity (dev) == MSC_COMMAND_DETACHED)
+ return USB_MSC_DETACHED;
+
+ return MSC_INST (dev)->ready;
}
void
@@ -646,7 +617,6 @@ usb_msc_init (usbdev_t *dev)
MSC_INST (dev)->bulk_in = 0;
MSC_INST (dev)->bulk_out = 0;
MSC_INST (dev)->usbdisk_created = 0;
- usb_msc_mark_ready (dev);
for (i = 1; i <= dev->num_endp; i++) {
if (dev->endpoints[i].endpoint == 0)
@@ -675,11 +645,8 @@ usb_msc_init (usbdev_t *dev)
usb_debug (" has %d luns\n", get_max_luns (dev) + 1);
- /* Test if unit is ready. */
- usb_msc_test_unit_ready (dev);
-
- /* Nothing to do if device is not ready. */
- if (!usb_msc_is_ready (dev))
+ /* Test if unit is ready (nothing to do if it isn't). */
+ if (usb_msc_test_unit_ready (dev) != USB_MSC_READY)
return;
/* Create the disk. */
@@ -689,21 +656,15 @@ usb_msc_init (usbdev_t *dev)
static void
usb_msc_poll (usbdev_t *dev)
{
- int prev_ready;
+ int prev_ready = MSC_INST (dev)->ready;
- /* Nothing to do if device is detached. */
- if (usb_msc_is_detached (dev))
+ if (usb_msc_test_unit_ready (dev) == USB_MSC_DETACHED)
return;
- /* Handle ready transitions by keeping track of previous state . */
- prev_ready = usb_msc_is_ready (dev);
-
- usb_msc_test_unit_ready (dev);
-
- if (!prev_ready && usb_msc_is_ready (dev)) {
+ if (!prev_ready && MSC_INST (dev)->ready) {
usb_debug ("usb msc: not ready -> ready\n");
usb_msc_create_disk (dev);
- } else if (prev_ready && !usb_msc_is_ready (dev)) {
+ } else if (prev_ready && !MSC_INST (dev)->ready) {
usb_debug ("usb msc: ready -> not ready\n");
usb_msc_remove_disk (dev);
}