the following patch was just integrated into master:
commit 6202aea9220f6a423429cba625c0444f88f9bb58
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Jun 20 05:41:21 2014 +0300
PS2 keyboard: Use acpi_is_wakeup_s3()
Change-Id: I812cc40e50a1e7e13caed48a1693feb8658b645c
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6073
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6073 for details.
-gerrit
the following patch was just integrated into master:
commit c3c4a38c95b90fbf713e98f7b4d1e5be18bee633
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Jun 20 05:21:30 2014 +0300
Misc: Use acpi_is_wakeup_s3()
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6072
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6072 for details.
-gerrit
the following patch was just integrated into master:
commit c3ed88636a3533b97cef5bcb445cbe61edbfae7f
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Jun 19 19:50:51 2014 +0300
intel boards: Use acpi_is_wakeup_s3()
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/6071
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/6071 for details.
-gerrit
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6090
-gerrit
commit d8118f93932318b782a89e7645ffeee0a21f25be
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Fri Jun 20 21:21:51 2014 -0600
fsp_baytrail: Minor Kconfig updates
- remove the Kconfig text when setting the default for the FSP location.
The text was showing up twice in the config menu.
- Remove an extra 'the' in the help text.
Change-Id: I3777833bf32e19bbe5a8493578a9346d6ab062a4
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/soc/intel/fsp_baytrail/fsp/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig
index 0949325..73800d6 100644
--- a/src/soc/intel/fsp_baytrail/fsp/Kconfig
+++ b/src/soc/intel/fsp_baytrail/fsp/Kconfig
@@ -30,12 +30,12 @@ config FSP_FILE
The path and filename of the Intel FSP binary for this platform.
config FSP_LOC
- hex "Intel FSP Binary location in CBFS"
+ hex
default 0xfffc0000
help
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
- rebase the FSP with the Intel's BCT (tool).
+ rebase the FSP with Intel's BCT (tool).
The Bay Trail FSP is built with a preferred base address of
0xFFFC0000.
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6089
-gerrit
commit 5d83a052fd5cd12b934fd0421c17e9db32b626b6
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Fri Jun 20 21:10:09 2014 -0600
bayleybay_fsp: Add comments for the MMC/SD devices in devicetree
This just adds some additional comments for the EMMC / SD / SDIO PCI
devices in devicetree.
The documentation states that the EMMC 4.1 device shouldn't be used,
but it's available to enable in the FSP. Because it can be enabled,
I've included it in the devicetree even though its use is discouraged.
Change-Id: I64633fe1908368f69a8d4031aa900b0bceb2189e
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/mainboard/intel/bayleybay_fsp/devicetree.cb | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index 66e0e4e..dd6ec93 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -44,14 +44,14 @@ chip soc/intel/fsp_baytrail
device pci 02.0 on end # 8086 0F31 - GFX
device pci 03.0 off end # 8086 0F38 - MIPI - camera interface
- device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port
- device pci 11.0 on end # 8086 0F15 - SDIO Port
- device pci 12.0 on end # 8086 0F16 - SD Port
+ device pci 10.0 off end # 8086 0F14 - EMMC 4.1 Port (MMC1 pins) - (DO NOT USE) - Only 1 EMMC port at a time
+ device pci 11.0 on end # 8086 0F15 - SDIO Port (SD2 pins)
+ device pci 12.0 on end # 8086 0F16 - SD Port (SD3 pins)
device pci 13.0 on end # 8086 0F23 - SATA AHCI (0F20, 0F21, 0F22, 0F23)
device pci 14.0 off end # 8086 0F35 - USB XHCI - Only 1 USB controller at a time
device pci 15.0 off end # 8086 0F28 - LP Engine Audio
device pci 16.0 off end # 8086 0F37 - OTG controller
- device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port
+ device pci 17.0 on end # 8086 0F50 - EMMC 4.5 Port (MMC1 pins) - Only 1 EMMC port at a time
device pci 18.0 on end # 8086 0F40 - SIO - DMA
device pci 18.1 on end # 8086 0F41 - I2C Port 1
device pci 18.2 on end # 8086 0F42 - I2C Port 2
the following patch was just integrated into master:
commit 49380b87d114cf4c1bd6f0692f43e89e73f662b8
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Mon Jun 16 16:48:44 2014 +1000
superio/smsc/fdc37n972: Trivial cleanup reorder headers
Alphabetise headers and a few trivial cleanups.
Change-Id: Ib8c8362962297cb59671d8274df8e4945373f94b
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6042
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
See http://review.coreboot.org/6042 for details.
-gerrit