coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: b45e86f mainboard/jetway/nf81-t56n-lf: Properly indent devicetree.cb
by Edward O'Callaghan 01 May '14

01 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5629 -gerrit commit b45e86f855c579adf20b88061da65c8472399779 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri May 2 03:11:42 2014 +1000 mainboard/jetway/nf81-t56n-lf: Properly indent devicetree.cb Following the reasoning in, dfa8a32 src/mainboard/asrock/e350m1: Properly indent devicetree.cb Change-Id: I88ca01519c1c47a7eb0d564a55c945589f9d32af Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 88 ++++++++++++------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 574bb8a..6c26f75 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -20,7 +20,7 @@ chip northbridge/amd/agesa/family14/root_complex device cpu_cluster 0 on chip cpu/amd/agesa/family14 - device lapic 0 on end + device lapic 0 on end end end device domain 0 on @@ -45,57 +45,57 @@ chip northbridge/amd/agesa/family14/root_complex device pci 13.0 on end # OHCI USB 5-9 device pci 13.2 on end # EHCI USB 5-9 device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71869ad + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f71869ad # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, # see page 18 from Fintek F71869 V1.1 datasheet. - device pnp 2e.00 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.01 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end + device pnp 2e.00 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.01 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end # COM2 not physically wired on board. - device pnp 2e.02 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.03 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.04 on # Hardware Monitor - io 0x60 = 0x225 # Fintek datasheet says 0x295. - irq 0x70 = 0 - end - device pnp 2e.05 on # KBC - io 0x60 = 0x060 - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - end - device pnp 2e.06 off end # GPIO + device pnp 2e.02 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.03 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.04 on # Hardware Monitor + io 0x60 = 0x225 # Fintek datasheet says 0x295. + irq 0x70 = 0 + end + device pnp 2e.05 on # KBC + io 0x60 = 0x060 + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + end + device pnp 2e.06 off end # GPIO # TODO: Verify BSEL register content with vendor BIOS using # $ sudo isadump 0x4e 0x4f 0x7 # which select logical device (LDN) 7. Then read that we have in 0x27, bit1 - device pnp 2e.07 off end # BSEL - device pnp 2e.0a on end # PME - end # f71869ad - end #LPC + device pnp 2e.07 off end # BSEL + device pnp 2e.0a on end # PME + end # f71869ad + end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # OHCI FS/LS USB (0x4399) device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)

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Patch merged into coreboot/master: 04f5c4e Build without ChromeOS
by gerrit＠coreboot.org 01 May '14

01 May '14

the following patch was just integrated into master: commit 04f5c4eca770641ec8e7090e0f0cd41906b94b07 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 16:38:56 2013 +0300 Build without ChromeOS Change-Id: I1da636573eed62ce693b984917084643787c094b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3978 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/3978 for details. -gerrit

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Patch merged into coreboot/master: 6578475 ChromeOS: Use common fill_lb_gpio()
by gerrit＠coreboot.org 01 May '14

01 May '14

the following patch was just integrated into master: commit 6578475d93c2584942bf58601ee0b07fd925838b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 03:12:38 2013 +0200 ChromeOS: Use common fill_lb_gpio() Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5586 for details. -gerrit

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Patch merged into coreboot/master: 9ab1c10 device: Conditionally bypass oprom execution
by gerrit＠coreboot.org 01 May '14

01 May '14

the following patch was just integrated into master: commit 9ab1c106c3ec88adfefc0dfe237e538e33f2750d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 00:22:49 2013 +0200 device: Conditionally bypass oprom execution Builds with CHROMEOS can bypass VGA oprom when boot is not in developer or recovery modes. Have the same functionality available without CHROMEOS but with BOOTMODE_STRAPS. Change-Id: I97644364305dc05aad78a744599476ccc58db163 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5595 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/5595 for details. -gerrit

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Patch merged into coreboot/master: ab56b3b ChromeOS: Remove oprom_is_loaded
by gerrit＠coreboot.org 01 May '14

01 May '14

the following patch was just integrated into master: commit ab56b3b11c34b5315fadc2147f5d1a860dccc419 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Nov 28 16:44:51 2013 +0200 ChromeOS: Remove oprom_is_loaded A global flag oprom_is_loaded was used to indicate to U-boot that VGA option ROM was loaded and run, or that native VGA init was completed on GMA device. Implement this feature without dependency to CHROMEOS option and replace use of global variable oprom_is_loaded with call to gfx_get_init_done(). Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/4309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/4309 for details. -gerrit

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Patch merged into coreboot/master: 926a8d1 google/stout: Fix build without ChromeOS
by gerrit＠coreboot.org 01 May '14

01 May '14

the following patch was just integrated into master: commit 926a8d1262c09fda9868f73cf0241140ccf09ec9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Apr 27 22:17:22 2014 +0300 google/stout: Fix build without ChromeOS Currently we have no developer or recovery mode switches when building without ChromeOS. Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5596 for details. -gerrit

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Patch merged into coreboot/master: 5687fc9 Declare recovery and developer modes outside ChromeOS
by gerrit＠coreboot.org 01 May '14

01 May '14

the following patch was just integrated into master: commit 5687fc9d2120c01b929f24df07667f87089f9b5f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Nov 28 18:11:49 2013 +0200 Declare recovery and developer modes outside ChromeOS Move the implementation for recovery and developer modes from vendorcode/google/chromes to lib/. Change-Id: I33335fb282de2c7bc613dc58d6912c47f3b5c06c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/4308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/4308 for details. -gerrit

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Patch merged into coreboot/master: 580e564 device: provide option to always load PCI option roms
by gerrit＠coreboot.org 01 May '14

01 May '14

the following patch was just integrated into master: commit 580e5642a8d1db1bc85c5d55dc2227f3fda8eb34 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu May 1 16:31:34 2014 +0300 device: provide option to always load PCI option roms Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5594 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5594 for details. -gerrit

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Patch set updated for coreboot: 5610ed8 device: provide option to always load PCI option roms
by Kyösti Mälkki 01 May '14

01 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5594 -gerrit commit 5610ed833fc43cff13dd7b193f60e29bbac3f130 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu May 1 16:31:34 2014 +0300 device: provide option to always load PCI option roms Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Kconfig | 12 ++++++++++++ src/device/pci_device.c | 50 +++++++++++++++++++++++++++++++++++++++---------- 2 files changed, 52 insertions(+), 10 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 932b4de..ab7a577 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -70,6 +70,18 @@ config S3_VGA_ROM_RUN If unsure, say N when using SeaBIOS as payload, Y otherwise. +config ALWAYS_LOAD_OPROM + def_bool n + depends on VGA_ROM_RUN + help + Always load option roms if any are found. The decision to run + the rom is still determined at runtime, but the distinction + between loading and not running comes into play for CHROMEOS. + + An example where this is required is that VBT (video bios tables) + are needed for the kernel's display driver to know how a piece of + hardware is configured to be used. + config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS diff --git a/src/device/pci_device.c b/src/device/pci_device.c index aa0d954..ca36046 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -23,6 +23,7 @@ * Copyright 1997 -- 1999 Martin Mares <mj(a)atrey.karlin.mff.cuni.cz> */ +#include <kconfig.h> #include <console/console.h> #include <stdlib.h> #include <stdint.h> @@ -663,15 +664,13 @@ void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device) int oprom_is_loaded = 0; #endif -/** Default handler: only runs the relevant PCI BIOS. */ -void pci_dev_init(struct device *dev) -{ #if CONFIG_VGA_ROM_RUN - struct rom_header *rom, *ram; +static int should_run_oprom(struct device *dev) +{ + static int should_run = -1; - /* Only execute VGA ROMs. */ - if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) - return; + if (should_run >= 0) + return should_run; #if CONFIG_CHROMEOS /* In ChromeOS we want to boot blazingly fast. Therefore @@ -680,19 +679,47 @@ void pci_dev_init(struct device *dev) */ if (!developer_mode_enabled() && !recovery_mode_enabled() && !vboot_wants_oprom()) { - printk(BIOS_DEBUG, "Not loading VGA Option ROM\n"); - return; + printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); + should_run = 0; + return should_run; } #endif + should_run = 1; + + return should_run; +} +static int should_load_oprom(struct device *dev) +{ #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN /* If S3_VGA_ROM_RUN is disabled, skip running VGA option * ROMs when coming out of an S3 resume. */ if ((acpi_slp_type == 3) && ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)) - return; + return 0; #endif + if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) + return 1; + if (should_run_oprom(dev)) + return 1; + + return 0; +} +#endif /* CONFIG_VGA_ROM_RUN */ + +/** Default handler: only runs the relevant PCI BIOS. */ +void pci_dev_init(struct device *dev) +{ +#if CONFIG_VGA_ROM_RUN + struct rom_header *rom, *ram; + + /* Only execute VGA ROMs. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return; + + if (!should_load_oprom(dev)) + return; rom = pci_rom_probe(dev); if (rom == NULL) @@ -702,6 +729,9 @@ void pci_dev_init(struct device *dev) if (ram == NULL) return; + if (!should_run_oprom(dev)) + return; + run_bios(dev, (unsigned long)ram); #if CONFIG_CHROMEOS oprom_is_loaded = 1;

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Patch set updated for coreboot: 28e7780 AMD F14h boards: Sanitise headers in agesawrapper.c
by Edward O'Callaghan 01 May '14

01 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5628 -gerrit commit 28e77800c234eee4806bacdd2cd70963e73177f4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 1 22:41:12 2014 +1000 AMD F14h boards: Sanitise headers in agesawrapper.c Change-Id: Ic9c5e8abb3da020a642635ee74c9242091923619 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/persimmon/agesawrapper.c | 35 +++++++--------------- src/mainboard/gizmosphere/gizmo/agesawrapper.c | 35 +++++++--------------- .../lippert/frontrunner-af/agesawrapper.c | 35 +++++++--------------- src/mainboard/lippert/toucan-af/agesawrapper.c | 35 +++++++--------------- 4 files changed, 44 insertions(+), 96 deletions(-) diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 462e825..cf8534e 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -17,37 +17,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*----------------------------------------------------------------------------- - * M O D U L E S U S E D - *----------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#define __SIMPLE_DEVICE__ + +#include <arch/acpi.h> #include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> -#include <arch/acpi.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> -#define FILECODE UNASSIGNED_FILE_FILECODE +#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> -/*------------------------------------------------------------------------------ - * D E F I N I T I O N S A N D M A C R O S - *------------------------------------------------------------------------------ - */ +#define FILECODE UNASSIGNED_FILE_FILECODE #define MMCONF_ENABLE 1 diff --git a/src/mainboard/gizmosphere/gizmo/agesawrapper.c b/src/mainboard/gizmosphere/gizmo/agesawrapper.c index e9d1874..04c4dd6 100755 --- a/src/mainboard/gizmosphere/gizmo/agesawrapper.c +++ b/src/mainboard/gizmosphere/gizmo/agesawrapper.c @@ -18,37 +18,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*----------------------------------------------------------------------------- - * M O D U L E S U S E D - *----------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#define __SIMPLE_DEVICE__ + +#include <arch/acpi.h> #include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> -#include <arch/acpi.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> -#define FILECODE UNASSIGNED_FILE_FILECODE +#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> -/*------------------------------------------------------------------------------ - * D E F I N I T I O N S A N D M A C R O S - *------------------------------------------------------------------------------ - */ +#define FILECODE UNASSIGNED_FILE_FILECODE #define MMCONF_ENABLE 1 diff --git a/src/mainboard/lippert/frontrunner-af/agesawrapper.c b/src/mainboard/lippert/frontrunner-af/agesawrapper.c index 462e825..cf8534e 100644 --- a/src/mainboard/lippert/frontrunner-af/agesawrapper.c +++ b/src/mainboard/lippert/frontrunner-af/agesawrapper.c @@ -17,37 +17,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*----------------------------------------------------------------------------- - * M O D U L E S U S E D - *----------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#define __SIMPLE_DEVICE__ + +#include <arch/acpi.h> #include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> -#include <arch/acpi.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> -#define FILECODE UNASSIGNED_FILE_FILECODE +#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> -/*------------------------------------------------------------------------------ - * D E F I N I T I O N S A N D M A C R O S - *------------------------------------------------------------------------------ - */ +#define FILECODE UNASSIGNED_FILE_FILECODE #define MMCONF_ENABLE 1 diff --git a/src/mainboard/lippert/toucan-af/agesawrapper.c b/src/mainboard/lippert/toucan-af/agesawrapper.c index 462e825..cf8534e 100644 --- a/src/mainboard/lippert/toucan-af/agesawrapper.c +++ b/src/mainboard/lippert/toucan-af/agesawrapper.c @@ -17,37 +17,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/*----------------------------------------------------------------------------- - * M O D U L E S U S E D - *----------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> #include "agesawrapper.h" #include "BiosCallOuts.h" -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "heapManager.h" -#include "amdlib.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" + +#define __SIMPLE_DEVICE__ + +#include <arch/acpi.h> #include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> #include <cbmem.h> -#include <arch/acpi.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> -#define FILECODE UNASSIGNED_FILE_FILECODE +#include <cpu/amd/agesa/s3_resume.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> -/*------------------------------------------------------------------------------ - * D E F I N I T I O N S A N D M A C R O S - *------------------------------------------------------------------------------ - */ +#define FILECODE UNASSIGNED_FILE_FILECODE #define MMCONF_ENABLE 1

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coreboot-gerrit May 2014