coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: b4bd53a tegra124: Active dc/sor register change immediately
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit b4bd53a3cba45b2cbf86b8b020bb8a678e583f97 Author: Vince Hsu <vinceh(a)nvidia.com> Date: Fri May 16 18:07:53 2014 +0800 tegra124: Active dc/sor register change immediately When doing DP attach, we need to make sure the register change to take effect immediately, otherwise it may fail to catch the attach timing. BRANCH=None BUG=chrome-os-partner:28128 TEST=Display works and system boots up on Nyan and Big Original-Change-Id: I569dc435a1aa4aac0d5ecd0655d2ad87a791246d Original-Signed-off-by: Vince Hsu <vinceh(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/200414 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 47b86e2893fa667bebada6a0e0b443886dd5ee02) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icf809b46e675bbdb8633d9a4f31d005d6644bd2a Reviewed-on: http://review.coreboot.org/7951 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/7951 for details. -gerrit

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Patch merged into coreboot/master: c09642e tegra124: display clock should be initialized before any access
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit c09642e31560b63c643f4ca5a7710057b23106cd Author: Vince Hsu <vinceh(a)nvidia.com> Date: Fri May 16 12:46:02 2014 +0800 tegra124: display clock should be initialized before any access We initialized the dc before the plld's initialization. So some of the dc init settings did not took effect. This patch moves the clock_display() before the dc init call. BRANCH=None BUG=chrome-os-partner:28128 TEST=Display works and system boots up on Nyan and Big Original-Change-Id: If2c40e2526fdf7a6aa33a2684ba324bd0ec40e90 Original-Signed-off-by: Vince Hsu <vinceh(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/200413 Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit dc3cc253c319c21772c30962d963ec9dfc4944a7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I021290f4293c740666d460f73fecbe79146896a4 Reviewed-on: http://review.coreboot.org/7950 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/7950 for details. -gerrit

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Patch merged into coreboot/master: d72d8aa nyan*: Log boot reason in eventlog
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit d72d8aa9523fae880a3be6b64ae8bcddb88fbcd3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue May 13 20:32:14 2014 -0700 nyan*: Log boot reason in eventlog BUG=none BRANCH=nyan TEST=built and booted on Big under various modes, verified that expected boot mode showed up using "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I8d98487a2cb910874c8d741008ae59a6c89102e7 Original-Reviewed-on: https://chromium-review.googlesource.com/199691 Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 9f4b2574c1af23dcdc01706e9a118441f46a0f97) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ibbf264a1e05323dfddb7cdb270ee6f2d49e83eff Reviewed-on: http://review.coreboot.org/7946 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7946 for details. -gerrit

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Patch merged into coreboot/master: d0d57a7 nyan*: Add an empty elog functions for the !CONFIG_ELOG case
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit d0d57a7460bf40f96818b064ca4cd9b687c58b4c Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu May 8 20:04:02 2014 -0700 nyan*: Add an empty elog functions for the !CONFIG_ELOG case Provide elog stub functions so eventlog support can be omitted without littering code with "#if CONFIG_ELOG". This makes it so coreboot can be built without eventlog support for these platforms for debugging purposes. BUG=none BRANCH=none TEST=compiled for Nyan and Rambi with CONFIG_ELOG unset Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Ibf56d29a09234068773378f99ad9bffd5480dc9c Original-Reviewed-on: https://chromium-review.googlesource.com/198647 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 8e83dd460647972c4f46c19f8dc3d3ad7baeb550) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I3c0803ceb7a1c06da717416c42b6b7730c029ed0 Reviewed-on: http://review.coreboot.org/7901 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/7901 for details. -gerrit

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Patch merged into coreboot/master: 7086ea9 libpayload: fix printf handling of unsigned long long
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit 7086ea920d4181f1d4927e9f150a3976c7a8f3a7 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Dec 29 19:53:51 2014 +0100 libpayload: fix printf handling of unsigned long long 1 << 63 is undefined for 32bit numbers. Change-Id: I22f0e2486b133ea18cfbb8dd79fd4aed91ac0a4c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/7972 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7972 for details. -gerrit

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Patch merged into coreboot/master: bcf07c3 libpayload: don't dereference null pointer in exception handler
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit bcf07c3f24e949b6a16f69ca5d21c5ecb1c9056e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Dec 29 19:34:56 2014 +0100 libpayload: don't dereference null pointer in exception handler Change-Id: I93e5e2488ddd616c91769beb1acd96f8ebd7d505 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/7971 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7971 for details. -gerrit

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Patch merged into coreboot/master: 8229244 libpayload: Add missing break statement
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit 82292441c7ffe941b4722bbcbac958face576ad4 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Dec 29 19:31:35 2014 +0100 libpayload: Add missing break statement Change-Id: I073b9bd30f4f9b0cdf6c45c10e4549889342d5f3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/7970 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7970 for details. -gerrit

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Patch merged into coreboot/master: f4c86b0 libpayload: Remove useless continue after return
by gerrit＠coreboot.org 30 Dec '14

30 Dec '14

the following patch was just integrated into master: commit f4c86b0159dedfd1ec90b69a76950a071f0da949 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Dec 29 19:30:37 2014 +0100 libpayload: Remove useless continue after return Change-Id: I7209ceaf4ad686bbb07eb0c6105f77834d5511fd Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Found-by: Coverity Scan Reviewed-on: http://review.coreboot.org/7969 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7969 for details. -gerrit

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Patch set updated for coreboot: 6b905a7 CBMEM: Always use DYNAMIC_CBMEM
by Kyösti Mälkki 30 Dec '14

30 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7851 -gerrit commit 6b905a753217583a6816234390a8ed22b2eac692 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 28 11:24:19 2014 +0200 CBMEM: Always use DYNAMIC_CBMEM Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- 3rdparty | 2 +- src/Kconfig | 10 +- src/arch/x86/boot/cbmem.c | 20 -- src/arch/x86/boot/tables.c | 9 +- src/cpu/allwinner/a10/Kconfig | 1 - src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/haswell/romstage.c | 5 +- src/cpu/ti/am335x/Kconfig | 1 - src/include/cbmem.h | 31 --- src/include/rmodule.h | 2 - src/lib/Makefile.inc | 6 - src/lib/cbmem.c | 288 ---------------------- src/lib/rmodule.c | 8 +- src/mainboard/emulation/qemu-armv7/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 - src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 1 - src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/nehalem/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 4 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 2 - src/soc/nvidia/tegra124/Kconfig | 1 - src/soc/qualcomm/ipq806x/Kconfig | 1 - src/soc/samsung/exynos5250/Kconfig | 1 - src/soc/samsung/exynos5420/Kconfig | 1 - src/soc/ucb/riscv/Kconfig | 1 - 32 files changed, 6 insertions(+), 404 deletions(-) diff --git a/3rdparty b/3rdparty index a8b0c52..9f68e20 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit a8b0c52850495c30dfa1cd8cc2c679a6ba4e18ac +Subproject commit 9f68e20e5ef4b6681fb18bdb4022471bc6810788 diff --git a/src/Kconfig b/src/Kconfig index 73cd803..fd9ceca 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,14 +159,6 @@ config INCLUDE_CONFIG_FILE config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT -config DYNAMIC_CBMEM - bool - default n - help - Instead of reserving a static amount of CBMEM space the CBMEM - area grows dynamically. CBMEM can be used both in romstage (after - memory initialization) and ramstage. - config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" default n @@ -200,7 +192,7 @@ config RELOCATABLE_MODULES loaded anywhere and all the relocations are handled automatically. config RELOCATABLE_RAMSTAGE - depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM && EARLY_CBMEM_INIT) + depends on (RELOCATABLE_MODULES && EARLY_CBMEM_INIT) bool "Build the ramstage to be relocatable in 32-bit address space." default n help diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index fe34471..49dd02b 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -23,20 +23,6 @@ #include <arch/acpi.h> #include <arch/early_variables.h> -#if !CONFIG_DYNAMIC_CBMEM -void get_cbmem_table(uint64_t *base, uint64_t *size) -{ - uint64_t top_of_ram = get_top_of_ram(); - - if (top_of_ram >= HIGH_MEMORY_SIZE) { - *base = top_of_ram - HIGH_MEMORY_SIZE; - *size = HIGH_MEMORY_SIZE; - } else { - *base = 0; - *size = 0; - } -} -#endif /* !DYNAMIC_CBMEM */ #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) @@ -49,11 +35,7 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); -#if !CONFIG_DYNAMIC_CBMEM - cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); -#else cbmem_set_top((void*)(uintptr_t)ramtop); -#endif } #endif /* !__PRE_RAM__ */ @@ -63,13 +45,11 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) return 0; } -#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ return (void *)get_top_of_ram(); } -#endif #endif /* LATE_CBMEM_INIT */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index c2265ea..712f66f 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -101,11 +101,8 @@ void write_tables(void) #endif /* CONFIG_GENERATE_MP_TABLE */ #if CONFIG_HAVE_ACPI_TABLES -#if CONFIG_DYNAMIC_CBMEM #define MAX_ACPI_SIZE (144 * 1024) -#else -#define MAX_ACPI_SIZE (45 * 1024) -#endif + post_code(0x9c); /* Write ACPI tables to F segment and high tables area */ @@ -199,11 +196,7 @@ void write_tables(void) /* FIXME: The high_table_base parameter is not reference when tables are high, * or high_table_pointer >1 MB. */ -#if CONFIG_DYNAMIC_CBMEM u64 fixme_high_tables_base = 0; -#else - u64 fixme_high_tables_base = (u32)get_cbmem_toc(); -#endif /* Also put a forwarder entry into 0-4K */ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index b7b435f..2bf32ec 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT - select DYNAMIC_CBMEM # The "eGON.BT0" header takes 32 bytes config BOOTBLOCK_BASE diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 9b0edfc..e9cbe43 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE - select DYNAMIC_CBMEM config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 2f891ad..5cd4c65 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE - select DYNAMIC_CBMEM choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 0597363..37ae5b3 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS select SMM_MODULES select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE - select DYNAMIC_CBMEM select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1af5259..50150cf 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -75,14 +75,11 @@ static inline u32 *stack_push(u32 *stack, u32 value) static unsigned long choose_top_of_stack(void) { unsigned long stack_top; -#if CONFIG_DYNAMIC_CBMEM + /* cbmem_add() does a find() before add(). */ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, ROMSTAGE_RAM_STACK_SIZE); stack_top += ROMSTAGE_RAM_STACK_SIZE; -#else - stack_top = CONFIG_RAMTOP; -#endif return stack_top; } diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index eb60ad1..fae527d 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -6,7 +6,6 @@ config CPU_TI_AM335X select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT - select DYNAMIC_CBMEM bool default n diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b1f3b5e..ea81fd0 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -118,8 +118,6 @@ struct cbmem_id_to_name { struct cbmem_entry; -#if CONFIG_DYNAMIC_CBMEM - /* * The dynamic cbmem infrastructure allows for growing cbmem dynamically as * things are added. It requires an external function, cbmem_top(), to be @@ -171,35 +169,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); -#else /* !CONFIG_DYNAMIC_CBMEM */ - -/* Allocation with static CBMEM is resolved at build time. We start - * with 128kB and conditionally add some of the most greedy CBMEM - * table entries. - */ -#define _CBMEM_SZ_MINIMAL ( 128 * 1024 ) - -#define _CBMEM_SZ_TOTAL \ - (_CBMEM_SZ_MINIMAL + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE + \ - HIGH_MEMORY_SAVE + HIGH_MEMORY_SCRATCH) - -#define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000) - -#ifndef __PRE_RAM__ -void cbmem_late_set_table(uint64_t base, uint64_t size); -#endif - -void get_cbmem_table(uint64_t *base, uint64_t *size); -struct cbmem_entry *get_cbmem_toc(void); - -static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) -{ - return NULL; -} -#endif /* CONFIG_DYNAMIC_CBMEM */ - -/* Common API between cbmem and dynamic cbmem. */ - /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ int cbmem_recovery(int s3resume); diff --git a/src/include/rmodule.h b/src/include/rmodule.h index d229cf8..76b855a 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -54,7 +54,6 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, /* Support for loading rmodule stages. This API is only available when * using dynamic cbmem because it uses the dynamic cbmem API to obtain * the backing store region for the stage. */ -#if CONFIG_DYNAMIC_CBMEM struct cbfs_stage; struct cbmem_entry; @@ -70,7 +69,6 @@ struct rmod_stage_load { /* Both of the following functions return 0 on success, -1 on error. */ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage); int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl); -#endif struct rmodule { void *location; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 6c79006..5a5ccc2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -74,14 +74,8 @@ ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -# The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM. -ifeq ($(CONFIG_DYNAMIC_CBMEM),y) ramstage-y += dynamic_cbmem.c romstage-y += dynamic_cbmem.c -else -ramstage-y += cbmem.c -romstage-y += cbmem.c -endif # CONFIG_DYNAMIC_CBMEM ramstage-y += cbmem_info.c ramstage-y += hexdump.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c deleted file mode 100644 index 5ea8d88..0000000 --- a/src/lib/cbmem.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <bootmem.h> -#include <bootstate.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/early_variables.h> -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) -#include <arch/acpi.h> -#endif - -// The CBMEM TOC reserves 512 bytes to keep -// the other entries somewhat aligned. -// Increase if MAX_CBMEM_ENTRIES exceeds 21 -#define CBMEM_TOC_RESERVED 512 -#define MAX_CBMEM_ENTRIES 16 -#define CBMEM_MAGIC 0x434f5245 - -struct cbmem_entry { - u32 magic; - u32 id; - u64 base; - u64 size; -} __attribute__((packed)); - -#ifndef __PRE_RAM__ -static uint64_t cbmem_base = 0; -static uint64_t cbmem_size = 0; -#endif - -static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) -{ - if (base && size && s) { - printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", - base, base + size - 1, s); - } -} - -static void cbmem_locate_table(uint64_t *base, uint64_t *size) -{ -#ifdef __PRE_RAM__ - get_cbmem_table(base, size); -#else - if (!(cbmem_base && cbmem_size)) { - get_cbmem_table(&cbmem_base, &cbmem_size); - cbmem_trace_location(cbmem_base, cbmem_size, __FUNCTION__); - } - *base = cbmem_base; - *size = cbmem_size; -#endif -} - -struct cbmem_entry *get_cbmem_toc(void) -{ - uint64_t base, size; - cbmem_locate_table(&base, &size); - return (struct cbmem_entry *)(unsigned long)base; -} - -#if !defined(__PRE_RAM__) -void cbmem_late_set_table(uint64_t base, uint64_t size) -{ - cbmem_trace_location(base, size, __FUNCTION__); - cbmem_base = base; - cbmem_size = size; -} -#endif - -/** - * cbmem is a simple mechanism to do some kind of book keeping of the coreboot - * high tables memory. This is a small amount of memory which is "stolen" from - * the system memory for coreboot purposes. Usually this memory is used for - * - the coreboot table - * - legacy tables (PIRQ, MP table) - * - ACPI tables - * - suspend/resume backup memory - */ - -static void cbmem_initialize_empty(void) -{ - uint64_t baseaddr, size; - struct cbmem_entry *cbmem_toc; - - cbmem_locate_table(&baseaddr, &size); - cbmem_trace_location(baseaddr, size, __FUNCTION__); - - if (!(baseaddr && size)) { - printk(BIOS_CRIT, "Unable to set location for CBMEM.\n"); - return; - } - - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); - - cbmem_toc[0] = (struct cbmem_entry) { - .magic = CBMEM_MAGIC, - .id = CBMEM_ID_FREESPACE, - .base = baseaddr + CBMEM_TOC_RESERVED, - .size = size - CBMEM_TOC_RESERVED - }; -} - -static int cbmem_check_toc(void) -{ - uint64_t baseaddr, size; - struct cbmem_entry *cbmem_toc; - - cbmem_locate_table(&baseaddr, &size); - cbmem_trace_location(baseaddr, size, __FUNCTION__); - - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - - return (cbmem_toc[0].magic == CBMEM_MAGIC); -} - -void *cbmem_add(u32 id, u64 size) -{ - struct cbmem_entry *cbmem_toc; - int i; - void *p; - - /* - * This could be a restart, check if the section is there already. It - * is remotely possible that the dram contents persisted over the - * bootloader upgrade AND the same section now needs more room, but - * this is quite a remote possibility and it is ignored here. - */ - p = cbmem_find(id); - if (p) { - printk(BIOS_NOTICE, - "CBMEM section %x: using existing location at %p.\n", - id, p); - return p; - } - - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) { - return NULL; - } - - if (cbmem_toc[0].magic != CBMEM_MAGIC) { - printk(BIOS_ERR, "ERROR: CBMEM was not initialized yet.\n"); - return NULL; - } - - /* Will the entry fit at all? */ - if (size > cbmem_toc[0].size) { - printk(BIOS_ERR, "ERROR: Not enough memory for table %x\n", id); - return NULL; - } - - /* Align size to 512 byte blocks */ - - size = ALIGN(size, 512) < cbmem_toc[0].size ? - ALIGN(size, 512) : cbmem_toc[0].size; - - /* Now look for the first free/usable TOC entry */ - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - if (cbmem_toc[i].id == CBMEM_ID_NONE) - break; - } - - if (i >= MAX_CBMEM_ENTRIES) { - printk(BIOS_ERR, "ERROR: No more CBMEM entries available.\n"); - return NULL; - } - - printk(BIOS_DEBUG, "Adding CBMEM entry as no. %d\n", i); - - cbmem_toc[i] = (struct cbmem_entry) { - .magic = CBMEM_MAGIC, - .id = id, - .base = cbmem_toc[0].base, - .size = size - }; - - cbmem_toc[0].base += size; - cbmem_toc[0].size -= size; - - return (void *)(uintptr_t)cbmem_toc[i].base; -} - -void *cbmem_find(u32 id) -{ - struct cbmem_entry *cbmem_toc; - int i; - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) - return NULL; - - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - if (cbmem_toc[i].id == id) - return (void *)(unsigned long)cbmem_toc[i].base; - } - - return (void *)NULL; -} - -/* Returns True if it was not initialized before. */ -int cbmem_recovery(int is_wakeup) -{ - int found = cbmem_check_toc(); - int wipe = 0; - - /* CBMEM TOC is wiped clean when we are not waking up from S3 - * suspend. Boards with EARLY_CBMEM_INIT do this in romstage, - * boards without EARLY_CBMEM_INIT do this in ramstage. - */ -#if defined(__PRE_RAM__) && CONFIG_EARLY_CBMEM_INIT - wipe = 1; -#endif -#if !defined(__PRE_RAM__) && !CONFIG_EARLY_CBMEM_INIT - wipe = 1; -#endif - - if (!is_wakeup && wipe) - cbmem_initialize_empty(); - - if (is_wakeup && !found) { - cbmem_initialize_empty(); - cbmem_fail_resume(); - } - - /* Complete migration to CBMEM. */ - cbmem_arch_init(); - - return !found; -} - -#ifndef __PRE_RAM__ -static void init_cbmem_post_device(void *unused) -{ -#if CONFIG_HAVE_ACPI_RESUME - cbmem_recovery(acpi_is_wakeup()); -#else - cbmem_recovery(0); -#endif -} - -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), -}; - -void cbmem_add_bootmem(void) -{ - bootmem_add_range(cbmem_base, cbmem_size, LB_MEM_TABLE); -} - -void cbmem_list(void) -{ - struct cbmem_entry *cbmem_toc; - int i; - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) - return; - - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - - if (cbmem_toc[i].magic != CBMEM_MAGIC) - continue; - cbmem_print_entry(i, cbmem_toc[i].id, cbmem_toc[i].base, - cbmem_toc[i].size); - } -} -#endif diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 908297b..5c6df02 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <assert.h> +#include <cbmem.h> +#include <cbfs_core.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -249,10 +251,6 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, return region_alignment - sizeof(struct rmodule_header); } -#if CONFIG_DYNAMIC_CBMEM -#include <cbmem.h> -#include <cbfs_core.h> - int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) { struct rmodule rmod_stage; @@ -307,5 +305,3 @@ int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl) return rmodule_stage_load(rsl, stage); } - -#endif /* DYNAMIC_CBMEM */ diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 7e24a20..b275e88 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARM_ROMSTAGE_ARMV7 select ARM_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 - select DYNAMIC_CBMEM config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index b002c21..406612e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select DYNAMIC_CBMEM select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 4931523..08d563f 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -130,10 +130,6 @@ static void cpu_pci_domain_read_resources(struct device *dev) "debugcon"); } -#if !CONFIG_DYNAMIC_CBMEM - set_top_of_ram(tomk * 1024); -#endif - if (q35 && ((tomk * 1024) < 0xb0000000)) { /* * Reserve the region between top-of-ram and the diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3949937..fcc750c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select DYNAMIC_CBMEM select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index fa08acc..a804fd3 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select DYNAMIC_CBMEM select INTEL_INT15 select VGA select INTEL_EDID diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index fac7329..096c80f 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_DEBUG_RAM_SETUP select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select IOMMU select VGA select INTEL_EDID diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index c578011..8a0cb5b 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select VGA diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index b49f331..ca5ffa5 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_INTEL_NEHALEM select CPU_INTEL_MODEL_2065X select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select VGA select INTEL_EDID select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 647b4fb..11370f5 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select PER_DEVICE_ACPI_TABLES @@ -31,7 +30,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES @@ -41,7 +39,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select PER_DEVICE_ACPI_TABLES @@ -50,7 +47,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index bcaa1ff..28dc7d7 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS - select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 019bed3..11e8429 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS - select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b61fac3..081ea09 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -30,8 +30,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select DYNAMIC_CBMEM - select BROKEN_CAR_MIGRATE select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 195261e..89d07c5 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA124 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE - select DYNAMIC_CBMEM select ARM_BOOTBLOCK_CUSTOM select ARM_LPAE diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index a6ddf81..0fb780c 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -2,7 +2,6 @@ config SOC_QC_IPQ806X select ARCH_BOOTBLOCK_ARMV4 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 8d7c867..9cbd37f 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -5,7 +5,6 @@ config CPU_SAMSUNG_EXYNOS5250 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 904091e..c9f2ec6 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -6,7 +6,6 @@ config CPU_SAMSUNG_EXYNOS5420 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select RELOCATABLE_MODULES - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index be4a675..d1e4ba7 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -3,7 +3,6 @@ config SOC_UCB_RISCV select ARCH_BOOTBLOCK_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV - select DYNAMIC_CBMEM bool default n

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Patch set updated for coreboot: 016dc4d CBMEM: Tag chipsets with LATE_CBMEM_INIT
by Kyösti Mälkki 30 Dec '14

30 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7850 -gerrit commit 016dc4dd465ff33d3e2cec4ed61fe0c29a09057a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 18 22:22:04 2014 +0200 CBMEM: Tag chipsets with LATE_CBMEM_INIT In preparation to remove the static CBMEM allocator, tag the chipsets that still do not implement get_top_of_ram() for romstage. LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE. Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 15 ++++++++------- src/arch/x86/boot/cbmem.c | 2 +- src/northbridge/amd/agesa/Kconfig | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 + src/northbridge/amd/amdk8/Kconfig | 1 + src/northbridge/amd/gx2/Kconfig | 1 + src/northbridge/amd/lx/Kconfig | 1 + src/northbridge/amd/pi/Kconfig | 1 + src/northbridge/dmp/vortex86ex/Kconfig | 1 + src/northbridge/intel/e7501/Kconfig | 1 + src/northbridge/intel/e7505/Kconfig | 1 + src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/i440bx/Kconfig | 1 + src/northbridge/intel/i440lx/Kconfig | 1 + src/northbridge/intel/i5000/Kconfig | 1 + src/northbridge/intel/i82810/Kconfig | 1 + src/northbridge/intel/i82830/Kconfig | 1 + src/northbridge/intel/i855/Kconfig | 1 + src/northbridge/intel/sch/Kconfig | 1 + src/northbridge/rdc/r8610/Kconfig | 1 + src/northbridge/via/cn700/Kconfig | 1 + src/northbridge/via/cx700/Kconfig | 1 + src/northbridge/via/vx800/Kconfig | 1 + src/northbridge/via/vx900/Kconfig | 1 + 24 files changed, 31 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 30961a4..c9a04a4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -157,16 +157,17 @@ config INCLUDE_CONFIG_FILE (empty) 0x8e480 null 3610440 config EARLY_CBMEM_INIT - bool - default n + def_bool !LATE_CBMEM_INIT + +config LATE_CBMEM_INIT + def_bool n help - Make coreboot initialize the CBMEM structures while running in ROM - stage. This is useful when the ROM stage wants to communicate - some, for instance, execution timestamps. It needs support in - romstage.c and should be enabled by the board's Kconfig. + Enable this in chipset's Kconfig if northbridge does not implement + early get_top_of_ram() call for romstage. CBMEM tables will be + allocated late in ramstage, after PCI devices resources are known. config BROKEN_CAR_MIGRATE - def_bool !EARLY_CBMEM_INIT + def_bool LATE_CBMEM_INIT help Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and manage CAR migration on S3 resume path only. Couple boards use diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 857d43f..7cd0c7b 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -53,7 +53,7 @@ void set_top_of_ram(uint64_t ramtop) } #endif /* !__PRE_RAM__ */ -#if CONFIG_BROKEN_CAR_MIGRATE || !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 68551fb..8fd8bfd 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 0789ac3..13b912e 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 8bee5ca..65dc173 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -24,6 +24,7 @@ config NORTHBRIDGE_AMD_AMDK8 select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDK8 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/gx2/Kconfig b/src/northbridge/amd/gx2/Kconfig index dc347c4..1fe33f8 100644 --- a/src/northbridge/amd/gx2/Kconfig +++ b/src/northbridge/amd/gx2/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_GX2 bool select GEODE_VSA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_GX2 diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index d74d715..abc3e4c 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_LX diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 8af4872..2b8e356 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_PI bool default CPU_AMD_PI + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/dmp/vortex86ex/Kconfig b/src/northbridge/dmp/vortex86ex/Kconfig index 7bf5235..74239ad 100644 --- a/src/northbridge/dmp/vortex86ex/Kconfig +++ b/src/northbridge/dmp/vortex86ex/Kconfig @@ -19,3 +19,4 @@ config NORTHBRIDGE_DMP_VORTEX86EX bool + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/e7501/Kconfig b/src/northbridge/intel/e7501/Kconfig index 88c0b45..763b96e 100644 --- a/src/northbridge/intel/e7501/Kconfig +++ b/src/northbridge/intel/e7501/Kconfig @@ -2,4 +2,5 @@ config NORTHBRIDGE_INTEL_E7501 bool select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index ff7f5a5..e755852 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT config HW_SCRUBBER bool diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 079004b..cb0bd38 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I3100 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_I3100 config DIMM_MAP_LOGICAL diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 902eb73..c5cc43e 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_INTEL_I440BX bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT config SDRAMPWR_4DIMM bool diff --git a/src/northbridge/intel/i440lx/Kconfig b/src/northbridge/intel/i440lx/Kconfig index a88a7a1..1ccaac6 100644 --- a/src/northbridge/intel/i440lx/Kconfig +++ b/src/northbridge/intel/i440lx/Kconfig @@ -20,4 +20,5 @@ config NORTHBRIDGE_INTEL_I440LX bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index f7344ca..3bd685a 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_I5000 select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_I5000 diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig index 79fe36a..723f751 100644 --- a/src/northbridge/intel/i82810/Kconfig +++ b/src/northbridge/intel/i82810/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_INTEL_I82810 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig index 20b31a2..662840f 100644 --- a/src/northbridge/intel/i82830/Kconfig +++ b/src/northbridge/intel/i82830/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_INTEL_I82830 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig index f5c2890..44becf6 100644 --- a/src/northbridge/intel/i855/Kconfig +++ b/src/northbridge/intel/i855/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_INTEL_I855 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig index b8dad72..f495e6a 100644 --- a/src/northbridge/intel/sch/Kconfig +++ b/src/northbridge/intel/sch/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_SCH bool select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_SCH diff --git a/src/northbridge/rdc/r8610/Kconfig b/src/northbridge/rdc/r8610/Kconfig index 85461b7..e93a3e6 100644 --- a/src/northbridge/rdc/r8610/Kconfig +++ b/src/northbridge/rdc/r8610/Kconfig @@ -1,2 +1,3 @@ config NORTHBRIDGE_RDC_R8610 bool + select LATE_CBMEM_INIT diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig index 34c330e..15c86eb 100644 --- a/src/northbridge/via/cn700/Kconfig +++ b/src/northbridge/via/cn700/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_VIA_CN700 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT # TODO: Values are from the CX700 datasheet, not sure if this matches CN700. # TODO: What should be the per-chipset default value here? diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig index 8f6e337..03014eb 100644 --- a/src/northbridge/via/cx700/Kconfig +++ b/src/northbridge/via/cx700/Kconfig @@ -5,6 +5,7 @@ config NORTHBRIDGE_VIA_CX700 select HAVE_HARD_RESET select IOAPIC select SMP + select LATE_CBMEM_INIT # TODO: What should be the per-chipset default value here? choice diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 48ea456..a59fc41 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -2,4 +2,5 @@ config NORTHBRIDGE_VIA_VX800 bool select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS + select LATE_CBMEM_INIT diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 9fe5909..617074f 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_VIA_VX900 select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select LATE_CBMEM_INIT if NORTHBRIDGE_VIA_VX900

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coreboot-gerrit December 2014