coreboot-gerrit November 2014

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Patch set updated for coreboot: df4cf15 AGESA: Add common eventlog
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7161 -gerrit commit df4cf1535dce9dc3ca98e0551a4ad1f89b372d5a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 16:18:00 2014 +0300 AGESA: Add common eventlog Change-Id: Ibbf10a53ea671990d336340fdc96dfb37b5defd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/Makefile.inc | 7 ++---- src/northbridge/amd/agesa/agesawrapper.h | 4 ---- src/northbridge/amd/agesa/agesawrapper_call.h | 2 +- src/northbridge/amd/agesa/family12/agesawrapper.c | 26 ---------------------- src/northbridge/amd/agesa/family14/agesawrapper.c | 26 ---------------------- .../amd/agesa/family15rl/agesawrapper.c | 26 ---------------------- .../amd/agesa/family15tn/agesawrapper.c | 26 ---------------------- .../amd/agesa/family16kb/agesawrapper.c | 26 ---------------------- 8 files changed, 3 insertions(+), 140 deletions(-) diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 6eb4941..1eed658 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -24,8 +24,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-y += def_callouts.c -ramstage-y += def_callouts.c - -romstage-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += eventlog.c -ramstage-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += eventlog.c +romstage-y += def_callouts.c eventlog.c +ramstage-y += def_callouts.c eventlog.c diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index 49f6666..e1eb69b 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -48,11 +48,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void); AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 -AGESA_STATUS agesawrapper_amdreadeventlog(void); -#else AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); -#endif AGESA_STATUS agesawrapper_amdinitcpuio(void); AGESA_STATUS agesawrapper_amdinitmmio(void); diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h index 71997a8..3720dd3 100644 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ b/src/northbridge/amd/agesa/agesawrapper_call.h @@ -62,7 +62,7 @@ static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) #if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 /* TODO: These families do not pass valid HeapStatus. */ #define AGESA_EVENTLOG(status) \ - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog() + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0) #else #define AGESA_EVENTLOG(status, heapstatus) \ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus) diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 8a5f03f..5ced7b2 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -427,29 +427,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdreadeventlog(VOID) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, - "\nEventLog: EventClass = %lx, EventInfo = %lx.\n", - AmdEventParams.EventClass, AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %lx, Param2 = %lx.\n", - AmdEventParams.DataParam1, AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %lx, Param4 = %lx.\n", - AmdEventParams.DataParam3, AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index 1f580ef..84a01b0 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -538,29 +538,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdreadeventlog(VOID) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, - "\nEventLog: EventClass = %lx, EventInfo = %lx.\n", - AmdEventParams.EventClass, AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %lx, Param2 = %lx.\n", - AmdEventParams.DataParam1, AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %lx, Param4 = %lx.\n", - AmdEventParams.DataParam3, AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 2099a49..4f2e535 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -469,29 +469,3 @@ AGESA_STATUS agesawrapper_amdS3Save(void) } #endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 2099a49..4f2e535 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -469,29 +469,3 @@ AGESA_STATUS agesawrapper_amdS3Save(void) } #endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 2099a49..4f2e535 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -469,29 +469,3 @@ AGESA_STATUS agesawrapper_amdS3Save(void) } #endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -}

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Patch set updated for coreboot: 14ed33a AGESA fam14: Move agesawrapper_amdinitmmio()
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7163 -gerrit commit 14ed33a61a90d52640c499bc0274ced6dbead364 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 25 14:03:29 2014 +0200 AGESA fam14: Move agesawrapper_amdinitmmio() Enabling MMCONF PCI-e configuration access should be done before console_init(). This will likely move further to bootblock one day. Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/romstage.c | 5 ++--- src/mainboard/amd/inagua/romstage.c | 5 ++--- src/mainboard/amd/persimmon/romstage.c | 5 ++--- src/mainboard/amd/south_station/romstage.c | 5 ++--- src/mainboard/amd/union_station/romstage.c | 5 ++--- src/mainboard/asrock/e350m1/romstage.c | 5 ++--- src/mainboard/gizmosphere/gizmo/romstage.c | 5 ++--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 5 ++--- src/mainboard/lippert/frontrunner-af/romstage.c | 5 ++--- src/mainboard/lippert/toucan-af/romstage.c | 5 ++--- 10 files changed, 20 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index b1e9a61..c011038 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -43,6 +43,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); @@ -62,9 +64,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } - post_code(0x32); - agesawrapper_amdinitmmio(); - /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3a5c761..68822e0 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -54,6 +54,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5434ed3..b0c1624 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -60,6 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -78,9 +80,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 7dcd9b2..727b92d 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -55,6 +55,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index ac583dd..4d31d2b 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -50,6 +50,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -67,9 +69,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index c7c71a1..ea59a8d 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,6 +55,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 92b5292..5132eef 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -68,6 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) msr.hi = 0; wrmsr (MSR_PSTATE_CONTROL, msr); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -86,9 +88,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 534bdc4..d7fa6bc 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -76,6 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -94,9 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index c4bf978..52da850 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -59,6 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -77,9 +79,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 9d99894..13d6f66 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -60,6 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -78,9 +80,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset();

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New patch to review for coreboot: 9a39bcf ec: Use DEVICE_NOOP macro formalism over static stub func
by Edward O'Callaghan 28 Nov '14

28 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7598 -gerrit commit 9a39bcf2464e79665e90999853bc7f16f8274a94 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Nov 29 00:03:03 2014 +1100 ec: Use DEVICE_NOOP macro formalism over static stub func The in source comment: /* This function avoids an error on serial console. */ refers to the resource allocator needing to find a non-NULL function pointer else complaints of "... missing read_resources" will be spewed. Unfortunately/fortunately (depending on the time of day) compiler optimisers have gotten a bit better at optimising away no-op functions leading to the very message these stubs attempted to avoid. By using the DEVICE_NOOP formalism that is static inlined 'suggests' (not enforces) to the compiler to keep these symbols around. Change-Id: I182019627b6954a4020f9f70e9c829ce3135f63c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/ec/compal/ene932/ec.c | 16 ++-------------- src/ec/quanta/ene_kb3940q/ec.c | 16 ++-------------- src/ec/quanta/it8518/ec.c | 16 ++-------------- 3 files changed, 6 insertions(+), 42 deletions(-) diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index 4bf6727..91c979e 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -142,22 +142,10 @@ static void ene932_init(struct device *dev) } - -static void ene932_read_resources(struct device *dev) -{ - /* This function avoids an error on serial console. */ -} - - -static void ene932_enable_resources(struct device *dev) -{ - /* This function avoids an error on serial console. */ -} - static struct device_operations ops = { .init = ene932_init, - .read_resources = ene932_read_resources, - .enable_resources = ene932_enable_resources + .read_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index dcd9c4a..d7539fc 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -152,22 +152,10 @@ static void ene_kb3940q_init(struct device *dev) ene_kb3940q_log_events(); } - -static void ene_kb3940q_read_resources(struct device *dev) -{ - /* This function avoids an error on serial console. */ -} - - -static void ene_kb3940q_enable_resources(struct device *dev) -{ - /* This function avoids an error on serial console. */ -} - static struct device_operations ops = { .init = ene_kb3940q_init, - .read_resources = ene_kb3940q_read_resources, - .enable_resources = ene_kb3940q_enable_resources + .read_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, }; static struct pnp_info pnp_dev_info[] = { diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index cd976e6..5ce5c6c 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -165,22 +165,10 @@ static void it8518_init(struct device *dev) pc_keyboard_init(); } - -static void it8518_read_resources(struct device *dev) -{ - /* This function avoids an error on serial console. */ -} - - -static void it8518_enable_resources(struct device *dev) -{ - /* This function avoids an error on serial console. */ -} - static struct device_operations ops = { .init = it8518_init, - .read_resources = it8518_read_resources, - .enable_resources = it8518_enable_resources + .read_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, }; static struct pnp_info pnp_dev_info[] = {

1 0

New patch to review for coreboot: 2eea87d TEST
by Edward O'Callaghan 28 Nov '14

28 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7597 -gerrit commit 2eea87df781d8909509e929e9df90cbfee7970fb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Nov 28 23:45:54 2014 +1100 TEST Change-Id: I9a218f7bb3aa7a63f9325248075bae3aa9027f1f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/agesawrapper.h | 2 +- src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 2 +- src/mainboard/amd/inagua/agesawrapper.h | 2 +- src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h | 2 +- src/mainboard/amd/olivehill/agesawrapper.h | 2 +- src/mainboard/amd/parmer/PlatformGnbPcieComplex.h | 2 +- src/mainboard/amd/parmer/agesawrapper.h | 2 +- src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h | 2 +- src/mainboard/amd/persimmon/agesawrapper.h | 2 +- src/mainboard/amd/south_station/PlatformGnbPcieComplex.h | 2 +- src/mainboard/amd/south_station/agesawrapper.h | 2 +- src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h | 2 +- src/mainboard/amd/thatcher/agesawrapper.h | 2 +- src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 2 +- src/mainboard/amd/torpedo/agesawrapper.h | 2 +- src/mainboard/amd/union_station/PlatformGnbPcieComplex.h | 2 +- src/mainboard/amd/union_station/agesawrapper.h | 2 +- src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h | 2 +- src/mainboard/asrock/e350m1/agesawrapper.h | 2 +- src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h | 2 +- src/mainboard/asrock/imb-a180/agesawrapper.h | 2 +- src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h | 2 +- src/mainboard/gizmosphere/gizmo/agesawrapper.h | 2 +- src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h | 2 +- src/mainboard/lippert/frontrunner-af/agesawrapper.h | 2 +- src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h | 2 +- src/mainboard/lippert/toucan-af/agesawrapper.h | 2 +- src/mainboard/supermicro/h8qgi/agesawrapper.h | 2 +- src/mainboard/supermicro/h8scm/agesawrapper.h | 2 +- src/mainboard/tyan/s8226/agesawrapper.h | 2 +- 30 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index efce9c2..e30618a 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 111ad6f..e854bbf 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h index 3f7549e..133040e 100644 --- a/src/mainboard/amd/inagua/agesawrapper.h +++ b/src/mainboard/amd/inagua/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h b/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h index b3c69cf..7bddd4f 100644 --- a/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/amd/olivehill/agesawrapper.h b/src/mainboard/amd/olivehill/agesawrapper.h index 9e4617d..de20341 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.h +++ b/src/mainboard/amd/olivehill/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h index b3c69cf..7bddd4f 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/amd/parmer/agesawrapper.h b/src/mainboard/amd/parmer/agesawrapper.h index 9e4617d..de20341 100644 --- a/src/mainboard/amd/parmer/agesawrapper.h +++ b/src/mainboard/amd/parmer/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index ec8a6e3..70f48e6 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h index d14603e..08244c6 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ b/src/mainboard/amd/persimmon/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 5efcd7d..ba5bc5a 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/amd/south_station/agesawrapper.h b/src/mainboard/amd/south_station/agesawrapper.h index 65c14e9..7e4885e 100644 --- a/src/mainboard/amd/south_station/agesawrapper.h +++ b/src/mainboard/amd/south_station/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h b/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h index b3c69cf..7bddd4f 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/amd/thatcher/agesawrapper.h b/src/mainboard/amd/thatcher/agesawrapper.h index 9e4617d..de20341 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.h +++ b/src/mainboard/amd/thatcher/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 5efcd7d..ba5bc5a 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h index 3a0aa0b..a8a23be 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.h +++ b/src/mainboard/amd/torpedo/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 5efcd7d..ba5bc5a 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/amd/union_station/agesawrapper.h b/src/mainboard/amd/union_station/agesawrapper.h index 65c14e9..7e4885e 100644 --- a/src/mainboard/amd/union_station/agesawrapper.h +++ b/src/mainboard/amd/union_station/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 5efcd7d..ba5bc5a 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h index 9937fb2..ae6f537 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.h +++ b/src/mainboard/asrock/e350m1/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h b/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h index 1db8b2d..ccc6813 100644 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.h b/src/mainboard/asrock/imb-a180/agesawrapper.h index acaa2b3..ca7551c 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.h +++ b/src/mainboard/asrock/imb-a180/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h index 5cd4b41..5fe3656 100755 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h @@ -21,7 +21,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> diff --git a/src/mainboard/gizmosphere/gizmo/agesawrapper.h b/src/mainboard/gizmosphere/gizmo/agesawrapper.h index b8c3f6c..b7f6a2b 100755 --- a/src/mainboard/gizmosphere/gizmo/agesawrapper.h +++ b/src/mainboard/gizmosphere/gizmo/agesawrapper.h @@ -22,7 +22,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h index 02c7f4e..ad0cf9a 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> diff --git a/src/mainboard/lippert/frontrunner-af/agesawrapper.h b/src/mainboard/lippert/frontrunner-af/agesawrapper.h index a74a800..26f7390 100644 --- a/src/mainboard/lippert/frontrunner-af/agesawrapper.h +++ b/src/mainboard/lippert/frontrunner-af/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h index 69e2615..b482c9e 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h @@ -20,7 +20,7 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #include "amdlib.h" #include <cpu/amd/agesa/s3_resume.h> diff --git a/src/mainboard/lippert/toucan-af/agesawrapper.h b/src/mainboard/lippert/toucan-af/agesawrapper.h index a74a800..26f7390 100644 --- a/src/mainboard/lippert/toucan-af/agesawrapper.h +++ b/src/mainboard/lippert/toucan-af/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h index fec1ada..aa0a476 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.h +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h @@ -22,7 +22,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.h b/src/mainboard/supermicro/h8scm/agesawrapper.h index e01c2ac..a665b4e 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.h +++ b/src/mainboard/supermicro/h8scm/agesawrapper.h @@ -22,7 +22,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS diff --git a/src/mainboard/tyan/s8226/agesawrapper.h b/src/mainboard/tyan/s8226/agesawrapper.h index 66a827d..88af20e 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.h +++ b/src/mainboard/tyan/s8226/agesawrapper.h @@ -21,7 +21,7 @@ #define _AGESAWRAPPER_H_ #include <stdint.h> -#include "Porting.h" +#include <vendorcode/amd/agesa/Porting.h> #include "AGESA.h" #define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS

1 0

Patch set updated for coreboot: 7a2d253 vendorcode/amd/agesa: Make Porting.h common between families
by Edward O'Callaghan 28 Nov '14

28 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7594 -gerrit commit 7a2d253d8b811550db98e14ecf83cad732d11aa7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Nov 28 22:26:45 2014 +1100 vendorcode/amd/agesa: Make Porting.h common between families Change-Id: Ica17b2452498f30b710533caf610c9f0c1a0452c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/Porting.h | 282 ++++++++++++++++++++++++++++ src/vendorcode/amd/agesa/f10/Makefile.inc | 1 + src/vendorcode/amd/agesa/f10/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f12/Makefile.inc | 1 + src/vendorcode/amd/agesa/f12/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f14/Makefile.inc | 1 + src/vendorcode/amd/agesa/f14/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f15/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15tn/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 1 + src/vendorcode/amd/agesa/f16kb/Porting.h | 282 ---------------------------- 13 files changed, 288 insertions(+), 1692 deletions(-) diff --git a/src/vendorcode/amd/agesa/Porting.h b/src/vendorcode/amd/agesa/Porting.h new file mode 100644 index 0000000..fc65cfc --- /dev/null +++ b/src/vendorcode/amd/agesa/Porting.h @@ -0,0 +1,282 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Describes compiler dependencies - to support several compile time environments + * + * Contains compiler environment porting descriptions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Includes + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _PORTING_H_ +#define _PORTING_H_ + +#if defined (_MSC_VER) + #include <intrin.h> + void _disable (void); + void _enable (void); + #pragma warning(disable: 4103 4001 4733) + #pragma intrinsic (_disable, _enable) + #pragma warning(push) + // ----------------------------------------------------------------------- + // Define a code_seg MACRO + // + #define MAKE_AS_A_STRING(arg) #arg + + #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) + + #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) + #define FUNC_ATTRIBUTE(arg) __declspec(arg) + //#include <intrin.h> // MS has built-in functions + + #if _MSC_VER < 900 + // ----------------------------------------------------------------------- + // Assume MSVC 1.52C (16-bit) + // + // NOTE: When using MSVC 1.52C use the following command line: + // + // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> + // + // This will produce 32-bit code in USE16 segment that is optimized for code + // size. + typedef void VOID; + + // Create the universal 32, 16, and 8-bit data types + typedef unsigned long UINTN; + typedef long INT32; + typedef unsigned long UINT32; + typedef int INT16; + typedef unsigned int UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + /// struct for 16-bit environment handling of 64-bit value + typedef struct _UINT64 { + IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value + IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value + } UINT64; + + // Create the Boolean type + #define TRUE 1 + #define FALSE 0 + typedef unsigned char BOOLEAN; + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV __pascal + #define ROMDATA __based( __segname( "_CODE" ) ) + #define _16BYTE_ALIGN __declspec(align(16)) + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning + #pragma pack(1) + + // Disable WORD->BYTE automatic conversion warnings. Example: + // BYTE LocalByte; + // void MyFunc(BYTE val); + // + // MyFunc(LocalByte*2+1); // Warning, automatic conversion + // + // The problem is any time math is performed on a BYTE, it is converted to a + // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning + // is generated. Disable warning C4761 + #pragma warning( disable : 4761 ) + + #else + // ----------------------------------------------------------------------- + // Assume a 32-bit MSVC++ + // + // Disable the following warnings: + // 4100 - 'identifier' : unreferenced formal parameter + // 4276 - 'function' : no prototype provided; assumed no parameters + // 4214 - non standard extension used : bit field types other than int + // 4001 - nonstandard extension 'single line comment' was used + // 4142 - benign redefinition of type for following declaration + // - typedef char INT8 + #if defined (_M_IX86) + #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) + + #ifndef VOID + typedef void VOID; + #endif + // Create the universal 32, 16, and 8-bit data types + #ifndef UINTN + typedef unsigned __w64 UINTN; + #endif + typedef __int64 INT64; + typedef unsigned __int64 UINT64; + typedef int INT32; + typedef unsigned int UINT32; + typedef short INT16; + typedef unsigned short UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + // Create the Boolean type + #ifndef TRUE + #define TRUE 1 + #endif + #ifndef FALSE + #define FALSE 0 + #endif + typedef unsigned char BOOLEAN; + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma pack(1) + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV + #define ROMDATA + #define _16BYTE_ALIGN __declspec(align(64)) + // 64 bit of compiler + #else + #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) + + #ifndef VOID + typedef void VOID; + #endif + // Create the universal 32, 16, and 8-bit data types + #ifndef UINTN + typedef unsigned __int64 UINTN; + #endif + typedef __int64 INT64; + typedef unsigned __int64 UINT64; + typedef int INT32; + typedef unsigned int UINT32; + typedef short INT16; + typedef unsigned short UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + // Create the Boolean type + #ifndef TRUE + #define TRUE 1 + #endif + #ifndef FALSE + #define FALSE 0 + #endif + typedef unsigned char BOOLEAN; + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma pack(1) + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV + #define ROMDATA + #endif + #endif + // ----------------------------------------------------------------------- + // End of MS compiler versions + +#elif defined __GNUC__ + + #define IN + #define OUT + #define STATIC static + #define VOLATILE volatile + #define TRUE 1 + #define FALSE 0 +// #undef CONST + #define CONST const + #define ROMDATA + #define CALLCONV + #define _16BYTE_ALIGN __attribute__ ((aligned (16))) + + typedef unsigned char BOOLEAN; + typedef signed char INT8; + typedef signed short INT16; + typedef signed long INT32; + typedef char CHAR8; + typedef unsigned char UINT8; + typedef unsigned short UINT16; + typedef unsigned long UINT32; + typedef unsigned long UINTN; + typedef unsigned long long UINT64; + typedef long long INT64; + typedef void VOID; + //typedef unsigned long size_t; + + //#include <intrin.h> // MingW-w64 library header +#pragma pack(1) + +#define CODE_GROUP(arg) +#define RDATA_GROUP(arg) + +#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) +#define MAKE_AS_A_STRING(arg) #arg +#include <stddef.h> +#include "gcc-intrin.h" + +#include <assert.h> +#include <console/console.h> +#include <console/loglevel.h> + +#ifndef NULL + #define NULL (void *)0 +#endif + +#else + // ----------------------------------------------------------------------- + // Unknown or unsupported compiler + // + #error "Unknown compiler in use" +#endif + +// ----------------------------------------------------------------------- +// Common definitions for all compilers +// + +//Support forward reference construct +#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x + +// The following are use in conformance to the UEFI style guide +#define IN +#define OUT + +#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc index b684a29..2d7e60c 100644 --- a/src/vendorcode/amd/agesa/f10/Makefile.inc +++ b/src/vendorcode/amd/agesa/f10/Makefile.inc @@ -22,6 +22,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f10 AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f10/Porting.h b/src/vendorcode/amd/agesa/f10/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f10/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index b7f9d92..c4578d5 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -32,6 +32,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f12 AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family AGESA_INC += -I$(AGESA_ROOT)/Include diff --git a/src/vendorcode/amd/agesa/f12/Porting.h b/src/vendorcode/amd/agesa/f12/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f12/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 0f570d7..5e36684 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -32,6 +32,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f14 AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f14/Porting.h b/src/vendorcode/amd/agesa/f14/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f14/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index 7c1359e..f086e4e 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -22,6 +22,7 @@ AGESA_ROOT ?= $(PWD) AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f15/Porting.h b/src/vendorcode/amd/agesa/f15/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f15/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 4b44cef..db932e5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -32,6 +32,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f15tn AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f15tn/Porting.h b/src/vendorcode/amd/agesa/f15tn/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f15tn/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 164b305..0708dc3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -32,6 +32,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f16kb AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f16kb/Porting.h b/src/vendorcode/amd/agesa/f16kb/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_

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New patch to review for coreboot: 311929a vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementation
by Edward O'Callaghan 28 Nov '14

28 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7596 -gerrit commit 311929a4846a18730c1023bef063816d2421be21 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Nov 28 22:58:01 2014 +1100 vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementation We don't actually use nor support these as our implementation makes use of gcccar.inc. They maybe useful as a reference for history so lets keep them in version history. Change-Id: I388251dead449dde14283e57db39c37982d947b2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f10/cpcar.inc | 477 ---------- src/vendorcode/amd/agesa/f12/cpcar.inc | 1302 ------------------------- src/vendorcode/amd/agesa/f14/cpcar.inc | 1124 ---------------------- src/vendorcode/amd/agesa/f15/cpcar.inc | 1470 ---------------------------- src/vendorcode/amd/agesa/f15tn/cpcar.inc | 1529 ------------------------------ 5 files changed, 5902 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/cpcar.inc b/src/vendorcode/amd/agesa/f10/cpcar.inc deleted file mode 100644 index 1a692c4..0000000 --- a/src/vendorcode/amd/agesa/f10/cpcar.inc +++ /dev/null @@ -1,477 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; $Workfile:: cpcar.inc -; -; Description: CPCAR.INC - AGESA cache-as-RAM setup Include File -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - -CORE0_STACK_BASE_ADDR EQU 40000h ;base address for primary cores stack -CORE1_STACK_BASE_ADDR EQU 60000h ;base address for AP cores -CORE0_STACK_SIZE EQU 4000h ;16KB for primary cores -CORE1_STACK_SIZE EQU 1000h ;4KB for each AP cores - -AMD_MTRR_FIX64k_00000 EQU 250h -AMD_MTRR_FIX16k_80000 EQU 258h -AMD_MTRR_FIX16k_A0000 EQU 259h -AMD_MTRR_FIX4k_C0000 EQU 268h -AMD_MTRR_FIX4k_C8000 EQU 269h -AMD_MTRR_FIX4k_D0000 EQU 26Ah -AMD_MTRR_FIX4k_D8000 EQU 26Bh -AMD_MTRR_FIX4k_E0000 EQU 26Ch -AMD_MTRR_FIX4k_E8000 EQU 26Dh -AMD_MTRR_FIX4k_F0000 EQU 26Eh -AMD_MTRR_FIX4k_F8000 EQU 26Fh -AMD_MTRR_DEFTYPE EQU 2FFh - -AMD_MTRR_VARIABLE_BASE6 EQU 020Ch - -TOP_MEM EQU 0C001001Ah - -MtrrFixDramEn EQU 18 -MtrrFixDramModEn EQU 19 -MtrrVarDramEn EQU 20 - -WB_DRAM_TYPE EQU 1Eh - -HWCR EQU 0C0010015h - INVD_WBINVD EQU 4 - -LS_CFG EQU 0C0011020h - DisStreamSt EQU 28 - -IC_CFG EQU 0C0011021h - DIS_SPEC_TLB_RLD EQU 9 - DIS_IND EQU 14 - -BU_CFG2 EQU 0C001102Ah - ClLinesToNbDis EQU 15 - -DC_DIS_SPEC_TLB_RLD EQU 4 ; disable speculative TLB reloads -DIS_CLR_WBTOL2_SMC_HIT EQU 8 ; self modifying code check buffer bit -DIS_HW_PF EQU 13 ; hardware prefetches bit -IC_DIS_SPEC_TLB_RLD EQU 9 ; disable speculative TLB reloads - -CR0_CD EQU 40000000h ; CR0[30] = Cache Disable -CR0_NW EQU 20000000h ; CR0[29] = Not Writethrough - -; CPUID Functions - -CPUID_MODEL EQU 1 -AMD_CPUID_FMF EQU 80000001h ; Family Model Features information - -NB_CFG EQU 0C001001Fh - bEnableCF8ExtCfg EQU 00004000h ; [46] - bInitAPICCPUIDLo EQU 00400000h ; [54] - -MTRR_SYS_CFG EQU 0C0010010h - ChxToDirtyDis EQU 16 - SysUcLockEn EQU 17 - MtrrFixDramEn EQU 18 - MtrrFixDramModEn EQU 19 - MtrrVarDramEn EQU 20 - MtrrTom2En EQU 21 - -PERF_COUNTER3 EQU 0C0010007h ; Performance event counter three -PERF_CONTROL3 EQU 0C0010003h ; Performance event control three -PERF_CONTROL3_RESERVE_L EQU 00200000h ; Preserve the reserved bits -PERF_CONTROL3_RESERVE_H EQU 0FCF0h ; Preserve the reserved bits -CONFIG_EVENT_L EQU 0F0E2h ; All cores with level detection -CONFIG_EVENT_H EQU 4 ; Increment count by number of event - ; occured in clock cycle -EVENT_ENABLE EQU 22 ; Enable the event - -;;*************************************************************************** -;; -;; CPU MACROS - PUBLIC -;; -;;*************************************************************************** -_WRMSR macro - db 0Fh, 30h - endm -_RDMSR macro - db 0Fh, 32h - endm - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless -; -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK MACRO - - AMD_DISABLE_STACK_FAMILY_HOOK_F10 - AMD_DISABLE_STACK_FAMILY_HOOK_F14 - -ENDM - -AMD_DISABLE_STACK_FAMILY_HOOK_F10 MACRO - - local cl_line_to_nb_enable_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz cl_line_to_nb_enable_exit ; Br if no - - ; For Family 10h, clear BU_CFG2[15] ClLinesToNbDis bit to Re-Enable L3 cache - ; Warning: icache for ROM (IO space) is disabled - mov ecx, 0C001102Ah ; BU_CFG2 - _RDMSR - btr eax, 15 - btr edx, 3 - _WRMSR - - ; * MSRC001_1021[DIS_IND]=0. Disable indirect branch predictor. - mov ecx, IC_CFG ; IC_CFG - _RDMSR - btr eax, DIS_IND ; turn off Disable indirect branch predictor - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - ; Disable INVD_WBINVD across the invd instruction. - mov cx, 0015h ; HWCR - _RDMSR - mov bx, ax ; save INVD -> WBINVD bit - and al, 0EFh ; disable INVD -> WBINVD conversion - _WRMSR - - invd ; Clear the cache tag RAMs - - ; Restore INVD_WBINVD - mov ax, bx ; restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Retrieve the current value - btc eax, EVENT_ENABLE ; Is event enable, complement it as well - jnc cl_line_to_nb_enable_exit ; No - cmp ax, CONFIG_EVENT_L ; Is the lower part of event set to capture the CAR Corruption - jne cl_line_to_nb_enable_exit ; No - cmp dl, CONFIG_EVENT_H ; Is the upper part of event set to capture the CAR Corruption - jne cl_line_to_nb_enable_exit ; No - _WRMSR ; Disable the event - -cl_line_to_nb_enable_exit: -ENDM - -AMD_DISABLE_STACK_FAMILY_HOOK_F14 MACRO - - local fam14_enable_stack_hook_exit - - ; - ; For Family 14h - ; - ; Restore the following configuration state: - ; * MSRC001_0015[INVD_WBINVD]=1. - ; * MSRC001_1020[DisStreamSt]=0. - ; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0. - ; * MSRC001_1022[DIS_HW_PF]=0. - ; - ; When BIOS is done executing from WP-IO the following steps are followed: - ; * MSRC001_102A[ClLinesToNbDis]=1. - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 10h? - jnz fam14_enable_stack_hook_exit ; Br if no - - ; * MSRC001_0015[INVD_WBINVD]=0. - mov ecx, HWCR - _RDMSR - bts eax, INVD_WBINVD ; turn off Convert INVD to WBINVD bit - _WRMSR - ; * MSRC001_1020[DisStreamSt]=1. - mov ecx, LS_CFG - _RDMSR - btr eax, DisStreamSt ; turn on Streaming store functionality disabled bit - _WRMSR - ; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. - inc ecx ; mov ecx, IC_CFG - _RDMSR - btr eax, DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit - _WRMSR - ; * MSRC001_1022[DIS_HW_PF]=1. - inc ecx - _RDMSR - btr eax, DIS_HW_PF ; turn on Disable hardware prefetches bit - _WRMSR - -fam14_enable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless -; -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK MACRO - - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - -ENDM - -AMD_ENABLE_STACK_FAMILY_HOOK_F10 MACRO - - local cl_line_to_nb_disable_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz cl_line_to_nb_disable_exit ; Br if no - - ; For Family 10h, set BU_CFG2[15] ClLinesToNbDis bit to disable L3 cache - ; Allow BIOS ROM to be cached in the IC - mov ecx, 0C001102Ah ; BU_CFG2 - _RDMSR - bts eax, 15 - bts edx, 3 - _WRMSR - - mov cx, 0015h ; HWCR - _RDMSR - and al, 0EFh ; disable INVD -> WBINVD conversion - _WRMSR - - ; * MSRC001_1021[DIS_IND]=1. Disable indirect branch predictor. - mov ecx, IC_CFG ; IC_CFG - _RDMSR - bts eax, DIS_IND ; turn on Disable indirect branch predictor - _WRMSR - - .if (di == 0) ;core 0 - mov ecx, PERF_COUNTER3 ; Select performance counter three - ; to count number of CAR Corruption - xor eax, eax ; Initialize the lower part of the counter to zero - xor edx, edx ; Initializa the upper part of the counter to zero - _WRMSR ; Save it - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Get the current setting - and eax, PERF_CONTROL3_RESERVE_L ; Preserve the reserved bits - or eax, CONFIG_EVENT_L ; Set the lower part of event register to - ; select CAR Corruption occurred by any cores - and dx, PERF_CONTROL3_RESERVE_H ; Preserve the reserved bits - or dx, CONFIG_EVENT_H ; Set the upper part of event register - _WRMSR ; Save it - bts eax, EVENT_ENABLE ; Enable it - _WRMSR ; Save it - .endif - -cl_line_to_nb_disable_exit: -ENDM - -AMD_ENABLE_STACK_FAMILY_HOOK_F14 MACRO - - local fam14_enable_stack_hook_exit - - ; - ; For Family 14h - ; - ; The following requirements must be satisfied prior to using the cache as general storage: - ; * Paging must be disabled. - ; * MSRC001_0015[INVD_WBINVD]=0. - ; * MSRC001_1020[DisStreamSt]=1. - ; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. - ; * MSRC001_1022[DIS_HW_PF]=1. - ; * MSRC001_102A[ClLinesToNbDis]=1. - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 10h? - jnz fam14_enable_stack_hook_exit ; Br if no - - ; * MSRC001_0015[INVD_WBINVD]=0. - mov ecx, HWCR - _RDMSR - btr eax, INVD_WBINVD ; turn off Convert INVD to WBINVD bit - _WRMSR - ; * MSRC001_1020[DisStreamSt]=1. - mov ecx, LS_CFG - _RDMSR - bts eax, DisStreamSt ; turn on Streaming store functionality disabled bit - _WRMSR - ; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. - inc ecx ; mov ecx, IC_CFG - _RDMSR - bts eax, DIS_SPEC_TLB_RLD ; turn on Disable speculative TLB reloads bit - _WRMSR - ; * MSRC001_1022[DIS_HW_PF]=1. - inc ecx - _RDMSR - bts eax, DIS_HW_PF ; turn on Disable hardware prefetches bit - _WRMSR - ; * MSRC001_102A[ClLinesToNbDis]=1. - mov ecx, BU_CFG2 - _RDMSR - bts eax, ClLinesToNbDis ; turn on DC and IC caches WT/WP-IO, but L2 does not. - _WRMSR - -fam14_enable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID Macro - Stackless -; -; Macro returns: -; SI= NODE ID -; DI= CORE ID -;--------------------------------------------------- -GET_NODE_ID_CORE_ID MACRO - - GET_NODE_ID_CORE_ID_F10 - GET_NODE_ID_CORE_ID_F12 - GET_NODE_ID_CORE_ID_F14 - -ENDM - -GET_NODE_ID_CORE_ID_F10 MACRO - - local node_core_f10_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f10_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz node_core_f10_exit ; Br if no - - mov ecx, 1Bh ; APIC Base MSR - _RDMSR - xor si, si ; Assume BSC - xor di, di - test ah, 1 ; Is this the BSC? - jnz node_core_f10_exit ; Br if yes - mov ecx, 0C0000408h ; Read the family 10h mailbox - _RDMSR - mov si, dx ; SI = raw mailbox contents - shr ebx, 24 ; BL = Initial APIC ID - mov di, bx ; DI = Initial APIC ID - - AMD_CPUID 80000008h - shr ch, 4 ; CH = ApicIdSize - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG - _RDMSR ; EDX bit 54-32=26 is InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, 54-32 ; InitApicId == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch - shr di, cl ; Right justify core number - .endif - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - mov di, dx ; DI = node-relative core number - and si, 000Fh ; SI = node number -node_core_f10_exit: -ENDM - -GET_NODE_ID_CORE_ID_F12 MACRO - - local node_core_f12_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f12_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 10h? - jnz node_core_f12_exit ; Br if no - - xor si, si ; Node must be 0 - shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - mov di, bx ; DI = core number -node_core_f12_exit: -ENDM - -GET_NODE_ID_CORE_ID_F14 MACRO - - local node_core_f14_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f14_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz node_core_f14_exit ; Br if no - - xor si, si ; Node must be 0 - mov ecx, 1Bh ; APIC Base MSR - _RDMSR - xor di, di ; Assume BSC - test ah, 1 ; Is this the BSC? - jnz node_core_f14_exit ; Br if yes - inc di ; Set core to 1 -node_core_f14_exit: -ENDM - - -AMD_CPUID MACRO arg0 - IFB <arg0> - mov eax, 1 - db 0Fh, 0A2h ; Execute instruction - bswap eax - xchg al, ah ; Ext model in al now - rol eax, 8 ; Ext model in ah, model in al - and ax, 0FFCFh ; Keep 23:16, 7:6, 3:0 - ELSE - mov eax, arg0 - db 0Fh, 0A2h - ENDIF -ENDM - diff --git a/src/vendorcode/amd/agesa/f12/cpcar.inc b/src/vendorcode/amd/agesa/f12/cpcar.inc deleted file mode 100644 index acb2636..0000000 --- a/src/vendorcode/amd/agesa/f12/cpcar.inc +++ /dev/null @@ -1,1302 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; $Workfile:: cpcar.inc -; -; Description: CPCAR.INC - AGESA cache-as-RAM setup Include File -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;***************************************************************************** - -BSP_STACK_BASE_ADDR EQU 30000h ; Base address for primary cores stack -BSP_STACK_SIZE EQU 10000h ; 64KB for BSP core -CORE0_STACK_BASE_ADDR EQU 80000h ; Base address for primary cores stack -CORE0_STACK_SIZE EQU 4000h ; 16KB for primary cores -CORE1_STACK_BASE_ADDR EQU 40000h ; Base address for AP cores -CORE1_STACK_SIZE EQU 1000h ; 4KB for each AP cores - -L3_CONTROL_REGISTER EQU 8100C3B8h ; Bus 0, Device 18h, Function 3, Offset 1B8h - -APIC_BASE_ADDRESS EQU 0000001Bh - APIC_BSC EQU 8 ; Boot Strap Core - -APIC_MSG_REG EQU 380h ; Location of BSC message - APIC_MSG EQU 00DE00ADh ; Message data -APIC_CMD_LO_REG EQU 300h ; APIC command low -APIC_CMD_HI_REG EQU 310h ; APIC command high - CMD_REG_TO_READ_DATA EQU 00000338h ; APIC command for remote read of APIC_MSG_REG - REMOTE_READ_STS EQU 00030000h ; Remote read status mask - REMOTE_DELIVERY_PEND EQU 00010000h ; Remote read is pending - REMOTE_DELIVERY_DONE EQU 00020000h ; Remote read is complete - DELIVERY_STS_BIT EQU 12 ; Delivery status valid bit -APIC_ID_REG EQU 0020h ; Local APIC ID offset - APIC20_APICID EQU 24 -APIC_REMOTE_READ_REG EQU 00C0h ; Remote read offset - -AMD_CU_NEED_TO_WAIT EQU 31 -AMD_CU_SEND_INVD_MSG EQU 30 -AMD_CU_RESTORE_ES EQU 29 - -AMD_MTRR_VARIABLE_BASE0 EQU 0200h -AMD_MTRR_VARIABLE_BASE6 EQU 020Ch -AMD_MTRR_VARIABLE_MASK7 EQU 020Fh -AMD_MTRR_FIX64k_00000 EQU 0250h -AMD_MTRR_FIX16k_80000 EQU 0258h -AMD_MTRR_FIX16k_A0000 EQU 0259h -AMD_MTRR_FIX4k_C0000 EQU 0268h -AMD_MTRR_FIX4k_C8000 EQU 0269h -AMD_MTRR_FIX4k_D0000 EQU 026Ah -AMD_MTRR_FIX4k_D8000 EQU 026Bh -AMD_MTRR_FIX4k_E0000 EQU 026Ch -AMD_MTRR_FIX4k_E8000 EQU 026Dh -AMD_MTRR_FIX4k_F0000 EQU 026Eh -AMD_MTRR_FIX4k_F8000 EQU 026Fh - -AMD_MTRR_DEFTYPE EQU 02FFh - WB_DRAM_TYPE EQU 1Eh ; MemType - memory type - MTRR_DEF_TYPE_EN EQU 11 ; MtrrDefTypeEn - variable and fixed MTRRs default enabled - MTRR_DEF_TYPE_FIX_EN EQU 10 ; MtrrDefTypeEn - fixed MTRRs default enabled - -HWCR EQU 0C0010015h ; Hardware Configuration - INVD_WBINVD EQU 4 ; INVD to WBINVD conversion - -IORR_BASE EQU 0C0010016h ; IO Range Regusters Base/Mask, 2 pairs - ; uses 16h - 19h -TOP_MEM EQU 0C001001Ah ; Top of Memory -TOP_MEM2 EQU 0C001001Dh ; Top of Memory2 - -LS_CFG EQU 0C0011020h ; Load-Store Configuration - DIS_SS EQU 28 ; Family 10h,12h,15h:Disable Streaming Store functionality - DIS_STREAM_ST EQU 28 ; Family 14h:DisStreamSt - Disable Streaming Store functionality - -IC_CFG EQU 0C0011021h ; Instruction Cache Config Register - IC_DIS_SPEC_TLB_RLD EQU 9 ; Disable speculative TLB reloads - DIS_IND EQU 14 ; Family 10-14h:Disable Indirect Branch Predictor - DIS_I_CACHE EQU 14 ; Family 15h:DisICache - Disable Indirect Branch Predictor - -DC_CFG EQU 0C0011022h ; Data Cache Configuration - DC_DIS_SPEC_TLB_RLD EQU 4 ; Disable speculative TLB reloads - DIS_CLR_WBTOL2_SMC_HIT EQU 8 ; self modifying code check buffer bit - DIS_HW_PF EQU 13 ; Hardware prefetches bit - -CU_CFG EQU 0C0011023h ; Family 15h: Combined Unit Configuration - L2_WAY_LOCK_EN EQU 23 ; L2WayLock - L2 way lock enable - L2_FIRST_LOCKED_WAY EQU 19 ; L2FirstLockedWay - first L2 way lockedh - L2_FIRST_LOCKED_WAY_OR_MASK EQU 000780000h - -DE_CFG EQU 0C0011029h ; Decode Configuration - CL_FLUSH_SERIALIZE EQU 23 ; Family 12h,15h: CL Flush Serialization - -BU_CFG2 EQU 0C001102Ah ; Family 10h: Bus Unit Configuration 2 -CU_CFG2 EQU 0C001102Ah ; Family 15h: Combined Unit Configuration 2 - F10_CL_LINES_TO_NB_DIS EQU 15 ; ClLinesToNbDis - allows WP code to be cached in L2 - IC_DIS_SPEC_TLB_WR EQU 35 ; IcDisSpecTlbWr - ITLB speculative writes - -CU_CFG3 EQU 0C001102Bh ; Combined Unit Configuration 3 - COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit - - -CR0_PE EQU 0 ; Protection Enable -CR0_NW EQU 29 ; Not Write-through -CR0_CD EQU 30 ; Cache Disable -CR0_PG EQU 31 ; Paging Enable - -; CPUID Functions - -CPUID_MODEL EQU 1 -AMD_CPUID_FMF EQU 80000001h ; Family Model Features information -AMD_CPUID_APIC EQU 80000008h ; Long Mode and APIC info., core count - APIC_ID_CORE_ID_SIZE EQU 12 ; ApicIdCoreIdSize bit position - -NB_CFG EQU 0C001001Fh ; Northbridge Configuration Register - INIT_APIC_ID_CPU_ID_LO EQU 54 ; InitApicIdCpuIdLo - is core# in high or low half of APIC ID? - ENABLE_CF8_EXT_CFG EQU 46 ; EnableCf8ExtCfg - enable CF8 extended configuration cycles - -MTRR_SYS_CFG EQU 0C0010010h ; System Configuration Register - CHX_TO_DIRTY_DIS EQU 16 ; ChxToDirtyDis Change to dirty disable - SYS_UC_LOCK_EN EQU 17 ; SysUcLockEn System lock command enable - MTRR_FIX_DRAM_EN EQU 18 ; MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable - MTRR_FIX_DRAM_MOD_EN EQU 19 ; MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable - MTRR_VAR_DRAM_EN EQU 20 ; MtrrVarDramEn MTRR variable DRAM enable - MTRR_TOM2_EN EQU 21 ; MtrrTom2En MTRR top of memory 2 enable - -PERF_CONTROL3 EQU 0C0010003h ; Performance event control three - PERF_CONTROL3_RESERVE_L EQU 00200000h ; Preserve the reserved bits - PERF_CONTROL3_RESERVE_H EQU 0FCF0h ; Preserve the reserved bits - CONFIG_EVENT_L EQU 0F0E2h ; All cores with level detection - CONFIG_EVENT_H EQU 4 ; Increment count by number of event - ; occured in clock cycle - EVENT_ENABLE EQU 22 ; Enable the event -PERF_COUNTER3 EQU 0C0010007h ; Performance event counter three - -; Local use flags, in upper most byte if ESI -FLAG_UNKNOWN_FAMILY EQU 24 ; Signals that the family# of the installed processor is not recognized -FLAG_STACK_REENTRY EQU 25 ; Signals that the environment has made a re-entry (2nd) call to set up the stack -FLAG_IS_PRIMARY EQU 26 ; Signals that this core is the primary within the compute unit -FLAG_CORE_NOT_IDENTIFIED EQU 27 ; Signals that the cores/compute units of the installed processor is not recognized - -; Error code returned in EDX by AMD_ENABLE_STACK -IFNDEF CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY - CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY EQU 008010500h -ENDIF -IFNDEF CPU_EVENT_STACK_REENTRY - CPU_EVENT_STACK_REENTRY EQU 008020500h -ENDIF -IFNDEF CPU_EVENT_CORE_NOT_IDENTIFIED - CPU_EVENT_CORE_NOT_IDENTIFIED EQU 008030500h -ENDIF - -; AGESA_STATUS values -IFNDEF AGESA_SUCCESS - AGESA_SUCCESS EQU 0 -ENDIF -IFNDEF AGESA_WARNING - AGESA_WARNING EQU 4 -ENDIF -IFNDEF AGESA_FATAL - AGESA_FATAL EQU 7 -ENDIF -;;*************************************************************************** -;; -;; CPU MACROS - PUBLIC -;; -;;*************************************************************************** -_WRMSR macro - db 0Fh, 30h - endm - -_RDMSR macro - db 0Fh, 32h - endm - -AMD_CPUID MACRO arg0 - IFB <arg0> - mov eax, 1 - db 0Fh, 0A2h ; Execute instruction - bswap eax - xchg al, ah ; Ext model in al now - rol eax, 8 ; Ext model in ah, model in al - and ax, 0FFCFh ; Keep 23:16, 7:6, 3:0 - ELSE - mov eax, arg0 - db 0Fh, 0A2h - ENDIF -ENDM - - -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; none -; Outputs: -; none -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK MACRO - - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 - -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; none -; Outputs: -; none -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK MACRO - - AMD_DISABLE_STACK_FAMILY_HOOK_F10 - AMD_DISABLE_STACK_FAMILY_HOOK_F12 - AMD_DISABLE_STACK_FAMILY_HOOK_F14 - AMD_DISABLE_STACK_FAMILY_HOOK_F15 - -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI[7:0] = Core# (0..N, relative to node) -; SI[15:8]= Node# (0..N) -; SI[23:16]= reserved -; SI[24]= flag: 1=Family Unrecognized -; SI[25]= flag: 1=Interface re-entry call -; SI[26]= flag: 1=Core is primary of compute unit -; SI[31:27]= reserved, =0 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID MACRO - - mov si, -1 - GET_NODE_ID_CORE_ID_F10 - GET_NODE_ID_CORE_ID_F12 - GET_NODE_ID_CORE_ID_F14 - GET_NODE_ID_CORE_ID_F15 - ; - ; Check for unrecognized Family - ; - .if (si == -1) ; Has family (node/core) been discovered? - mov esi, ( (1 SHL FLAG_UNKNOWN_FAMILY)+(1 SHL FLAG_IS_PRIMARY) ) ; No, Set error code, Only let BSP continue - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (!carry?) - ; No, this is an AP - hlt ; Kill APs - .endif - .endif -ENDM - - - - -;;*************************************************************************** -;; Family 10h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; -; Family 10h requirements (BKDG section 2.3.3): -; * Paging disabled -; * MSRC001_0015[INVDWBINVD]=0 -; * MSRC001_1021[DIS_IND]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -; * MSRC001_1022[DIS_HW_PF]=1 -; * MSRC001_102A[IcDisSpecTlbWr]=1 -; * MSRC001_102A[ClLinesToNbDis]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F10 MACRO - local fam10_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz fam10_enable_stack_hook_exit ; Br if no - - ; Errata #385 - ; F3x1B8[23] = 1 before enabling L3 cache through CR0[30](CD) - mov eax, ebx ; Restore revision info to EAX - .if (al >= 80h) ; Is this Revision D and later? - mov ecx, NB_CFG ; MSR:C001_001F - _RDMSR ; EDX has EnableCf8ExtCfg bit - bts edx, (ENABLE_CF8_EXT_CFG - 32) - _WRMSR - - mov eax, esi ; Get node# from esi[15:8] - and eax, 0000FF00h - shl eax, (11 - 8) ; Device# - add eax, L3_CONTROL_REGISTER - mov dx, 0CF8h ; PCI Read - out dx, eax - mov dx, 0CFCh - in eax, dx - - or eax, (1 shl 23) ; F3x1B8[23] = 1 - - out dx, eax ; PCI Write - .endif - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DTLB reloads bit - bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Turn on Disable the self modifying code check buffer bit - bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit - _WRMSR - - dec cx ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative TLB reloads bit - bts eax, DIS_IND ; Turn on Disable indirect branch predictor - _WRMSR - - mov ecx, BU_CFG2 ; MSR C001_102A - _RDMSR - bts eax, F10_CL_LINES_TO_NB_DIS ; Allow BIOS ROM to be cached in the IC - bts edx, (IC_DIS_SPEC_TLB_WR-32) ;Disable speculative writes to the ITLB - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov eax, esi ; load core# - .if (al == 0) ; If (BSP) - mov ecx, PERF_COUNTER3 ; Select performance counter three - ; to count number of CAR evictions - xor eax, eax ; Initialize the lower part of the counter to zero - xor edx, edx ; Initializa the upper part of the counter to zero - _WRMSR ; Save it - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Get the current setting - and eax, PERF_CONTROL3_RESERVE_L ; Preserve the reserved bits - or eax, CONFIG_EVENT_L ; Set the lower part of event register to - ; select CAR Corruption occurred by any cores - and dx, PERF_CONTROL3_RESERVE_H ; Preserve the reserved bits - or dx, CONFIG_EVENT_H ; Set the upper part of event register - _WRMSR ; Save it - bts eax, EVENT_ENABLE ; Enable it - _WRMSR ; Save it - .endif ; endif - -fam10_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; -; Family 10h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1021[DIS_IND]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -; * MSRC001_102A[IcDisSpecTlbWr]=0 -; * MSRC001_102A[ClLinesToNbDis]=0 -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F10 MACRO - local fam10_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz fam10_disable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Enable speculative TLB reloads - btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Allow self modifying code check buffer - btr eax, DIS_HW_PF ; Allow hardware prefetches - _WRMSR - - dec cx ; MSR:C001_1021 - _RDMSR - btr eax, DIS_IND ; Turn on indirect branch predictor - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - _WRMSR - - mov ecx, BU_CFG2 ; MSR:C001_102A - _RDMSR - btr eax, F10_CL_LINES_TO_NB_DIS ; Return L3 to normal mode - btr edx, (IC_DIS_SPEC_TLB_WR-32) ;Re-enable speculative writes to the ITLB - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - mov ecx, HWCR ; MSR:0000_0015 - _RDMSR - mov bx, ax ; Save INVD -> WBINVD bit - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion for the invd instruction. - _WRMSR - invd ; Clear the cache tag RAMs - mov ax, bx ; Restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Retrieve the current value - btc eax, EVENT_ENABLE ; Is event enable, complement it as well - jnc fam10_disable_stack_hook_exit ; No - cmp ax, CONFIG_EVENT_L ; Is the lower part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit ; No - cmp dl, CONFIG_EVENT_H ; Is the upper part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit ; No - _WRMSR ; Disable the event - -fam10_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F10 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F10 MACRO - - local node_core_f10_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f10_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz node_core_f10_exit ; Br if no - - xor esi, esi ; Assume BSC, clear flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (carry?) - ; This is the BSP. - ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx - btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0 - out dx, eax - .else - ; This is an AP. Routing tables have been enabled by the HT Init process. - ; Also, the MailBox register was set by the BSP during early init - ; The Mailbox register content is formatted as follows: - ; UINT32 Node:4; // The node id of Core's node. - ; UINT32 Socket:4; // The socket of this Core's node. - ; UINT32 Module:2; // The internal module number for Core's node. - ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - ; UINT32 :20; // Reserved - ; - mov ecx, 0C0000408h ; Read the family 10h mailbox - _RDMSR ; MC4_MISC1[63:32] - mov si, dx ; SI = raw mailbox contents (will extract node# from this) - shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov di, bx ; DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID AMD_CPUID_APIC ; - shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core# - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG ; MSR:C001_001F - _RDMSR ; EDX has InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch - shr di, cl ; Right justify core number - .endif - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - movzx eax, si ; prepare return value (clears flags) - and ax, 000Fh ; AX = node number - shl ax, 8 ; [15:8]=node# - mov al, dl ; [7:0]=core# (relative to node) - mov esi, eax ; ESI = return value - .endif ; end: Is_AP - bts esi, FLAG_IS_PRIMARY ; all Family 10h cores are primary - -node_core_f10_exit: -ENDM - - -;;*************************************************************************** -;; Family 12h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; -; Family 12h requirements (BKDG section 2.3.3): -; The following requirements must be satisfied prior to using the cache as general storage: -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0 -; * MSRC001_1020[DIS_SS]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -; * MSRC001_1022[DIS_HW_PF]=1 -; * MSRC001_1029[ClflushSerialize]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F12 MACRO - local fam12_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz fam12_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative DC-TLB reloads - bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable self modifying code check buffer - bts eax, DIS_HW_PF ; Disable hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative IC-TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_SS ; Disabled Streaming store functionality - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov ecx, DE_CFG ; MSR:C001_1029 - _RDMSR - bts eax, CL_FLUSH_SERIALIZE ; Serialize all CL Flush actions - _WRMSR - -fam12_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; -; Family 12h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1020[DIS_SS]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -; * MSRC001_1029[ClflushSerialize]=0 -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F12 MACRO - local fam12_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz fam12_disable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads - btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Enable self modifying code check buffer - btr eax, DIS_HW_PF ; Enable Hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative IC-TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - btr eax, DIS_SS ; Turn on Streaming store functionality - _WRMSR - - mov ecx, DE_CFG ; MSR:C001_1029 - _RDMSR - btr eax, CL_FLUSH_SERIALIZE - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, HWCR ; MSR:0000_0015h - _RDMSR - mov bx, ax ; Save INVD -> WBINVD bit - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - mov ax, bx ; Restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - -fam12_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F12 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F12 MACRO - - local node_core_f12_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f12_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz node_core_f12_exit ; Br if no - - shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts ebx, FLAG_IS_PRIMARY ; all family 12h cores are primary - mov esi, ebx ; ESI = Node#=0, core number -node_core_f12_exit: -ENDM - - -;;*************************************************************************** -;; Family 14h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; -; Family 14h requirements (BKDG section 2.3.3): -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0. -; * MSRC001_1020[DisStreamSt]=1. -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. -; * MSRC001_1022[DIS_HW_PF]=1. -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F14 MACRO - local fam14_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz fam14_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DIS_HW_PF ; Disable hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_STREAM_ST ; Disabled Streaming store functionality - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - -fam14_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; -; Family 14h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1. -; * MSRC001_1020[DisStreamSt]=0. -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0. -; * MSRC001_1022[DIS_HW_PF]=0. -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F14 MACRO - local fam14_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz fam14_disable_stack_hook_exit ; Br if no - - mov ecx, LS_CFG ; MSR:C001_1020 - _RDMSR - btr eax, DIS_STREAM_ST ; Turn on Streaming store functionality - _WRMSR - - inc cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads - _WRMSR - - inc cx ;DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DIS_HW_PF ; Turn on hardware prefetches - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - bts eax, INVD_WBINVD ; Turn on Conversion of INVD to WBINVD - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - -fam14_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F14 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F14 MACRO - - local node_core_f14_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f14_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz node_core_f14_exit ; Br if no - - shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts ebx, FLAG_IS_PRIMARY ; all family 14h cores are primary - mov esi, ebx ; ESI = Node#=0, core number -node_core_f14_exit: -ENDM - - - -;;*************************************************************************** -;; Family 15h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; -; Family 15h requirements (BKDG #42301 section 2.3.3): -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0 -; * MSRC001_1020[DisSS]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DisHwPf]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F15 MACRO - local fam15_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz fam15_enable_stack_hook_exit ; Br if no - - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov ecx, LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_SS ; Turn on Streaming store functionality disabled bit - _WRMSR - - inc ecx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative IC-TLB reloads bit - _WRMSR - - inc ecx ;DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DC-TLB reloads bit - bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit - _WRMSR - - mov ecx, CU_CFG3 ; MSR:C001_102B - _RDMSR - btr edx, (COMBINE_CR0_CD - 32) ; Clear CombineCr0Cd bit - _WRMSR - -fam15_enable_stack_hook_exit: -ENDM - - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; -; Family 15h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1020[DisSS]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F15 MACRO - local fam15_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz fam15_disable_stack_hook_exit ; Br if no - - mov edi, ebx ; Save revision info to EDI - AMD_CPUID AMD_CPUID_APIC - mov al, cl ; AL = number of cores - 1 - shr cx, APIC_ID_CORE_ID_SIZE ; CL = ApicIdCoreIdSize - mov bx, 1 - shl bl, cl ; BL = theoretical number of cores on socket - dec bx ; BL = core number on socket mask - mov ah, bl ; AH = core number on socket mask - mov ebx, edi ; Restore revision info to EBX - mov di, ax ; DI[15:8] = core number mask, DI[7:0] = number of cores - 1 - - and ebx, 0F00FFh - mov eax, ebx - shr eax, 8 - or bx, ax ; Save Extended Model, Model and Stepping to BX - ; [11:8] = Extended Model, [7:4] = Model, [3:0] = Stepping - - ;; A handshake is required to ensure that all cores on a node invalidate in sync. - mov ecx, APIC_BASE_ADDRESS - _RDMSR - mov dx, bx ; Save Extended Model, Model and Stepping to DX - shl edx, 16 ; EDX[31:16] = Extended Model, Model and Stepping - mov ebx, eax ; EBX = LAPIC base - xor ecx, ecx ; Zero out CU flags - bts ecx, AMD_CU_NEED_TO_WAIT ; Default to waiting - bts ecx, AMD_CU_SEND_INVD_MSG ; Default to signaling - mov eax, CR0 - bt ax, CR0_PE ; Are we in protected mode? - .if (!carry?) - bts ecx, AMD_CU_RESTORE_ES ; Indicate ES restore is required - mov cx, es ; Save ES segment register to CX - xor ax, ax - mov es, ax ; Set ES to big real mode selector for 4GB access - .endif - - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bl, APIC_ID_REG - mov eax, es:[ebx] ; EAX[31:24] = APIC ID - shr eax, APIC20_APICID ; AL = APIC ID - mov ah, al ; AH = APIC ID - mov dx, di ; DH = core mask - and ah, dh ; AH = core number - .if (zero?) - ;; Core 0 of a socket - btr ecx, AMD_CU_SEND_INVD_MSG ; No need to signal after INVD - .if (dl != 0) - ;; This socket has multiple cores - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_MSG_REG - mov edi, APIC_MSG - mov es:[ebx], edi ; Signal for non core 0s to complete CAR breakdown - .else - btr ecx, AMD_CU_NEED_TO_WAIT ; No need to wait on a single core CPU - .endif - .endif - - bt ecx, AMD_CU_NEED_TO_WAIT - .if (carry?) - .if (ah == dl) - ;; This is the highest numbered core on this socket -- wait on core 0 - not dh ; Flip the mask to determine local core 0's APIC ID - and al, dh ; AL = target APIC ID - .else - ;; All other cores (including core 0) wait on the next highest core. - ;; In this way, cores will halt in a cascading fashion down to 0. - inc al - .endif - - shl eax, APIC20_APICID - and bx, 0F000h - or bx, APIC_CMD_HI_REG - mov es:[ebx], eax ; Set target APIC ID - - stc - .while (carry?) - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_CMD_LO_REG - mov eax, CMD_REG_TO_READ_DATA - mov es:[ebx], eax ; Fire remote read IPI - stc - .while (carry?) - mov eax, es:[ebx] - bt eax, DELIVERY_STS_BIT - .endw - stc - .while (carry?) - mov eax, es:[ebx] - and eax, REMOTE_READ_STS - .if (eax == REMOTE_DELIVERY_PEND) - stc - .else - clc - .endif - .endw - .if (eax == REMOTE_DELIVERY_DONE) - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bl, APIC_REMOTE_READ_REG - mov eax, es:[ebx] - .if (eax == APIC_MSG) - clc - .else - stc - .endif - .else - stc - .endif - .endw - .endif - bt ecx, AMD_CU_RESTORE_ES - .if (carry?) - mov es, cx - .endif - mov edi, ecx ; EDI = CU flags - shr edx, 16 - mov bx, dx ; Restore Extended Model, Model and Stepping - - ;; Handshaking complete. Continue tearing down CAR. - mov ecx, LS_CFG ; MSR:C001_1020 - .if (bx != 0) ; Is this OR A0? - _RDMSR - btr eax, DIS_SS ; Turn on Streaming store functionality - _WRMSR - .endif ; End workaround for errata 495 and 496 - - inc ecx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - _WRMSR - - inc ecx ;DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - .if (bx != 0) ; Is this OR A0? - btr eax, DIS_HW_PF ; Turn on hardware prefetches - .endif ; End workaround for erratum 498 - _WRMSR - - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - - ; Do Standard Family 15 work - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - bts eax, INVD_WBINVD ; Turn on INVD -> WBINVD conversion - _WRMSR - - mov ecx, CU_CFG3 ; MSR:C001_102B - _RDMSR - bts edx, (COMBINE_CR0_CD - 32) ; Set CombineCr0Cd bit - _WRMSR - - bt edi, AMD_CU_SEND_INVD_MSG - .if (carry?) - ;; Non core zero needs to signal to core 0 to proceed - mov ecx, APIC_BASE_ADDRESS - _RDMSR - mov ebx, eax ; EBX = LAPIC base - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_MSG_REG - mov eax, APIC_MSG - mov es:[ebx], eax ; Signal for core 0 to complete CAR breakdown - .endif - -fam15_disable_stack_hook_exit: -ENDM - - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F15 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F15 MACRO - - local node_core_f15_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f15_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz node_core_f15_exit ; Br if no - - xor esi, esi ; Assume BSC, clear local flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (carry?) - ; This is the BSP. - ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx - btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0 - out dx, eax - .else ; - ; This is an AP. Routing tables have been enabled by the HT Init process. - ; Also, the MailBox register was set by the BSP during early init - ; The Mailbox register content is formatted as follows: - ; UINT32 Node:4; // The node id of Core's node. - ; UINT32 Socket:4; // The socket of this Core's node. - ; UINT32 Module:2; // The internal module number for Core's node. - ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - ; UINT32 :20; // Reserved - ; - mov ecx, 0C0000408h ; Read the family 15h mailbox - _RDMSR ; MC4_MISC1[63:32] - mov si, dx ; SI = raw mailbox contents (will extract node# from this) - shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov di, bx ; DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID AMD_CPUID_APIC ; - shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core# - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG - _RDMSR ; EDX has InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch ; - shr di, cl ; Right justify core number - .endif ; - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - movzx eax, si ; Prepare return value - and ax, 000Fh ; AX = node number - shl ax, 8 ; [15:8]=node# - mov al, dl ; [7:0]=core# (relative to node) - mov esi, eax ; ESI = node-relative core number - .endif ; end - - ; - ; determine if this core shares MTRRs - ; - mov eax, 8000C580h ; Compute Unit Status - mov bx, si ; load node#(bh), core#(bl) - shl bh, 3 ; Move node# to PCI Dev# field - add ah, bh ; Adjust PCI adress for node number - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx ; [3:0]=Enabled; [19:16]=DualCore - - ; BL is MyCore# , BH is primary flag - mov cx, 06h ; Use CH as 'first of pair' core# - .while (cl > 0) - bt eax, 0 ; Is pair enabled? - .if (carry?) ; - mov bh, 01h ; flag core as primary - bt eax, 16 ; Is there a 2nd in the pair? - .if (carry?) ; - .break .if (ch == bl) ; Does 1st match MyCore#? - inc ch - xor bh, bh ; flag core as NOT primary - .break .if (ch == bl) ; Does 2nd match MyCore#? - .else ; No 2nd core - .break .if (ch == bl) ; Does 1st match MyCore#? - .endif - inc ch - .endif - shr eax, 1 - dec cl - .endw - .if (cl == 0) - ;Error - core# didn't match Compute Unit Status content - bts esi, FLAG_CORE_NOT_IDENTIFIED - bts esi, FLAG_IS_PRIMARY ; Set Is_Primary for unknowns - .endif - .if (bh != 0) ; Check state of primary for the matched core - bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value - .endif -node_core_f15_exit: -ENDM - - - diff --git a/src/vendorcode/amd/agesa/f14/cpcar.inc b/src/vendorcode/amd/agesa/f14/cpcar.inc deleted file mode 100644 index ce33f62..0000000 --- a/src/vendorcode/amd/agesa/f14/cpcar.inc +++ /dev/null @@ -1,1124 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; $Workfile:: cpcar.inc -; -; Description: CPCAR.INC - AGESA cache-as-RAM setup Include File -; -;***************************************************************************** -; -; Copyright (c) 2011, Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - -BSP_STACK_BASE_ADDR EQU 30000h ; Base address for primary cores stack -BSP_STACK_SIZE EQU 10000h ; 64KB for BSP core -CORE0_STACK_BASE_ADDR EQU 80000h ; Base address for primary cores stack -CORE0_STACK_SIZE EQU 4000h ; 16KB for primary cores -CORE1_STACK_BASE_ADDR EQU 40000h ; Base address for AP cores -CORE1_STACK_SIZE EQU 1000h ; 4KB for each AP cores - -APIC_BASE_ADDRESS EQU 0000001Bh - APIC_BSC EQU 8 ; Boot Strap Core - -AMD_MTRR_VARIABLE_BASE0 EQU 0200h -AMD_MTRR_VARIABLE_BASE6 EQU 020Ch -AMD_MTRR_FIX64k_00000 EQU 0250h -AMD_MTRR_FIX16k_80000 EQU 0258h -AMD_MTRR_FIX16k_A0000 EQU 0259h -AMD_MTRR_FIX4k_C0000 EQU 0268h -AMD_MTRR_FIX4k_C8000 EQU 0269h -AMD_MTRR_FIX4k_D0000 EQU 026Ah -AMD_MTRR_FIX4k_D8000 EQU 026Bh -AMD_MTRR_FIX4k_E0000 EQU 026Ch -AMD_MTRR_FIX4k_E8000 EQU 026Dh -AMD_MTRR_FIX4k_F0000 EQU 026Eh -AMD_MTRR_FIX4k_F8000 EQU 026Fh - -AMD_MTRR_DEFTYPE EQU 02FFh - WB_DRAM_TYPE EQU 1Eh ; MemType - memory type - MTRR_DEF_TYPE_EN EQU 11 ; MtrrDefTypeEn - variable and fixed MTRRs default enabled - MTRR_DEF_TYPE_FIX_EN EQU 10 ; MtrrDefTypeEn - fixed MTRRs default enabled - -HWCR EQU 0C0010015h ; Hardware Configuration - INVD_WBINVD EQU 4 ; INVD to WBINVD conversion - -IORR_BASE EQU 0C0010016h ; IO Range Regusters Base/Mask, 2 pairs - ; uses 16h - 19h -TOP_MEM EQU 0C001001Ah ; Top of Memory -TOP_MEM2 EQU 0C001001Dh ; Top of Memory2 - -LS_CFG EQU 0C0011020h ; Load-Store Configuration - DIS_SS EQU 28 ; Family 10h,12h,15h:Disable Streaming Store functionality - DIS_STREAM_ST EQU 28 ; Family 14h:DisStreamSt - Disable Streaming Store functionality - -IC_CFG EQU 0C0011021h ; Instruction Cache Config Register - IC_DIS_SPEC_TLB_RLD EQU 9 ; Disable speculative TLB reloads - DIS_IND EQU 14 ; Family 10-14h:Disable Indirect Branch Predictor - DIS_I_CACHE EQU 14 ; Family 15h:DisICache - Disable Indirect Branch Predictor - -DC_CFG EQU 0C0011022h ; Data Cache Configuration - DC_DIS_SPEC_TLB_RLD EQU 4 ; Disable speculative TLB reloads - DIS_CLR_WBTOL2_SMC_HIT EQU 8 ; self modifying code check buffer bit - DIS_HW_PF EQU 13 ; Hardware prefetches bit - -DE_CFG EQU 0C0011029h ; Decode Configuration - CL_FLUSH_SERIALIZE EQU 23 ; Family 12h,15h: CL Flush Serialization - -BU_CFG2 EQU 0C001102Ah ; Family 10h: Bus Unit Configuration 2 -CU_CFG2 EQU 0C001102Ah ; Family 15h: Combined Unit Configuration 2 - F10_CL_LINES_TO_NB_DIS EQU 15 ; ClLinesToNbDis - allows WP code to be cached in L2 - IC_DIS_SPEC_TLB_WR EQU 35 ; IcDisSpecTlbWr - ITLB speculative writes - -CU_CFG3 EQU 0C001102Bh ; Combined Unit Configuration 3 - COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit - - -CR0_PE EQU 0 ; Protection Enable -CR0_NW EQU 29 ; Not Write-through -CR0_CD EQU 30 ; Cache Disable -CR0_PG EQU 31 ; Paging Enable - -; CPUID Functions - -CPUID_MODEL EQU 1 -AMD_CPUID_FMF EQU 80000001h ; Family Model Features information -AMD_CPUID_APIC EQU 80000008h ; Long Mode and APIC info., core count - -NB_CFG EQU 0C001001Fh ; Northbridge Configuration Register - INIT_APIC_ID_CPU_ID_LO EQU 54 ; InitApicIdCpuIdLo - is core# in high or low half of APIC ID? - -MTRR_SYS_CFG EQU 0C0010010h ; System Configuration Register - CHX_TO_DIRTY_DIS EQU 16 ; ChxToDirtyDis Change to dirty disable - SYS_UC_LOCK_EN EQU 17 ; SysUcLockEn System lock command enable - MTRR_FIX_DRAM_EN EQU 18 ; MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable - MTRR_FIX_DRAM_MOD_EN EQU 19 ; MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable - MTRR_VAR_DRAM_EN EQU 20 ; MtrrVarDramEn MTRR variable DRAM enable - MTRR_TOM2_EN EQU 21 ; MtrrTom2En MTRR top of memory 2 enable - -PERF_CONTROL3 EQU 0C0010003h ; Performance event control three - PERF_CONTROL3_RESERVE_L EQU 00200000h ; Preserve the reserved bits - PERF_CONTROL3_RESERVE_H EQU 0FCF0h ; Preserve the reserved bits - CONFIG_EVENT_L EQU 0F0E2h ; All cores with level detection - CONFIG_EVENT_H EQU 4 ; Increment count by number of event - ; occured in clock cycle - EVENT_ENABLE EQU 22 ; Enable the event -PERF_COUNTER3 EQU 0C0010007h ; Performance event counter three - -; Local use flags, in upper most byte if ESI -FLAG_UNKNOWN_FAMILY EQU 24 ; Signals that the family# of the installed processor is not recognized -FLAG_STACK_REENTRY EQU 25 ; Signals that the environment has made a re-entry (2nd) call to set up the stack -FLAG_IS_PRIMARY EQU 26 ; Signals that this core is the primary within the comoute unit - -; AGESA_STATUS values -IFNDEF AGESA_SUCCESS - AGESA_SUCCESS EQU 0 -ENDIF -IFNDEF AGESA_WARNING - AGESA_WARNING EQU 4 -ENDIF -IFNDEF AGESA_FATAL - AGESA_FATAL EQU 7 -ENDIF -;;*************************************************************************** -;; -;; CPU MACROS - PUBLIC -;; -;;*************************************************************************** -_WRMSR macro - db 0Fh, 30h - endm - -_RDMSR macro - db 0Fh, 32h - endm - -AMD_CPUID MACRO arg0 - IFB <arg0> - mov eax, 1 - db 0Fh, 0A2h ; Execute instruction - bswap eax - xchg al, ah ; Ext model in al now - rol eax, 8 ; Ext model in ah, model in al - and ax, 0FFCFh ; Keep 23:16, 7:6, 3:0 - ELSE - mov eax, arg0 - db 0Fh, 0A2h - ENDIF -ENDM - - -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; none -; Outputs: -; none -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK MACRO - - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 - -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; none -; Outputs: -; none -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK MACRO - - AMD_DISABLE_STACK_FAMILY_HOOK_F10 - AMD_DISABLE_STACK_FAMILY_HOOK_F12 - AMD_DISABLE_STACK_FAMILY_HOOK_F14 - AMD_DISABLE_STACK_FAMILY_HOOK_F15 - -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI[7:0] = Core# (0..N, relative to node) -; SI[15:8]= Node# (0..N) -; SI[23:16]= reserved -; SI[24]= flag: 1=Family Unrecognized -; SI[25]= flag: 1=Interface re-entry call -; SI[26]= flag: 1=Core is primary of compute unit -; SI[31:27]= reserved, =0 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID MACRO - - mov si, -1 - GET_NODE_ID_CORE_ID_F10 - GET_NODE_ID_CORE_ID_F12 - GET_NODE_ID_CORE_ID_F14 - GET_NODE_ID_CORE_ID_F15 - ; - ; Check for unrecognized Family - ; - .if (si == -1) ; Has family (node/core) been discovered? - mov esi, ( (1 SHL FLAG_UNKNOWN_FAMILY)+(1 SHL FLAG_IS_PRIMARY) ) ; No, Set error code, Only let BSP continue - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (!carry?) - ; No, this is an AP - hlt ; Kill APs - .endif - .endif -ENDM - - - - -;;*************************************************************************** -;; Family 10h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; -; Family 10h requirements (BKDG section 2.3.3): -; * Paging disabled -; * MSRC001_0015[INVDWBINVD]=0 -; * MSRC001_1021[DIS_IND]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -; * MSRC001_1022[DIS_HW_PF]=1 -; * MSRC001_102A[IcDisSpecTlbWr]=1 -; * MSRC001_102A[ClLinesToNbDis]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F10 MACRO - local fam10_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz fam10_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DTLB reloads bit - bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Turn on Disable the self modifying code check buffer bit - bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit - _WRMSR - - dec cx ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative TLB reloads bit - bts eax, DIS_IND ; Turn on Disable indirect branch predictor - _WRMSR - - mov ecx, BU_CFG2 ; MSR C001_102A - _RDMSR - bts eax, F10_CL_LINES_TO_NB_DIS ; Allow BIOS ROM to be cached in the IC - bts edx, (IC_DIS_SPEC_TLB_WR-32) ;Disable speculative writes to the ITLB - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov eax, esi ; load core# - .if (al == 0) ; If (BSP) - mov ecx, PERF_COUNTER3 ; Select performance counter three - ; to count number of CAR evictions - xor eax, eax ; Initialize the lower part of the counter to zero - xor edx, edx ; Initializa the upper part of the counter to zero - _WRMSR ; Save it - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Get the current setting - and eax, PERF_CONTROL3_RESERVE_L ; Preserve the reserved bits - or eax, CONFIG_EVENT_L ; Set the lower part of event register to - ; select CAR Corruption occurred by any cores - and dx, PERF_CONTROL3_RESERVE_H ; Preserve the reserved bits - or dx, CONFIG_EVENT_H ; Set the upper part of event register - _WRMSR ; Save it - bts eax, EVENT_ENABLE ; Enable it - _WRMSR ; Save it - .endif ; endif - -fam10_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; -; Family 10h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1021[DIS_IND]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -; * MSRC001_102A[IcDisSpecTlbWr]=0 -; * MSRC001_102A[ClLinesToNbDis]=0 -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F10 MACRO - local fam10_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz fam10_disable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Enable speculative TLB reloads - btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Allow self modifying code check buffer - btr eax, DIS_HW_PF ; Allow hardware prefetches - _WRMSR - - dec cx ; MSR:C001_1021 - _RDMSR - btr eax, DIS_IND ; Turn on indirect branch predictor - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - _WRMSR - - mov ecx, BU_CFG2 ; MSR:C001_102A - _RDMSR - btr eax, F10_CL_LINES_TO_NB_DIS ; Return L3 to normal mode - btr edx, (IC_DIS_SPEC_TLB_WR-32) ;Re-enable speculative writes to the ITLB - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - mov ecx, HWCR ; MSR:0000_0015 - _RDMSR - mov bx, ax ; Save INVD -> WBINVD bit - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion for the invd instruction. - _WRMSR - invd ; Clear the cache tag RAMs - mov ax, bx ; Restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Retrieve the current value - btc eax, EVENT_ENABLE ; Is event enable, complement it as well - jnc fam10_disable_stack_hook_exit ; No - cmp ax, CONFIG_EVENT_L ; Is the lower part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit ; No - cmp dl, CONFIG_EVENT_H ; Is the upper part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit ; No - _WRMSR ; Disable the event - -fam10_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F10 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F10 MACRO - - local node_core_f10_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f10_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz node_core_f10_exit ; Br if no - - xor esi, esi ; Assume BSC, clear flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (carry?) - ; This is the BSP. - ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx - btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0 - out dx, eax - .else - ; This is an AP. Routing tables have been enabled by the HT Init process. - ; Also, the MailBox register was set by the BSP during early init - ; The Mailbox register content is formatted as follows: - ; UINT32 Node:4; // The node id of Core's node. - ; UINT32 Socket:4; // The socket of this Core's node. - ; UINT32 Module:2; // The internal module number for Core's node. - ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - ; UINT32 :20; // Reserved - ; - mov ecx, 0C0000408h ; Read the family 10h mailbox - _RDMSR ; MC4_MISC1[63:32] - mov si, dx ; SI = raw mailbox contents (will extract node# from this) - shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov di, bx ; DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID AMD_CPUID_APIC ; - shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core# - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG ; MSR:C001_001F - _RDMSR ; EDX has InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch - shr di, cl ; Right justify core number - .endif - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - movzx eax, si ; prepare return value (clears flags) - and ax, 000Fh ; AX = node number - shl ax, 8 ; [15:8]=node# - mov al, dl ; [7:0]=core# (relative to node) - mov esi, eax ; ESI = return value - .endif ; end: Is_AP - bts esi, FLAG_IS_PRIMARY ; all Family 10h cores are primary - -node_core_f10_exit: -ENDM - - -;;*************************************************************************** -;; Family 12h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; -; Family 12h requirements (BKDG section 2.3.3): -; The following requirements must be satisfied prior to using the cache as general storage: -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0 -; * MSRC001_1020[DIS_SS]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -; * MSRC001_1022[DIS_HW_PF]=1 -; * MSRC001_1029[ClflushSerialize]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F12 MACRO - local fam12_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz fam12_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative DC-TLB reloads - bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable self modifying code check buffer - bts eax, DIS_HW_PF ; Disable hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative IC-TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_SS ; Disabled Streaming store functionality - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov ecx, DE_CFG ; MSR:C001_1029 - _RDMSR - bts eax, CL_FLUSH_SERIALIZE ; Serialize all CL Flush actions - _WRMSR - -fam12_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; -; Family 12h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1020[DIS_SS]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -; * MSRC001_1029[ClflushSerialize]=0 -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F12 MACRO - local fam12_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz fam12_disable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads - btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Enable self modifying code check buffer - btr eax, DIS_HW_PF ; Enable Hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative IC-TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - btr eax, DIS_SS ; Turn on Streaming store functionality - _WRMSR - - mov ecx, DE_CFG ; MSR:C001_1029 - _RDMSR - btr eax, CL_FLUSH_SERIALIZE - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, HWCR ; MSR:0000_0015h - _RDMSR - mov bx, ax ; Save INVD -> WBINVD bit - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - mov ax, bx ; Restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - -fam12_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F12 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F12 MACRO - - local node_core_f12_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f12_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz node_core_f12_exit ; Br if no - - shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts ebx, FLAG_IS_PRIMARY ; all family 12h cores are primary - mov esi, ebx ; ESI = Node#=0, core number -node_core_f12_exit: -ENDM - - -;;*************************************************************************** -;; Family 14h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; -; Family 14h requirements (BKDG section 2.3.3): -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0. -; * MSRC001_1020[DisStreamSt]=1. -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. -; * MSRC001_1022[DIS_HW_PF]=1. -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F14 MACRO - local fam14_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz fam14_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DIS_HW_PF ; Disable hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_STREAM_ST ; Disabled Streaming store functionality - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - -fam14_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; -; Family 14h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1. -; * MSRC001_1020[DisStreamSt]=0. -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0. -; * MSRC001_1022[DIS_HW_PF]=0. -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F14 MACRO - local fam14_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz fam14_disable_stack_hook_exit ; Br if no - - mov ecx, LS_CFG ; MSR:C001_1020 - _RDMSR - btr eax, DIS_STREAM_ST ; Turn on Streaming store functionality - _WRMSR - - inc cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads - _WRMSR - - inc cx ;DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DIS_HW_PF ; Turn on hardware prefetches - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - bts eax, INVD_WBINVD ; Turn on Conversion of INVD to WBINVD - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - -fam14_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F14 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F14 MACRO - - local node_core_f14_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f14_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz node_core_f14_exit ; Br if no - - xor esi, esi ; Node must be 0 - bts esi, FLAG_IS_PRIMARY ; all family 14h cores are primary - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; - .if (!carry?) ; Is this the BSC? - ; No, this is an AP - inc si ; Set core to 1 - .endif ; -node_core_f14_exit: -ENDM - - - -;;*************************************************************************** -;; Family 15h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; -; Family 15h requirements (BKDG #42301 section 2.3.3): -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0 -; * MSRC001_1020[DisSS]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DisHwPf]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F15 MACRO - local fam15_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz fam15_enable_stack_hook_exit ; Br if no - - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov ecx, LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_SS ; Turn on Streaming store functionality disabled bit - _WRMSR - - inc ecx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative IC-TLB reloads bit - _WRMSR - - inc ecx ;DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DC-TLB reloads bit - bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit - _WRMSR - - mov ecx, CU_CFG3 ; MSR:C001_102B - _RDMSR - btr edx, (COMBINE_CR0_CD - 32) ; Clear CombineCr0Cd bit - _WRMSR - -fam15_enable_stack_hook_exit: -ENDM - - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; -; Family 15h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1020[DisSS]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F15 MACRO - local fam15_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz fam15_disable_stack_hook_exit ; Br if no - - mov ecx, LS_CFG ; MSR:C001_1020 - .if (ebx != 00600F00h) ; Is this rev A0? - _RDMSR - btr eax, DIS_SS ; Turn on Streaming store functionality - _WRMSR - .endif ; End workaround for errata 495 and 496 - - inc ecx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - _WRMSR - - inc ecx ;DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - .if (ebx != 00600F00h) ; Is this rev A0? - btr eax, DIS_HW_PF ; Turn on hardware prefetches - .endif ; End workaround for erratum 498 - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - bt esi, FLAG_IS_PRIMARY - .if (carry?) ; Only clear cache from primary core - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - bts eax, INVD_WBINVD ; Turn on Conversion of INVD to WBINVD - _WRMSR - .endif ; end - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, CU_CFG3 ; MSR:C001_102B - _RDMSR - bts edx, (COMBINE_CR0_CD - 32) ; Set CombineCr0Cd bit - _WRMSR - -fam15_disable_stack_hook_exit: -ENDM - - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F15 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F15 MACRO - - local node_core_f15_exit - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f15_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz node_core_f15_exit ; Br if no - - xor esi, esi ; Assume BSC, clear local flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (carry?) - ; This is the BSP. - ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx - btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0 - out dx, eax - .else ; - ; This is an AP. Routing tables have been enabled by the HT Init process. - ; Also, the MailBox register was set by the BSP during early init - ; The Mailbox register content is formatted as follows: - ; UINT32 Node:4; // The node id of Core's node. - ; UINT32 Socket:4; // The socket of this Core's node. - ; UINT32 Module:2; // The internal module number for Core's node. - ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - ; UINT32 :20; // Reserved - ; - mov ecx, 0C0000408h ; Read the family 15h mailbox - _RDMSR ; MC4_MISC1[63:32] - mov si, dx ; SI = raw mailbox contents (will extract node# from this) - shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov di, bx ; DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID AMD_CPUID_APIC ; - shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core# - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG - _RDMSR ; EDX has InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch ; - shr di, cl ; Right justify core number - .endif ; - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - movzx eax, si ; Prepare return value - and ax, 000Fh ; AX = node number - shl ax, 8 ; [15:8]=node# - mov al, dl ; [7:0]=core# (relative to node) - mov esi, eax ; ESI = node-relative core number - .endif ; end - - ; - ; determine if this core shares MTRRs - ; - mov eax, 8000C580h ; Compute Unit Status - mov bx, si ; load node#(bh), core#(bl) - shl bh, 3 ; Move node# to PCI Dev# field - add ah, bh ; Adjust PCI adress for node number - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx ; [3:0]=Enabled; [19:16]=DualCore - ; - ; BL is MyCore# , BH is primary flag - mov cx, 06h ; Use CH as 'first of pair' core# - .while (cl > 0) - bt eax, 0 ; Is pair enabled? - .if (carry?) ; - mov bh, 01h ; flag core as primary - bt eax, 16 ; Is there a 2nd in the pair? - .if (carry?) ; - .break .if (ch == bl) ; Does 1st match MyCore#? - inc ch - xor bh, bh ; flag core as NOT primary - .break .if (ch == bl) ; Does 2nd match MyCore#? - .else ; No 2nd core - .break .if (ch == bl) ; Does 1st match MyCore#? - .endif - inc ch - .endif - shr eax, 1 - dec cl - .endw - .if (cl == 0) - ;Error - core# didn't match Compute Unit Status content - bts esi, FLAG_UNKNOWN_FAMILY - bts esi, FLAG_IS_PRIMARY ; Set Is_Primary for unknowns - .endif - .if (bh != 0) ; Check state of primary for the matched core - bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value - .endif - ; -node_core_f15_exit: -ENDM - - - diff --git a/src/vendorcode/amd/agesa/f15/cpcar.inc b/src/vendorcode/amd/agesa/f15/cpcar.inc deleted file mode 100644 index 544cc64..0000000 --- a/src/vendorcode/amd/agesa/f15/cpcar.inc +++ /dev/null @@ -1,1470 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; $Workfile:: cpcar.inc -; -; Description: CPCAR.INC - AGESA cache-as-RAM setup Include File -; -;***************************************************************************** -; -; Copyright (C) 2012 Advanced Micro Devices, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; * Neither the name of Advanced Micro Devices, Inc. nor the names of -; its contributors may be used to endorse or promote products derived -; from this software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY -; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;***************************************************************************** - .LIST - .mmx - -BSP_STACK_BASE_ADDR EQU 30000h ; Base address for primary cores stack -BSP_STACK_SIZE_64K EQU 10000h ; 64KB for BSP core -BSP_STACK_SIZE_32K EQU 8000h ; 32KB for BSP core -CORE0_STACK_BASE_ADDR EQU 80000h ; Base address for primary cores stack -CORE0_STACK_SIZE EQU 4000h ; 16KB for primary cores -CORE1_STACK_BASE_ADDR EQU 40000h ; Base address for AP cores -CORE1_STACK_SIZE EQU 1000h ; 4KB for each AP cores - -L3_CONTROL_REGISTER EQU 8100C3B8h ; Bus 0, Device 18h, Function 3, Offset 1B8h - -APIC_BASE_ADDRESS EQU 0000001Bh - APIC_BSC EQU 8 ; Boot Strap Core - -APIC_MSG_REG EQU 380h ; Location of BSC message - APIC_MSG EQU 00DE00ADh ; Message data -APIC_CMD_LO_REG EQU 300h ; APIC command low -APIC_CMD_HI_REG EQU 310h ; APIC command high - CMD_REG_TO_READ_DATA EQU 00000338h ; APIC command for remote read of APIC_MSG_REG - REMOTE_READ_STS EQU 00030000h ; Remote read status mask - REMOTE_DELIVERY_PEND EQU 00010000h ; Remote read is pending - REMOTE_DELIVERY_DONE EQU 00020000h ; Remote read is complete - DELIVERY_STS_BIT EQU 12 ; Delivery status valid bit -APIC_ID_REG EQU 0020h ; Local APIC ID offset - APIC20_APICID EQU 24 -APIC_REMOTE_READ_REG EQU 00C0h ; Remote read offset - -; Flags can only run from bits 31 to 24. Bits 23:0 are in use. -AMD_CU_NEED_TO_WAIT EQU 31 -AMD_CU_SEND_INVD_MSG EQU 30 -AMD_CU_RESTORE_ES EQU 29 - -AMD_MTRR_VARIABLE_BASE0 EQU 0200h -AMD_MTRR_VARIABLE_BASE6 EQU 020Ch -AMD_MTRR_VARIABLE_BASE7 EQU 020Eh - VMTRR_VALID EQU 11 - MTRR_TYPE_WB EQU 06h - MTRR_TYPE_WP EQU 05h - MTRR_TYPE_WT EQU 04h - MTRR_TYPE_UC EQU 00h -AMD_MTRR_VARIABLE_MASK7 EQU 020Fh -AMD_MTRR_FIX64k_00000 EQU 0250h -AMD_MTRR_FIX16k_80000 EQU 0258h -AMD_MTRR_FIX16k_A0000 EQU 0259h -AMD_MTRR_FIX4k_C0000 EQU 0268h -AMD_MTRR_FIX4k_C8000 EQU 0269h -AMD_MTRR_FIX4k_D0000 EQU 026Ah -AMD_MTRR_FIX4k_D8000 EQU 026Bh -AMD_MTRR_FIX4k_E0000 EQU 026Ch -AMD_MTRR_FIX4k_E8000 EQU 026Dh -AMD_MTRR_FIX4k_F0000 EQU 026Eh -AMD_MTRR_FIX4k_F8000 EQU 026Fh - -AMD_MTRR_DEFTYPE EQU 02FFh - WB_DRAM_TYPE EQU 1Eh ; MemType - memory type - MTRR_DEF_TYPE_EN EQU 11 ; MtrrDefTypeEn - variable and fixed MTRRs default enabled - MTRR_DEF_TYPE_FIX_EN EQU 10 ; MtrrDefTypeEn - fixed MTRRs default enabled - -HWCR EQU 0C0010015h ; Hardware Configuration - INVD_WBINVD EQU 4 ; INVD to WBINVD conversion - -IORR_BASE EQU 0C0010016h ; IO Range Regusters Base/Mask, 2 pairs - ; uses 16h - 19h -TOP_MEM EQU 0C001001Ah ; Top of Memory -TOP_MEM2 EQU 0C001001Dh ; Top of Memory2 - -LS_CFG EQU 0C0011020h ; Load-Store Configuration - DIS_SS EQU 28 ; Family 10h,12h,15h:Disable Streaming Store functionality - DIS_STREAM_ST EQU 28 ; Family 14h:DisStreamSt - Disable Streaming Store functionality - -IC_CFG EQU 0C0011021h ; Instruction Cache Config Register - IC_DIS_SPEC_TLB_RLD EQU 9 ; Disable speculative TLB reloads - DIS_IND EQU 14 ; Family 10-14h:Disable Indirect Branch Predictor - DIS_I_CACHE EQU 14 ; Family 15h:DisICache - Disable Indirect Branch Predictor - -DC_CFG EQU 0C0011022h ; Data Cache Configuration - DC_DIS_SPEC_TLB_RLD EQU 4 ; Disable speculative TLB reloads - DIS_CLR_WBTOL2_SMC_HIT EQU 8 ; self modifying code check buffer bit - DIS_HW_PF EQU 13 ; Hardware prefetches bit - -CU_CFG EQU 0C0011023h ; Family 15h: Combined Unit Configuration - L2_WAY_LOCK_EN EQU 23 ; L2WayLock - L2 way lock enable - L2_FIRST_LOCKED_WAY EQU 19 ; L2FirstLockedWay - first L2 way lockedh - L2_FIRST_LOCKED_WAY_OR_MASK EQU 000780000h - -DE_CFG EQU 0C0011029h ; Decode Configuration - CL_FLUSH_SERIALIZE EQU 23 ; Family 12h,15h: CL Flush Serialization - -BU_CFG2 EQU 0C001102Ah ; Family 10h-14h: Bus Unit Configuration 2 -CU_CFG2 EQU 0C001102Ah ; Family 15h: Combined Unit Configuration 2 - F10_CL_LINES_TO_NB_DIS EQU 15 ; ClLinesToNbDis - allows WP code to be cached in L2 - IC_DIS_SPEC_TLB_WR EQU 35 ; IcDisSpecTlbWr - ITLB speculative writes - -CU_CFG3 EQU 0C001102Bh ; Combined Unit Configuration 3 - COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit - - -CR0_PE EQU 0 ; Protection Enable -CR0_NW EQU 29 ; Not Write-through -CR0_CD EQU 30 ; Cache Disable -CR0_PG EQU 31 ; Paging Enable - -; CPUID Functions - -CPUID_MODEL EQU 1 -AMD_CPUID_FMF EQU 80000001h ; Family Model Features information -AMD_CPUID_L2Cache EQU 80000006h ; L2/L3 cache info -AMD_CPUID_APIC EQU 80000008h ; Long Mode and APIC info., core count - APIC_ID_CORE_ID_SIZE EQU 12 ; ApicIdCoreIdSize bit position - -NB_CFG EQU 0C001001Fh ; Northbridge Configuration Register - INIT_APIC_ID_CPU_ID_LO EQU 54 ; InitApicIdCpuIdLo - is core# in high or low half of APIC ID? - ENABLE_CF8_EXT_CFG EQU 46 ; EnableCf8ExtCfg - enable CF8 extended configuration cycles - -MTRR_SYS_CFG EQU 0C0010010h ; System Configuration Register - CHX_TO_DIRTY_DIS EQU 16 ; ChxToDirtyDis Change to dirty disable - SYS_UC_LOCK_EN EQU 17 ; SysUcLockEn System lock command enable - MTRR_FIX_DRAM_EN EQU 18 ; MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable - MTRR_FIX_DRAM_MOD_EN EQU 19 ; MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable - MTRR_VAR_DRAM_EN EQU 20 ; MtrrVarDramEn MTRR variable DRAM enable - MTRR_TOM2_EN EQU 21 ; MtrrTom2En MTRR top of memory 2 enable - -PERF_CONTROL3 EQU 0C0010003h ; Performance event control three - PERF_CONTROL3_RESERVE_L EQU 00200000h ; Preserve the reserved bits - PERF_CONTROL3_RESERVE_H EQU 0FCF0h ; Preserve the reserved bits - CONFIG_EVENT_L EQU 0F0E2h ; All cores with level detection - CONFIG_EVENT_H EQU 4 ; Increment count by number of event - ; occured in clock cycle - EVENT_ENABLE EQU 22 ; Enable the event -PERF_COUNTER3 EQU 0C0010007h ; Performance event counter three - -; Local use flags, in upper most byte of ESI -FLAG_UNKNOWN_FAMILY EQU 24 ; Signals that the family# of the installed processor is not recognized -FLAG_STACK_REENTRY EQU 25 ; Signals that the environment has made a re-entry (2nd) call to set up the stack -FLAG_IS_PRIMARY EQU 26 ; Signals that this core is the primary within the compute unit -FLAG_CORE_NOT_IDENTIFIED EQU 27 ; Signals that the cores/compute units of the installed processor is not recognized -FLAG_FORCE_32K_STACK EQU 28 ; Signals that to force 32KB stack size for BSP core - -; Error code returned in EDX by AMD_ENABLE_STACK -IFNDEF CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY - CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY EQU 008010500h -ENDIF -IFNDEF CPU_EVENT_STACK_REENTRY - CPU_EVENT_STACK_REENTRY EQU 008020500h -ENDIF -IFNDEF CPU_EVENT_CORE_NOT_IDENTIFIED - CPU_EVENT_CORE_NOT_IDENTIFIED EQU 008030500h -ENDIF - -; AGESA_STATUS values -IFNDEF AGESA_SUCCESS - AGESA_SUCCESS EQU 0 -ENDIF -IFNDEF AGESA_WARNING - AGESA_WARNING EQU 4 -ENDIF -IFNDEF AGESA_FATAL - AGESA_FATAL EQU 7 -ENDIF -;;*************************************************************************** -;; -;; CPU MACROS - PUBLIC -;; -;;*************************************************************************** -_WRMSR macro - db 0Fh, 30h - endm - -_RDMSR macro - db 0Fh, 32h - endm - -AMD_CPUID MACRO arg0 - IFB <arg0> - mov eax, 1 - db 0Fh, 0A2h ; Execute instruction - bswap eax - xchg al, ah ; Ext model in al now - rol eax, 8 ; Ext model in ah, model in al - and ax, 0FFCFh ; Keep 23:16, 7:6, 3:0 - ELSE - mov eax, arg0 - db 0Fh, 0A2h - ENDIF -ENDM - -;--------------------------------------------------- -; LoadTableAddress -; Due to the various assembly methodologies used by BIOS vendors, this macro is needed to abstract the -; loading of the address of a table. The default is the standard LEA instruction with table address. -; The IBV that needs to use an alternative method can define their version of the macro prior to including -; this file into their source. -; An alternative example: -; LoadTableAddress MACRO MyTable -; LEA eax, -(LAST_ADDRESS - MyTable) -;--------------------------------------------------- -IFNDEF LoadTableAddress - LoadTableAddress Macro TargetTable - LEA eax, TargetTable - ENDM -ENDIF - - -;;*************************************************************************** -;; -;; CPU STRUCTURES - PUBLIC -;; -;;*************************************************************************** -CPU_FAMILY_INFO STRUC - L2_MIN_SIZE WORD ? ; Minimum size of the L2 cache for this family, in K - NUM_SHARED_CORES BYTE ? ; Number of cores sharing an L2 cache - L2_ALLOC_MEM BYTE ? ; L2 space reserved for memory training, in K - L2_ALLOC_EXE WORD ? ; L2 space reserved for EXE CACHE, in K. 0 means unlimited. - SIZE_ADDRESS_BUS BYTE ? ; Number of address bits supported by this family - FAMILY_RESERVED BYTE ? ; reserved, pad to DWORD size -CPU_FAMILY_INFO ENDS - - -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK MACRO - - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 - -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK MACRO - - AMD_DISABLE_STACK_FAMILY_HOOK_F10 - AMD_DISABLE_STACK_FAMILY_HOOK_F12 - AMD_DISABLE_STACK_FAMILY_HOOK_F14 - AMD_DISABLE_STACK_FAMILY_HOOK_F15 - -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI[7:0] = Core# (0..N, relative to node) -; SI[15:8]= Node# (0..N) -; SI[23:16]= reserved -; SI[24]= flag: 1=Family Unrecognized -; SI[25]= flag: 1=Interface re-entry call -; SI[26]= flag: 1=Core is primary of compute unit -; SI[31:27]= reserved, =0 -; -; Destroyed: -; eax, ebx, ecx, edx, esi -;--------------------------------------------------- -GET_NODE_ID_CORE_ID MACRO - - mov si, -1 - GET_NODE_ID_CORE_ID_F10 - GET_NODE_ID_CORE_ID_F12 - GET_NODE_ID_CORE_ID_F14 - GET_NODE_ID_CORE_ID_F15 - ; - ; Check for unrecognized Family - ; - .if (si == -1) ; Has family (node/core) been discovered? - mov esi, ( (1 SHL FLAG_UNKNOWN_FAMILY)+(1 SHL FLAG_IS_PRIMARY) ) ; No, Set error code, Only let BSP continue - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (!carry?) - ; No, this is an AP - hlt ; Kill APs - .endif - .endif -ENDM - - - - -;;*************************************************************************** -;; Family 10h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 10h requirements (BKDG section 2.3.3): -; * Paging disabled -; * MSRC001_0015[INVDWBINVD]=0 -; * MSRC001_1021[DIS_IND]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -; * MSRC001_1022[DIS_HW_PF]=1 -; * MSRC001_102A[IcDisSpecTlbWr]=1 -; * MSRC001_102A[ClLinesToNbDis]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F10 MACRO - local fam10_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz fam10_enable_stack_hook_exit ; Br if no - - ; Errata #385 - ; F3x1B8[23] = 1 before enabling L3 cache through CR0[30](CD) - mov eax, ebx ; Restore revision info to EAX - .if (al >= 80h) ; Is this Revision D and later? - mov ecx, NB_CFG ; MSR:C001_001F - _RDMSR ; EDX has EnableCf8ExtCfg bit - bts edx, (ENABLE_CF8_EXT_CFG - 32) - _WRMSR - - mov eax, esi ; Get node# from esi[15:8] - and eax, 0000FF00h - shl eax, (11 - 8) ; Device# - add eax, L3_CONTROL_REGISTER - mov dx, 0CF8h ; PCI Read - out dx, eax - mov dx, 0CFCh - in eax, dx - - or eax, (1 shl 23) ; F3x1B8[23] = 1 - - out dx, eax ; PCI Write - .endif - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DTLB reloads bit - bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Turn on Disable the self modifying code check buffer bit - bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit - _WRMSR - - dec cx ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative TLB reloads bit - bts eax, DIS_IND ; Turn on Disable indirect branch predictor - _WRMSR - - mov ecx, BU_CFG2 ; MSR C001_102A - _RDMSR - bts eax, F10_CL_LINES_TO_NB_DIS ; Allow BIOS ROM to be cached in the IC - bts edx, (IC_DIS_SPEC_TLB_WR-32) ;Disable speculative writes to the ITLB - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov eax, esi ; load core# - .if (al == 0) ; If (BSP) - mov ecx, PERF_COUNTER3 ; Select performance counter three - ; to count number of CAR evictions - xor eax, eax ; Initialize the lower part of the counter to zero - xor edx, edx ; Initializa the upper part of the counter to zero - _WRMSR ; Save it - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Get the current setting - and eax, PERF_CONTROL3_RESERVE_L ; Preserve the reserved bits - or eax, CONFIG_EVENT_L ; Set the lower part of event register to - ; select CAR Corruption occurred by any cores - and dx, PERF_CONTROL3_RESERVE_H ; Preserve the reserved bits - or dx, CONFIG_EVENT_H ; Set the upper part of event register - _WRMSR ; Save it - bts eax, EVENT_ENABLE ; Enable it - _WRMSR ; Save it - .endif ; endif - -fam10_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 10h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1021[DIS_IND]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -; * MSRC001_102A[IcDisSpecTlbWr]=0 -; * MSRC001_102A[ClLinesToNbDis]=0 -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F10 MACRO - local fam10_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz fam10_disable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Enable speculative TLB reloads - btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Allow self modifying code check buffer - btr eax, DIS_HW_PF ; Allow hardware prefetches - _WRMSR - - dec cx ; MSR:C001_1021 - _RDMSR - btr eax, DIS_IND ; Turn on indirect branch predictor - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - _WRMSR - - mov ecx, BU_CFG2 ; MSR:C001_102A - _RDMSR - btr eax, F10_CL_LINES_TO_NB_DIS ; Return L3 to normal mode - btr edx, (IC_DIS_SPEC_TLB_WR-32) ;Re-enable speculative writes to the ITLB - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - mov ecx, HWCR ; MSR:0000_0015 - _RDMSR - mov bx, ax ; Save INVD -> WBINVD bit - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion for the invd instruction. - _WRMSR - invd ; Clear the cache tag RAMs - mov ax, bx ; Restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Retrieve the current value - btc eax, EVENT_ENABLE ; Is event enable, complement it as well - jnc fam10_disable_stack_hook_exit ; No - cmp ax, CONFIG_EVENT_L ; Is the lower part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit ; No - cmp dl, CONFIG_EVENT_H ; Is the upper part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit ; No - _WRMSR ; Disable the event - -fam10_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F10 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F10 MACRO - - local node_core_f10_exit - local end_of_f10h_data - - IFNDEF FAM10H_INFO_STRUCT - jmp end_of_f10h_data - ; Family 10h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - FAM10H_INFO_STRUCT CPU_FAMILY_INFO { 512, 1, 16, 384, 48, 0} -end_of_f10h_data: - ENDIF - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f10_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz node_core_f10_exit ; Br if no - - LoadTableAddress(FAM10H_INFO_STRUCT) - movd mm5, eax ; load pointer to Family Info Struc - - xor esi, esi ; Assume BSC, clear flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (carry?) - ; This is the BSP. - ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx - btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0 - out dx, eax - .else - ; This is an AP. Routing tables have been enabled by the HT Init process. - ; Also, the MailBox register was set by the BSP during early init - ; The Mailbox register content is formatted as follows: - ; UINT32 Node:4; // The node id of Core's node. - ; UINT32 Socket:4; // The socket of this Core's node. - ; UINT32 Module:2; // The internal module number for Core's node. - ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - ; UINT32 :20; // Reserved - ; - mov ecx, 0C0000408h ; Read the family 10h mailbox - _RDMSR ; MC4_MISC1[63:32] - mov si, dx ; SI = raw mailbox contents (will extract node# from this) - shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov di, bx ; DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID AMD_CPUID_APIC ; - shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core# - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG ; MSR:C001_001F - _RDMSR ; EDX has InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch - shr di, cl ; Right justify core number - .endif - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - movzx eax, si ; prepare return value (clears flags) - and ax, 000Fh ; AX = node number - shl ax, 8 ; [15:8]=node# - mov al, dl ; [7:0]=core# (relative to node) - mov esi, eax ; ESI = return value - .endif ; end: Is_AP - bts esi, FLAG_IS_PRIMARY ; all Family 10h cores are primary - bts esi, FLAG_FORCE_32K_STACK ; all Family 10h to force 32KB stack size for BSP core - -node_core_f10_exit: -ENDM - - -;;*************************************************************************** -;; Family 12h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 12h requirements (BKDG section 2.3.3): -; The following requirements must be satisfied prior to using the cache as general storage: -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0 -; * MSRC001_1020[DIS_SS]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -; * MSRC001_1022[DIS_HW_PF]=1 -; * MSRC001_1029[ClflushSerialize]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F12 MACRO - local fam12_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz fam12_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative DC-TLB reloads - bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable self modifying code check buffer - bts eax, DIS_HW_PF ; Disable hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative IC-TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_SS ; Disabled Streaming store functionality - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov ecx, DE_CFG ; MSR:C001_1029 - _RDMSR - bts eax, CL_FLUSH_SERIALIZE ; Serialize all CL Flush actions - _WRMSR - -fam12_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 12h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1020[DIS_SS]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -; * MSRC001_1029[ClflushSerialize]=0 -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F12 MACRO - local fam12_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz fam12_disable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads - btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Enable self modifying code check buffer - btr eax, DIS_HW_PF ; Enable Hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative IC-TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - btr eax, DIS_SS ; Turn on Streaming store functionality - _WRMSR - - mov ecx, DE_CFG ; MSR:C001_1029 - _RDMSR - btr eax, CL_FLUSH_SERIALIZE - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, HWCR ; MSR:0000_0015h - _RDMSR - mov bx, ax ; Save INVD -> WBINVD bit - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - mov ax, bx ; Restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - -fam12_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F12 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F12 MACRO - - local node_core_f12_exit - local end_of_f12h_data - - IFNDEF FAM12H_INFO_STRUCT - jmp end_of_f12h_data - ; Family 12h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - FAM12H_INFO_STRUCT CPU_FAMILY_INFO { 512, 1, 0, 384, 40, 0 } -end_of_f12h_data: - ENDIF - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f12_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz node_core_f12_exit ; Br if no - - LoadTableAddress(FAM12H_INFO_STRUCT) - movd mm5, eax ; load pointer to Family Info Struc - - shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts ebx, FLAG_IS_PRIMARY ; all family 12h cores are primary - mov esi, ebx ; ESI = Node#=0, core number - bts esi, FLAG_FORCE_32K_STACK ; all Family 12h to force 32KB stack size for BSP core -node_core_f12_exit: -ENDM - - -;;*************************************************************************** -;; Family 14h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 14h requirements (BKDG section 2.3.3): -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0. -; * MSRC001_1020[DisStreamSt]=1. -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. -; * MSRC001_1022[DIS_HW_PF]=1. -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F14 MACRO - local fam14_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz fam14_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DIS_HW_PF ; Disable hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_STREAM_ST ; Disabled Streaming store functionality - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - -fam14_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 14h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1. -; * MSRC001_1020[DisStreamSt]=0. -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0. -; * MSRC001_1022[DIS_HW_PF]=0. -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F14 MACRO - local fam14_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz fam14_disable_stack_hook_exit ; Br if no - - mov ecx, LS_CFG ; MSR:C001_1020 - _RDMSR - btr eax, DIS_STREAM_ST ; Turn on Streaming store functionality - _WRMSR - - inc cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads - _WRMSR - - inc cx ;DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DIS_HW_PF ; Turn on hardware prefetches - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - bts eax, INVD_WBINVD ; Turn on Conversion of INVD to WBINVD - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - -fam14_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F14 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F14 MACRO - - local node_core_f14_exit - local end_of_f14h_data - - IFNDEF FAM14H_INFO_STRUCT - jmp end_of_f14h_data - ; Family 14h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - FAM14H_INFO_STRUCT CPU_FAMILY_INFO { 256, 1, 0, 0, 36, 0} -end_of_f14h_data: - ENDIF - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f14_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz node_core_f14_exit ; Br if no - - LoadTableAddress(FAM14H_INFO_STRUCT) - movd mm5, eax ; load pointer to Family Info Struc - - shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts ebx, FLAG_IS_PRIMARY ; all family 14h cores are primary - mov esi, ebx ; ESI = Node#=0, core number -node_core_f14_exit: -ENDM - - - -;;*************************************************************************** -;; Family 15h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 15h requirements (BKDG #42301 section 2.3.3): -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0 -; * MSRC001_1020[DisSS]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DisHwPf]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F15 MACRO - local fam15_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz fam15_enable_stack_hook_exit ; Br if no - - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov ecx, LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_SS ; Turn on Streaming store functionality disabled bit - _WRMSR - - inc ecx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative IC-TLB reloads bit - _WRMSR - - inc ecx ;DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DC-TLB reloads bit - bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit - _WRMSR - - mov eax, ebx ; Restore revision info to EAX - shr eax, 16 - and al, 0Fh ; AL = cpu extended model - .if (al == 01h) ; Is this TN? - ; Do TN enable stack special - mov ecx, CU_CFG ; MSR:C001_1023 - _RDMSR - bt eax, L2_WAY_LOCK_EN ; Check if way 15 of the L2 needs to be reserved - .if (!carry?) - bts eax, L2_WAY_LOCK_EN - or eax, L2_FIRST_LOCKED_WAY_OR_MASK - _WRMSR - .endif - .endif - ; Do Standard Family 15 work - mov ecx, CU_CFG3 ; MSR:C001_102B - _RDMSR - btr edx, (COMBINE_CR0_CD - 32) ; Clear CombineCr0Cd bit - _WRMSR - -fam15_enable_stack_hook_exit: -ENDM - - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 15h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1020[DisSS]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F15 MACRO - local fam15_disable_stack_hook_exit - local fam15_disable_stack_remote_read_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz fam15_disable_stack_hook_exit ; Br if no - - mov edi, ebx ; Save revision info to EDI - AMD_CPUID AMD_CPUID_APIC - mov al, cl ; AL = number of cores - 1 - shr cx, APIC_ID_CORE_ID_SIZE ; CL = ApicIdCoreIdSize - mov bx, 1 - shl bl, cl ; BL = theoretical number of cores on socket - dec bx ; BL = core number on socket mask - mov ah, bl ; AH = core number on socket mask - mov ebx, edi ; Restore revision info to EBX - mov di, ax ; DI[15:8] = core number mask, DI[7:0] = number of cores - 1 - - and ebx, 0F00FFh - mov eax, ebx - shr eax, 8 - or bx, ax ; Save Extended Model, Model and Stepping to BX - ; [11:8] = Extended Model, [7:4] = Model, [3:0] = Stepping - - ;; A handshake is required to ensure that all cores on a node invalidate in sync. - mov ecx, APIC_BASE_ADDRESS - _RDMSR - mov dx, bx ; Save Extended Model, Model and Stepping to DX - shl edx, 16 ; EDX[31:16] = Extended Model, Model and Stepping - mov ebx, eax ; EBX = LAPIC base - xor ecx, ecx ; Zero out CU flags - bts ecx, AMD_CU_NEED_TO_WAIT ; Default to waiting - bts ecx, AMD_CU_SEND_INVD_MSG ; Default to signaling - mov eax, CR0 - bt ax, CR0_PE ; Are we in protected mode? - .if (!carry?) - bts ecx, AMD_CU_RESTORE_ES ; Indicate ES restore is required - mov cx, es ; Save ES segment register to CX - xor ax, ax - mov es, ax ; Set ES to big real mode selector for 4GB access - .endif - - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bl, APIC_ID_REG - mov eax, es:[ebx] ; EAX[31:24] = APIC ID - shr eax, APIC20_APICID ; AL = APIC ID - mov ah, al ; AH = APIC ID - mov dx, di ; DH = core mask - and ah, dh ; AH = core number - .if (zero?) - ;; Core 0 of a socket - btr ecx, AMD_CU_SEND_INVD_MSG ; No need to signal after INVD - .if (dl != 0) - ;; This socket has multiple cores - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_MSG_REG - mov edi, APIC_MSG - mov es:[ebx], edi ; Signal for non core 0s to complete CAR breakdown - .else - btr ecx, AMD_CU_NEED_TO_WAIT ; No need to wait on a single core CPU - .endif - .endif - - bt ecx, AMD_CU_NEED_TO_WAIT - .if (carry?) - .if (ah == dl) - ;; This is the highest numbered core on this socket -- wait on core 0 - not dh ; Flip the mask to determine local core 0's APIC ID - and al, dh ; AL = target APIC ID - .else - ;; All other cores (including core 0) wait on the next highest core. - ;; In this way, cores will halt in a cascading fashion down to 0. - inc al - .endif - - shl eax, APIC20_APICID - and bx, 0F000h - or bx, APIC_CMD_HI_REG - mov es:[ebx], eax ; Set target APIC ID - - ;; Use bits 23:16 as a timeout for unresponsive cores - ror ecx, 8 - mov ch, 0FFh - stc - .while (carry?) - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_CMD_LO_REG - mov eax, CMD_REG_TO_READ_DATA - mov es:[ebx], eax ; Fire remote read IPI - inc ch ; Pre increment the timeout - stc - .while (carry?) - dec ch ; Check the timeout - jz fam15_disable_stack_remote_read_exit ; Branch if there is an unresponsive core - mov eax, es:[ebx] - bt eax, DELIVERY_STS_BIT - .endw - stc - .while (carry?) - mov eax, es:[ebx] - and eax, REMOTE_READ_STS - .if (eax == REMOTE_DELIVERY_PEND) - dec ch ; Check the timeout - jz fam15_disable_stack_remote_read_exit ; Branch if there is an unresponsive core - stc - .else - clc - .endif - .endw - .if (eax == REMOTE_DELIVERY_DONE) - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bl, APIC_REMOTE_READ_REG - mov eax, es:[ebx] - .if (eax == APIC_MSG) - clc - .else - stc - .endif - .else - dec ch ; Check the timeout - jz fam15_disable_stack_remote_read_exit ; Branch if there is an unresponsive core - stc - .endif - .endw - -fam15_disable_stack_remote_read_exit: - rol ecx, 8 ; Restore ECX - - .endif - bt ecx, AMD_CU_RESTORE_ES - .if (carry?) - mov es, cx - .endif - mov edi, ecx ; EDI = CU flags - shr edx, 16 - mov bx, dx ; Restore Extended Model, Model and Stepping - - ;; Handshaking complete. Continue tearing down CAR. - mov ecx, LS_CFG ; MSR:C001_1020 - .if (bx != 0) ; Is this OR A0? - _RDMSR - btr eax, DIS_SS ; Turn on Streaming store functionality - _WRMSR - .endif ; End workaround for errata 495 and 496 - - inc ecx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - _WRMSR - - inc ecx ;DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - .if (bx != 0) ; Is this OR A0? - btr eax, DIS_HW_PF ; Turn on hardware prefetches - .endif ; End workaround for erratum 498 - _WRMSR - - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - - .if (bh == 01h) ; Is this TN? - ; Do TN enable stack special - mov ecx, CU_CFG ; MSR:C001_1023 - _RDMSR - shr eax, L2_FIRST_LOCKED_WAY - and eax, 01Fh - .if (eax == 01Fh) ; Check if way 15 of the L2 needs to be reserved - mov ecx, CU_CFG ; MSR:C001_1023 - _RDMSR - btr eax, L2_WAY_LOCK_EN - _WRMSR - .endif - .endif - ; Do Standard Family 15 work - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - bts eax, INVD_WBINVD ; Turn on INVD -> WBINVD conversion - _WRMSR - - mov ecx, CU_CFG3 ; MSR:C001_102B - _RDMSR - bts edx, (COMBINE_CR0_CD - 32) ; Set CombineCr0Cd bit - _WRMSR - - bt edi, AMD_CU_SEND_INVD_MSG - .if (carry?) - ;; Non core zero needs to signal to core 0 to proceed - mov ecx, APIC_BASE_ADDRESS - _RDMSR - mov ebx, eax ; EBX = LAPIC base - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_MSG_REG - mov eax, APIC_MSG - mov es:[ebx], eax ; Signal for core 0 to complete CAR breakdown - .endif - -fam15_disable_stack_hook_exit: -ENDM - - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F15 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F15 MACRO - - local node_core_f15_exit - local end_of_f15h_data - - IFNDEF FAM15H_INFO_STRUCT - jmp end_of_f15h_data - ; Family 15h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - FAM15H_INFO_STRUCT CPU_FAMILY_INFO { 512, 2, 0, 0, 48, 0 } -end_of_f15h_data: - ENDIF - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f15_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz node_core_f15_exit ; Br if no - - LoadTableAddress(FAM15H_INFO_STRUCT) - movd mm5, eax ; load pointer to Family Info Struc - - xor esi, esi ; Assume BSC, clear local flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (carry?) - ; This is the BSP. - ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx - btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0 - out dx, eax - .else ; - ; This is an AP. Routing tables have been enabled by the HT Init process. - ; Also, the MailBox register was set by the BSP during early init - ; The Mailbox register content is formatted as follows: - ; UINT32 Node:4; // The node id of Core's node. - ; UINT32 Socket:4; // The socket of this Core's node. - ; UINT32 Module:2; // The internal module number for Core's node. - ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - ; UINT32 :20; // Reserved - ; - mov ecx, 0C0000408h ; Read the family 15h mailbox - _RDMSR ; MC4_MISC1[63:32] - mov si, dx ; SI = raw mailbox contents (will extract node# from this) - shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov di, bx ; DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID AMD_CPUID_APIC ; - shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core# - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG - _RDMSR ; EDX has InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch ; - shr di, cl ; Right justify core number - .endif ; - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - movzx eax, si ; Prepare return value - and ax, 000Fh ; AX = node number - shl ax, 8 ; [15:8]=node# - mov al, dl ; [7:0]=core# (relative to node) - mov esi, eax ; ESI = node-relative core number - .endif ; end - - ; - ; determine if this core shares MTRRs - ; - mov eax, 8000C580h ; Compute Unit Status - mov bx, si ; load node#(bh), core#(bl) - shl bh, 3 ; Move node# to PCI Dev# field - add ah, bh ; Adjust PCI adress for node number - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx ; [3:0]=Enabled; [19:16]=DualCore - - ; BL is MyCore# , BH is primary flag - mov cx, 06h ; Use CH as 'first of pair' core# - .while (cl > 0) - bt eax, 0 ; Is pair enabled? - .if (carry?) ; - mov bh, 01h ; flag core as primary - bt eax, 16 ; Is there a 2nd in the pair? - .if (carry?) ; - .break .if (ch == bl) ; Does 1st match MyCore#? - inc ch - xor bh, bh ; flag core as NOT primary - .break .if (ch == bl) ; Does 2nd match MyCore#? - .else ; No 2nd core - .break .if (ch == bl) ; Does 1st match MyCore#? - .endif - inc ch - .endif - shr eax, 1 - dec cl - .endw - .if (cl == 0) - ;Error - core# didn't match Compute Unit Status content - bts esi, FLAG_CORE_NOT_IDENTIFIED - bts esi, FLAG_IS_PRIMARY ; Set Is_Primary for unknowns - .endif - .if (bh != 0) ; Check state of primary for the matched core - bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value - .endif -node_core_f15_exit: -ENDM - - - diff --git a/src/vendorcode/amd/agesa/f15tn/cpcar.inc b/src/vendorcode/amd/agesa/f15tn/cpcar.inc deleted file mode 100644 index 7d17e99..0000000 --- a/src/vendorcode/amd/agesa/f15tn/cpcar.inc +++ /dev/null @@ -1,1529 +0,0 @@ -;***************************************************************************** -; AMD Generic Encapsulated Software Architecture -; -; $Workfile:: cpcar.inc -; -; Description: CPCAR.INC - AGESA cache-as-RAM setup Include File -; -;***************************************************************************** -; - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;***************************************************************************** - .LIST - .mmx - -BSP_STACK_BASE_ADDR EQU 30000h ; Base address for primary cores stack -BSP_STACK_SIZE_64K EQU 10000h ; 64KB for BSP core -BSP_STACK_SIZE_32K EQU 8000h ; 32KB for BSP core -CORE0_STACK_BASE_ADDR EQU 80000h ; Base address for primary cores stack -CORE0_STACK_SIZE EQU 4000h ; 16KB for primary cores -CORE1_STACK_BASE_ADDR EQU 40000h ; Base address for AP cores -CORE1_STACK_SIZE EQU 1000h ; 4KB for each AP cores - -L3_CONTROL_REGISTER EQU 8100C3B8h ; Bus 0, Device 18h, Function 3, Offset 1B8h - -APIC_BASE_ADDRESS EQU 0000001Bh - APIC_BSC EQU 8 ; Boot Strap Core - -APIC_MSG_REG EQU 380h ; Location of BSC message - APIC_MSG EQU 00DE00ADh ; Message data -APIC_CMD_LO_REG EQU 300h ; APIC command low -APIC_CMD_HI_REG EQU 310h ; APIC command high - CMD_REG_TO_READ_DATA EQU 00000338h ; APIC command for remote read of APIC_MSG_REG - REMOTE_READ_STS EQU 00030000h ; Remote read status mask - REMOTE_DELIVERY_PEND EQU 00010000h ; Remote read is pending - REMOTE_DELIVERY_DONE EQU 00020000h ; Remote read is complete - DELIVERY_STS_BIT EQU 12 ; Delivery status valid bit -APIC_ID_REG EQU 0020h ; Local APIC ID offset - APIC20_APICID EQU 24 -APIC_REMOTE_READ_REG EQU 00C0h ; Remote read offset - -; Flags can only run from bits 31 to 24. Bits 23:0 are in use. -AMD_CU_NEED_TO_WAIT EQU 31 -AMD_CU_SEND_INVD_MSG EQU 30 -AMD_CU_RESTORE_ES EQU 29 - -AMD_MTRR_VARIABLE_BASE0 EQU 0200h -AMD_MTRR_VARIABLE_BASE6 EQU 020Ch -AMD_MTRR_VARIABLE_BASE7 EQU 020Eh - VMTRR_VALID EQU 11 - MTRR_TYPE_WB EQU 06h - MTRR_TYPE_WP EQU 05h - MTRR_TYPE_WT EQU 04h - MTRR_TYPE_UC EQU 00h -AMD_MTRR_VARIABLE_MASK7 EQU 020Fh -AMD_MTRR_FIX64k_00000 EQU 0250h -AMD_MTRR_FIX16k_80000 EQU 0258h -AMD_MTRR_FIX16k_A0000 EQU 0259h -AMD_MTRR_FIX4k_C0000 EQU 0268h -AMD_MTRR_FIX4k_C8000 EQU 0269h -AMD_MTRR_FIX4k_D0000 EQU 026Ah -AMD_MTRR_FIX4k_D8000 EQU 026Bh -AMD_MTRR_FIX4k_E0000 EQU 026Ch -AMD_MTRR_FIX4k_E8000 EQU 026Dh -AMD_MTRR_FIX4k_F0000 EQU 026Eh -AMD_MTRR_FIX4k_F8000 EQU 026Fh - -AMD_MTRR_DEFTYPE EQU 02FFh - WB_DRAM_TYPE EQU 1Eh ; MemType - memory type - MTRR_DEF_TYPE_EN EQU 11 ; MtrrDefTypeEn - variable and fixed MTRRs default enabled - MTRR_DEF_TYPE_FIX_EN EQU 10 ; MtrrDefTypeEn - fixed MTRRs default enabled - -HWCR EQU 0C0010015h ; Hardware Configuration - INVD_WBINVD EQU 4 ; INVD to WBINVD conversion - -IORR_BASE EQU 0C0010016h ; IO Range Regusters Base/Mask, 2 pairs - ; uses 16h - 19h -TOP_MEM EQU 0C001001Ah ; Top of Memory -TOP_MEM2 EQU 0C001001Dh ; Top of Memory2 - -LS_CFG EQU 0C0011020h ; Load-Store Configuration - DIS_SS EQU 28 ; Family 10h,12h,15h:Disable Streaming Store functionality - DIS_STREAM_ST EQU 28 ; Family 14h:DisStreamSt - Disable Streaming Store functionality - -IC_CFG EQU 0C0011021h ; Instruction Cache Config Register - IC_DIS_SPEC_TLB_RLD EQU 9 ; Disable speculative TLB reloads - DIS_IND EQU 14 ; Family 10-14h:Disable Indirect Branch Predictor -;del DIS_I_CACHE EQU 14 ; Family 15h:DisICache - Disable Indirect Branch Predictor - -DC_CFG EQU 0C0011022h ; Data Cache Configuration - DC_DIS_SPEC_TLB_RLD EQU 4 ; Disable speculative TLB reloads - DIS_CLR_WBTOL2_SMC_HIT EQU 8 ; self modifying code check buffer bit - DIS_HW_PF EQU 13 ; Hardware prefetches bit - -CU_CFG EQU 0C0011023h ; Family 15h: Combined Unit Configuration - L2_WAY_LOCK_EN EQU 23 ; L2WayLock - L2 way lock enable - L2_FIRST_LOCKED_WAY EQU 19 ; L2FirstLockedWay - first L2 way lockedh - L2_FIRST_LOCKED_WAY_OR_MASK EQU 000780000h - -DE_CFG EQU 0C0011029h ; Decode Configuration - CL_FLUSH_SERIALIZE EQU 23 ; Family 12h,15h: CL Flush Serialization - -BU_CFG2 EQU 0C001102Ah ; Family 10h-14h: Bus Unit Configuration 2 -CU_CFG2 EQU 0C001102Ah ; Family 15h: Combined Unit Configuration 2 - F10_CL_LINES_TO_NB_DIS EQU 15 ; ClLinesToNbDis - allows WP code to be cached in L2 -;del IC_DIS_SPEC_TLB_WR EQU 35 ; IcDisSpecTlbWr - ITLB speculative writes - -CU_CFG3 EQU 0C001102Bh ; Combined Unit Configuration 3 - COMBINE_CR0_CD EQU 49 ; Combine CR0.CD for both cores of a compute unit - - -CR0_PE EQU 0 ; Protection Enable -CR0_NW EQU 29 ; Not Write-through -CR0_CD EQU 30 ; Cache Disable -CR0_PG EQU 31 ; Paging Enable - -; CPUID Functions - -CPUID_MODEL EQU 1 -AMD_CPUID_FMF EQU 80000001h ; Family Model Features information -AMD_CPUID_L2Cache EQU 80000006h ; L2/L3 cache info -AMD_CPUID_APIC EQU 80000008h ; Long Mode and APIC info., core count - APIC_ID_CORE_ID_SIZE EQU 12 ; ApicIdCoreIdSize bit position - -NB_CFG EQU 0C001001Fh ; Northbridge Configuration Register - INIT_APIC_ID_CPU_ID_LO EQU 54 ; InitApicIdCpuIdLo - is core# in high or low half of APIC ID? - ENABLE_CF8_EXT_CFG EQU 46 ; EnableCf8ExtCfg - enable CF8 extended configuration cycles - -MTRR_SYS_CFG EQU 0C0010010h ; System Configuration Register - CHX_TO_DIRTY_DIS EQU 16 ; ChxToDirtyDis Change to dirty disable - SYS_UC_LOCK_EN EQU 17 ; SysUcLockEn System lock command enable - MTRR_FIX_DRAM_EN EQU 18 ; MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable - MTRR_FIX_DRAM_MOD_EN EQU 19 ; MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable - MTRR_VAR_DRAM_EN EQU 20 ; MtrrVarDramEn MTRR variable DRAM enable - MTRR_TOM2_EN EQU 21 ; MtrrTom2En MTRR top of memory 2 enable - -PERF_CONTROL3 EQU 0C0010003h ; Performance event control three - PERF_CONTROL3_RESERVE_L EQU 00200000h ; Preserve the reserved bits - PERF_CONTROL3_RESERVE_H EQU 0FCF0h ; Preserve the reserved bits - CONFIG_EVENT_L EQU 0F0E2h ; All cores with level detection - CONFIG_EVENT_H EQU 4 ; Increment count by number of event - ; occured in clock cycle - EVENT_ENABLE EQU 22 ; Enable the event -PERF_COUNTER3 EQU 0C0010007h ; Performance event counter three - -; PCI Registers -FUNC_3 EQU 3 -MCA_NB_CFG EQU 44h ; MCA NB Configuration - CPU_ERR_DIS EQU 6 ; CPU error response disable - -PRODUCT_INFO_REG1 EQU 1FCh ; Product Information Register 1 - -; Local use flags, in upper most byte of ESI -FLAG_UNKNOWN_FAMILY EQU 24 ; Signals that the family# of the installed processor is not recognized -FLAG_STACK_REENTRY EQU 25 ; Signals that the environment has made a re-entry (2nd) call to set up the stack -FLAG_IS_PRIMARY EQU 26 ; Signals that this core is the primary within the compute unit -FLAG_CORE_NOT_IDENTIFIED EQU 27 ; Signals that the cores/compute units of the installed processor is not recognized -FLAG_FORCE_32K_STACK EQU 28 ; Signals that to force 32KB stack size for BSP core - -; Error code returned in EDX by AMD_ENABLE_STACK -IFNDEF CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY - CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY EQU 008010500h -ENDIF -IFNDEF CPU_EVENT_STACK_REENTRY - CPU_EVENT_STACK_REENTRY EQU 008020500h -ENDIF -IFNDEF CPU_EVENT_CORE_NOT_IDENTIFIED - CPU_EVENT_CORE_NOT_IDENTIFIED EQU 008030500h -ENDIF - -; AGESA_STATUS values -IFNDEF AGESA_SUCCESS - AGESA_SUCCESS EQU 0 -ENDIF -IFNDEF AGESA_WARNING - AGESA_WARNING EQU 4 -ENDIF -IFNDEF AGESA_FATAL - AGESA_FATAL EQU 7 -ENDIF -;;*************************************************************************** -;; -;; CPU MACROS - PUBLIC -;; -;;*************************************************************************** -_WRMSR macro - db 0Fh, 30h - endm - -_RDMSR macro - db 0Fh, 32h - endm - -AMD_CPUID MACRO arg0 - IFB <arg0> - mov eax, 1 - db 0Fh, 0A2h ; Execute instruction - bswap eax - xchg al, ah ; Ext model in al now - rol eax, 8 ; Ext model in ah, model in al - and ax, 0FFCFh ; Keep 23:16, 7:6, 3:0 - ELSE - mov eax, arg0 - db 0Fh, 0A2h - ENDIF -ENDM - -MAKE_EXT_PCI_ADDR MACRO Seg, Bus, Dev, Func, Offset - mov eax, ((1 SHL 31) OR (Seg SHL 28) OR (((Offset AND 0F00h) SHR 8) SHL 24) OR (Bus SHL 16) OR (Dev SHL 11) OR (Func SHL 8) OR (Offset AND 0FCh)) - ENDM - -;--------------------------------------------------- -; LoadTableAddress -; Due to the various assembly methodologies used by BIOS vendors, this macro is needed to abstract the -; loading of the address of a table. The default is the standard LEA instruction with table address. -; The IBV that needs to use an alternative method can define their version of the macro prior to including -; this file into their source. -; An alternative example: -; LoadTableAddress MACRO MyTable -; LEA eax, -(LAST_ADDRESS - MyTable) -;--------------------------------------------------- -IFNDEF LoadTableAddress - LoadTableAddress Macro TargetTable - LEA eax, TargetTable - ENDM -ENDIF - - -;;*************************************************************************** -;; -;; CPU STRUCTURES - PUBLIC -;; -;;*************************************************************************** -CPU_FAMILY_INFO STRUC - L2_MIN_SIZE WORD ? ; Minimum size of the L2 cache for this family, in K - NUM_SHARED_CORES BYTE ? ; Number of cores sharing an L2 cache - L2_ALLOC_MEM BYTE ? ; L2 space reserved for memory training, in K - L2_ALLOC_EXE WORD ? ; L2 space reserved for EXE CACHE, in K. 0 means unlimited. - SIZE_ADDRESS_BUS BYTE ? ; Number of address bits supported by this family - FAMILY_RESERVED BYTE ? ; reserved, pad to DWORD size -CPU_FAMILY_INFO ENDS - - -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK MACRO - - AMD_ENABLE_STACK_FAMILY_HOOK_F10 - AMD_ENABLE_STACK_FAMILY_HOOK_F12 - AMD_ENABLE_STACK_FAMILY_HOOK_F14 - AMD_ENABLE_STACK_FAMILY_HOOK_F15 - -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK MACRO - - AMD_DISABLE_STACK_FAMILY_HOOK_F10 - AMD_DISABLE_STACK_FAMILY_HOOK_F12 - AMD_DISABLE_STACK_FAMILY_HOOK_F14 - AMD_DISABLE_STACK_FAMILY_HOOK_F15 - -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; SI[7:0] = Core# (0..N, relative to node) -; SI[15:8]= Node# (0..N) -; SI[23:16]= reserved -; SI[24]= flag: 1=Family Unrecognized -; SI[25]= flag: 1=Interface re-entry call -; SI[26]= flag: 1=Core is primary of compute unit -; SI[31:27]= reserved, =0 -; -; Destroyed: -; eax, ebx, ecx, edx, esi -;--------------------------------------------------- -GET_NODE_ID_CORE_ID MACRO - - mov si, -1 - GET_NODE_ID_CORE_ID_F10 - GET_NODE_ID_CORE_ID_F12 - GET_NODE_ID_CORE_ID_F14 - GET_NODE_ID_CORE_ID_F15 - ; - ; Check for unrecognized Family - ; - .if (si == -1) ; Has family (node/core) been discovered? - mov esi, ( (1 SHL FLAG_UNKNOWN_FAMILY)+(1 SHL FLAG_IS_PRIMARY) ) ; No, Set error code, Only let BSP continue - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (!carry?) - ; No, this is an AP - hlt ; Kill APs - .endif - .endif -ENDM - - - - -;;*************************************************************************** -;; Family 10h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 10h requirements (BKDG section 2.3.3): -; * Paging disabled -; * MSRC001_0015[INVDWBINVD]=0 -; * MSRC001_1021[DIS_IND]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -; * MSRC001_1022[DIS_HW_PF]=1 -; * MSRC001_102A[IcDisSpecTlbWr]=1 -; * MSRC001_102A[ClLinesToNbDis]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F10 MACRO - local fam10_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz fam10_enable_stack_hook_exit ; Br if no - - ; Errata #385 - ; F3x1B8[23] = 1 before enabling L3 cache through CR0[30](CD) - mov eax, ebx ; Restore revision info to EAX - .if (al >= 80h) ; Is this Revision D and later? - mov ecx, NB_CFG ; MSR:C001_001F - _RDMSR ; EDX has EnableCf8ExtCfg bit - bts edx, (ENABLE_CF8_EXT_CFG - 32) - _WRMSR - - mov eax, esi ; Get node# from esi[15:8] - and eax, 0000FF00h - shl eax, (11 - 8) ; Device# - add eax, L3_CONTROL_REGISTER - mov dx, 0CF8h ; PCI Read - out dx, eax - mov dx, 0CFCh - in eax, dx - - or eax, (1 shl 23) ; F3x1B8[23] = 1 - - out dx, eax ; PCI Write - .endif - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DTLB reloads bit - bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Turn on Disable the self modifying code check buffer bit - bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit - _WRMSR - - dec cx ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative TLB reloads bit - bts eax, DIS_IND ; Turn on Disable indirect branch predictor - _WRMSR - - mov ecx, BU_CFG2 ; MSR C001_102A - _RDMSR - bts eax, F10_CL_LINES_TO_NB_DIS ; Allow BIOS ROM to be cached in the IC - bts edx, (IC_DIS_SPEC_TLB_WR-32) ;Disable speculative writes to the ITLB - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov eax, esi ; load core# - .if (al == 0) ; If (BSP) - mov ecx, PERF_COUNTER3 ; Select performance counter three - ; to count number of CAR evictions - xor eax, eax ; Initialize the lower part of the counter to zero - xor edx, edx ; Initializa the upper part of the counter to zero - _WRMSR ; Save it - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Get the current setting - and eax, PERF_CONTROL3_RESERVE_L ; Preserve the reserved bits - or eax, CONFIG_EVENT_L ; Set the lower part of event register to - ; select CAR Corruption occurred by any cores - and dx, PERF_CONTROL3_RESERVE_H ; Preserve the reserved bits - or dx, CONFIG_EVENT_H ; Set the upper part of event register - _WRMSR ; Save it - bts eax, EVENT_ENABLE ; Enable it - _WRMSR ; Save it - .endif ; endif - -fam10_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 10h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1021[DIS_IND]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -; * MSRC001_102A[IcDisSpecTlbWr]=0 -; * MSRC001_102A[ClLinesToNbDis]=0 -;---------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F10 MACRO - local fam10_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz fam10_disable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Enable speculative TLB reloads - btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Allow self modifying code check buffer - btr eax, DIS_HW_PF ; Allow hardware prefetches - _WRMSR - - dec cx ; MSR:C001_1021 - _RDMSR - btr eax, DIS_IND ; Turn on indirect branch predictor - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - _WRMSR - - mov ecx, BU_CFG2 ; MSR:C001_102A - _RDMSR - btr eax, F10_CL_LINES_TO_NB_DIS ; Return L3 to normal mode - btr edx, (IC_DIS_SPEC_TLB_WR-32) ;Re-enable speculative writes to the ITLB - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - mov ecx, HWCR ; MSR:0000_0015 - _RDMSR - mov bx, ax ; Save INVD -> WBINVD bit - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion for the invd instruction. - _WRMSR - invd ; Clear the cache tag RAMs - mov ax, bx ; Restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, PERF_CONTROL3 ; Select the event control three - _RDMSR ; Retrieve the current value - btc eax, EVENT_ENABLE ; Is event enable, complement it as well - jnc fam10_disable_stack_hook_exit ; No - cmp ax, CONFIG_EVENT_L ; Is the lower part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit ; No - cmp dl, CONFIG_EVENT_H ; Is the upper part of event set to capture the CAR Corruption - jne fam10_disable_stack_hook_exit ; No - _WRMSR ; Disable the event - -fam10_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F10 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F10 MACRO - - local node_core_f10_exit - local end_of_f10h_data - - IFNDEF FAM10H_INFO_STRUCT - jmp end_of_f10h_data - ; Family 10h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - FAM10H_INFO_STRUCT CPU_FAMILY_INFO { 512, 1, 16, 384, 48, 0} -end_of_f10h_data: - ENDIF - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f10_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 01h ; Is this family 10h? - jnz node_core_f10_exit ; Br if no - - LoadTableAddress(FAM10H_INFO_STRUCT) - movd mm5, eax ; load pointer to Family Info Struc - - xor esi, esi ; Assume BSC, clear flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (carry?) - ; This is the BSP. - ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx - btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0 - out dx, eax - .else - ; This is an AP. Routing tables have been enabled by the HT Init process. - ; Also, the MailBox register was set by the BSP during early init - ; The Mailbox register content is formatted as follows: - ; UINT32 Node:4; // The node id of Core's node. - ; UINT32 Socket:4; // The socket of this Core's node. - ; UINT32 Module:2; // The internal module number for Core's node. - ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - ; UINT32 :20; // Reserved - ; - mov ecx, 0C0000408h ; Read the family 10h mailbox - _RDMSR ; MC4_MISC1[63:32] - mov si, dx ; SI = raw mailbox contents (will extract node# from this) - shr ebx, 24 ; BL = CPUID Fn0000_0001_EBX[LocalApicId] - mov di, bx ; DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID AMD_CPUID_APIC ; - shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core# - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG ; MSR:C001_001F - _RDMSR ; EDX has InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch - shr di, cl ; Right justify core number - .endif - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - movzx eax, si ; prepare return value (clears flags) - and ax, 000Fh ; AX = node number - shl ax, 8 ; [15:8]=node# - mov al, dl ; [7:0]=core# (relative to node) - mov esi, eax ; ESI = return value - .endif ; end: Is_AP - bts esi, FLAG_IS_PRIMARY ; all Family 10h cores are primary - bts esi, FLAG_FORCE_32K_STACK ; all Family 10h to force 32KB stack size for BSP core - -node_core_f10_exit: -ENDM - - -;;*************************************************************************** -;; Family 12h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 12h requirements (BKDG section 2.3.3): -; The following requirements must be satisfied prior to using the cache as general storage: -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0 -; * MSRC001_1020[DIS_SS]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1 -; * MSRC001_1022[DIS_HW_PF]=1 -; * MSRC001_1029[ClflushSerialize]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F12 MACRO - local fam12_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz fam12_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Disable speculative DC-TLB reloads - bts eax, DIS_CLR_WBTOL2_SMC_HIT ; Disable self modifying code check buffer - bts eax, DIS_HW_PF ; Disable hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative IC-TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_SS ; Disabled Streaming store functionality - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov ecx, DE_CFG ; MSR:C001_1029 - _RDMSR - bts eax, CL_FLUSH_SERIALIZE ; Serialize all CL Flush actions - _WRMSR - -fam12_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 12h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1020[DIS_SS]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -; * MSRC001_1029[ClflushSerialize]=0 -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F12 MACRO - local fam12_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz fam12_disable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads - btr eax, DIS_CLR_WBTOL2_SMC_HIT ; Enable self modifying code check buffer - btr eax, DIS_HW_PF ; Enable Hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative IC-TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - btr eax, DIS_SS ; Turn on Streaming store functionality - _WRMSR - - mov ecx, DE_CFG ; MSR:C001_1029 - _RDMSR - btr eax, CL_FLUSH_SERIALIZE - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, HWCR ; MSR:0000_0015h - _RDMSR - mov bx, ax ; Save INVD -> WBINVD bit - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - mov ax, bx ; Restore INVD -> WBINVD bit - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - -fam12_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F12 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F12 MACRO - - local node_core_f12_exit - local end_of_f12h_data - - IFNDEF FAM12H_INFO_STRUCT - jmp end_of_f12h_data - ; Family 12h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - FAM12H_INFO_STRUCT CPU_FAMILY_INFO { 512, 1, 0, 384, 40, 0 } -end_of_f12h_data: - ENDIF - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f12_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 03h ; Is this family 12h? - jnz node_core_f12_exit ; Br if no - - LoadTableAddress(FAM12H_INFO_STRUCT) - movd mm5, eax ; load pointer to Family Info Struc - - shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts ebx, FLAG_IS_PRIMARY ; all family 12h cores are primary - mov esi, ebx ; ESI = Node#=0, core number - bts esi, FLAG_FORCE_32K_STACK ; all Family 12h to force 32KB stack size for BSP core -node_core_f12_exit: -ENDM - - -;;*************************************************************************** -;; Family 14h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 14h requirements (BKDG section 2.3.3): -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0. -; * MSRC001_1020[DisStreamSt]=1. -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads. -; * MSRC001_1022[DIS_HW_PF]=1. -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F14 MACRO - local fam14_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz fam14_enable_stack_hook_exit ; Br if no - - mov ecx, DC_CFG ; MSR:C001_1022 - _RDMSR - bts eax, DIS_HW_PF ; Disable hardware prefetches - _WRMSR - - dec cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Disable speculative TLB reloads - _WRMSR - - dec cx ;LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_STREAM_ST ; Disabled Streaming store functionality - _WRMSR - - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - -fam14_enable_stack_hook_exit: -ENDM - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 14h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1. -; * MSRC001_1020[DisStreamSt]=0. -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0. -; * MSRC001_1022[DIS_HW_PF]=0. -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F14 MACRO - local fam14_disable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz fam14_disable_stack_hook_exit ; Br if no - - mov ecx, LS_CFG ; MSR:C001_1020 - _RDMSR - btr eax, DIS_STREAM_ST ; Turn on Streaming store functionality - _WRMSR - - inc cx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative DC-TLB reloads - _WRMSR - - inc cx ;DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DIS_HW_PF ; Turn on hardware prefetches - _WRMSR - - ;-------------------------------------------------------------------------- - ; Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - bts eax, INVD_WBINVD ; Turn on Conversion of INVD to WBINVD - _WRMSR - - ;-------------------------------------------------------------------------- - ; End critical sequence in which EAX, BX, ECX, and EDX must be preserved. - ;-------------------------------------------------------------------------- - -fam14_disable_stack_hook_exit: -ENDM - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F14 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F14 MACRO - - local node_core_f14_exit - local end_of_f14h_data - - IFNDEF FAM14H_INFO_STRUCT - jmp end_of_f14h_data - ; Family 14h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - FAM14H_INFO_STRUCT CPU_FAMILY_INFO { 256, 1, 0, 0, 36, 0} -end_of_f14h_data: - ENDIF - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f14_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 20 ; AL = cpu extended family - cmp al, 05h ; Is this family 14h? - jnz node_core_f14_exit ; Br if no - - LoadTableAddress(FAM14H_INFO_STRUCT) - movd mm5, eax ; load pointer to Family Info Struc - - shr ebx, 24 ; CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID - bts ebx, FLAG_IS_PRIMARY ; all family 14h cores are primary - mov esi, ebx ; ESI = Node#=0, core number -node_core_f14_exit: -ENDM - - - -;;*************************************************************************** -;; Family 15h MACROS -;;*************************************************************************** -;--------------------------------------------------- -; -; AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -; -; Set any family specific controls needed to enable the use of -; cache as general storage before main memory is available. -; -; Inputs: -; ESI - node#, core#, flags from GET_NODE_ID_CORE_ID -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 15h requirements (BKDG #42301 section 2.3.3): -; * Paging must be disabled. -; * MSRC001_0015[INVD_WBINVD]=0 -; * MSRC001_1020[DisSS]=1 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=1 -; * MSRC001_1022[DisHwPf]=1 -; * No INVD or WBINVD, no exceptions, page faults or interrupts -;--------------------------------------------------- -AMD_ENABLE_STACK_FAMILY_HOOK_F15 MACRO - local fam15_enable_stack_hook_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz fam15_enable_stack_hook_exit ; Br if no - - bt esi, FLAG_STACK_REENTRY ; Check if stack has already been set - .if (!carry?) - mov ecx, HWCR ; MSR C001_0015 - _RDMSR - btr eax, INVD_WBINVD ; disable INVD -> WBINVD conversion - _WRMSR - .endif - - mov ecx, LS_CFG ; MSR:C001_1020 - _RDMSR - bts eax, DIS_SS ; Turn on Streaming store functionality disabled bit - _WRMSR - - inc ecx ;IC_CFG ; MSR:C001_1021 - _RDMSR - bts eax, IC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative IC-TLB reloads bit - _WRMSR - - mov eax, ebx ; Restore revision info to EAX - shr eax, 16 - and al, 0Fh ; AL = cpu extended model - inc ecx ;DC_CFG ; MSR:C001_1022 - - _RDMSR - bts eax, DC_DIS_SPEC_TLB_RLD ; Turn on Disable speculative DC-TLB reloads bit - bts eax, DIS_HW_PF ; Turn on Disable hardware prefetches bit - _WRMSR - - mov eax, ebx ; Restore revision info to EAX - shr eax, 16 - and al, 0Fh ; AL = cpu extended model - .if (al == 01h) || (al == 03h) ;del ; Is this TN or KV? - .if (al == 01h) ; Is this TN - ; Enable MSRC001_001F[EnableCf8ExtCfg] - mov ecx, NB_CFG ; MSR:C001_001F - _RDMSR ; EDX has EnableCf8ExtCfg bit - bts edx, (ENABLE_CF8_EXT_CFG - 32) - _WRMSR - - ; Set F3x44[6, CpuErrDis] = 1 - MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, MCA_NB_CFG - mov dx, 0CF8h ; PCI Read - out dx, eax - add dx, 4 - in eax, dx - bts eax, CPU_ERR_DIS - out dx, eax - .endif - -;del ; Do TN/KV enable stack special - mov ecx, CU_CFG ; MSR:C001_1023 - _RDMSR - bt eax, L2_WAY_LOCK_EN ; Check if way 15 of the L2 needs to be reserved - .if (!carry?) - bts eax, L2_WAY_LOCK_EN - or eax, L2_FIRST_LOCKED_WAY_OR_MASK - _WRMSR - .endif - .endif - - mov eax, ebx ; Restore revision info to EAX - xchg al, ah - shr eax, 8 ; AX = {ExtFamily, ExtModel, BaseModel, Stepping} -;del .if (ax == 6100h) ; Is this TN-A0? -;del ; Check if F3x1FC[21] is 0 -;del MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, PRODUCT_INFO_REG1 -;del mov dx, 0CF8h ; PCI Read -;del out dx, eax -;del add dx, 4 -;del in eax, dx -;del bt eax, 21 -;del .if (!carry?) ; if F3x1FC[21] == 0? -;del mov ecx, CU_CFG2 ; MSR:C001_102A -;del _RDMSR -;del bts eax, 8 ; Erratum#684. This bit should be set for TN-A0 with D18F3x1FC[21] = 0. -;del _WRMSR -;del .endif -;del .endif - - ; Do Standard Family 15 work - mov ecx, CU_CFG3 ; MSR:C001_102B - _RDMSR - btr edx, (COMBINE_CR0_CD - 32) ; Clear CombineCr0Cd bit - _WRMSR - -fam15_enable_stack_hook_exit: -ENDM - - -;---------------------------------------------- -; -; AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless -; -; Return any family specific controls to their 'standard' -; settings for using cache with main memory. -; -; Inputs: -; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core# -; Outputs: -; none -; Destroyed: -; eax, ebx, ecx, edx -; -; Family 15h requirements: -; * INVD or WBINVD -; * MSRC001_0015[INVD_WBINVD]=1 -; * MSRC001_1020[DisSS]=0 -; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0 -; * MSRC001_1022[DIS_HW_PF]=0 -;--------------------------------------------------- -AMD_DISABLE_STACK_FAMILY_HOOK_F15 MACRO - local fam15_disable_stack_hook_exit - local fam15_disable_stack_remote_read_exit - - AMD_CPUID CPUID_MODEL - mov ebx, eax ; Save revision info to EBX - shr eax, 20 ; AL = cpu extended family - cmp al, 06h ; Is this family 15h? - jnz fam15_disable_stack_hook_exit ; Br if no - - mov edi, ebx ; Save revision info to EDI - AMD_CPUID AMD_CPUID_APIC - mov al, cl ; AL = number of cores - 1 - shr cx, APIC_ID_CORE_ID_SIZE ; CL = ApicIdCoreIdSize - mov bx, 1 - shl bl, cl ; BL = theoretical number of cores on socket - dec bx ; BL = core number on socket mask - mov ah, bl ; AH = core number on socket mask - mov ebx, edi ; Restore revision info to EBX - mov di, ax ; DI[15:8] = core number mask, DI[7:0] = number of cores - 1 - - and ebx, 0F00FFh - mov eax, ebx - shr eax, 8 - or bx, ax ; Save Extended Model, Model and Stepping to BX - ; [11:8] = Extended Model, [7:4] = Model, [3:0] = Stepping - - ;; A handshake is required to ensure that all cores on a node invalidate in sync. - mov ecx, APIC_BASE_ADDRESS - _RDMSR - mov dx, bx ; Save Extended Model, Model and Stepping to DX - shl edx, 16 ; EDX[31:16] = Extended Model, Model and Stepping - mov ebx, eax ; EBX = LAPIC base - xor ecx, ecx ; Zero out CU flags - bts ecx, AMD_CU_NEED_TO_WAIT ; Default to waiting - bts ecx, AMD_CU_SEND_INVD_MSG ; Default to signaling - mov eax, CR0 - bt ax, CR0_PE ; Are we in protected mode? - .if (!carry?) - bts ecx, AMD_CU_RESTORE_ES ; Indicate ES restore is required - mov cx, es ; Save ES segment register to CX - xor ax, ax - mov es, ax ; Set ES to big real mode selector for 4GB access - .endif - - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bl, APIC_ID_REG - mov eax, es:[ebx] ; EAX[31:24] = APIC ID - shr eax, APIC20_APICID ; AL = APIC ID - mov ah, al ; AH = APIC ID - mov dx, di ; DH = core mask - and ah, dh ; AH = core number - .if (zero?) - ;; Core 0 of a socket - btr ecx, AMD_CU_SEND_INVD_MSG ; No need to signal after INVD - .if (dl != 0) - ;; This socket has multiple cores - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_MSG_REG - mov edi, APIC_MSG - mov es:[ebx], edi ; Signal for non core 0s to complete CAR breakdown - .else - btr ecx, AMD_CU_NEED_TO_WAIT ; No need to wait on a single core CPU - .endif - .endif - - bt ecx, AMD_CU_NEED_TO_WAIT - .if (carry?) - .if (ah == dl) - ;; This is the highest numbered core on this socket -- wait on core 0 - not dh ; Flip the mask to determine local core 0's APIC ID - and al, dh ; AL = target APIC ID - .else - ;; All other cores (including core 0) wait on the next highest core. - ;; In this way, cores will halt in a cascading fashion down to 0. - inc al - .endif - - shl eax, APIC20_APICID - and bx, 0F000h - or bx, APIC_CMD_HI_REG - mov es:[ebx], eax ; Set target APIC ID - - ;; Use bits 23:16 as a timeout for unresponsive cores - ror ecx, 8 - mov ch, 0FFh - stc - .while (carry?) - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_CMD_LO_REG - mov eax, CMD_REG_TO_READ_DATA - mov es:[ebx], eax ; Fire remote read IPI - inc ch ; Pre increment the timeout - stc - .while (carry?) - dec ch ; Check the timeout - jz fam15_disable_stack_remote_read_exit ; Branch if there is an unresponsive core - mov eax, es:[ebx] - bt eax, DELIVERY_STS_BIT - .endw - stc - .while (carry?) - mov eax, es:[ebx] - and eax, REMOTE_READ_STS - .if (eax == REMOTE_DELIVERY_PEND) - dec ch ; Check the timeout - jz fam15_disable_stack_remote_read_exit ; Branch if there is an unresponsive core - stc - .else - clc - .endif - .endw - .if (eax == REMOTE_DELIVERY_DONE) - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bl, APIC_REMOTE_READ_REG - mov eax, es:[ebx] - .if (eax == APIC_MSG) - clc - .else - stc - .endif - .else - dec ch ; Check the timeout - jz fam15_disable_stack_remote_read_exit ; Branch if there is an unresponsive core - stc - .endif - .endw - -fam15_disable_stack_remote_read_exit: - rol ecx, 8 ; Restore ECX - - .endif - bt ecx, AMD_CU_RESTORE_ES - .if (carry?) - mov es, cx - .endif - mov edi, ecx ; EDI = CU flags - shr edx, 16 - mov bx, dx ; Restore Extended Model, Model and Stepping - - ;; Handshaking complete. Continue tearing down CAR. - mov ecx, LS_CFG ; MSR:C001_1020 - .if (bx != 0) ;del ; Is this OR A0? - _RDMSR - btr eax, DIS_SS ; Turn on Streaming store functionality - _WRMSR - .endif ; End workaround for errata 495 and 496 - - inc ecx ;IC_CFG ; MSR:C001_1021 - _RDMSR - btr eax, IC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - _WRMSR - - inc ecx ;DC_CFG ; MSR:C001_1022 - _RDMSR - btr eax, DC_DIS_SPEC_TLB_RLD ; Turn on speculative TLB reloads - .if (bx != 0) ;del ; Is this OR A0? - btr eax, DIS_HW_PF ;del ; Turn on hardware prefetches - .endif ; End workaround for erratum 498 - _WRMSR - - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - btr eax, INVD_WBINVD ; Disable INVD -> WBINVD conversion - _WRMSR - invd ; Clear the cache tag RAMs - - .if (bh == 01h) || (bh == 03h) ;del ; Is this TN or KV? -;del ; Do TN/KV disable stack special - mov ecx, CU_CFG ; MSR:C001_1023 - _RDMSR - shr eax, L2_FIRST_LOCKED_WAY - and eax, 01Fh - .if (eax == 01Fh) ; Check if way 15 of the L2 needs to be reserved - _RDMSR ; ECX = CU_CFG, MSR:C001_1023 - btr eax, L2_WAY_LOCK_EN - _WRMSR - .endif - .endif - - ; Do Standard Family 15 work - mov ecx, HWCR ; MSR:C001_0015h - _RDMSR - bts eax, INVD_WBINVD ; Turn on INVD -> WBINVD conversion - _WRMSR - - mov ecx, CU_CFG3 ; MSR:C001_102B - _RDMSR - bts edx, (COMBINE_CR0_CD - 32) ; Set CombineCr0Cd bit - _WRMSR - - bt edi, AMD_CU_SEND_INVD_MSG - .if (carry?) - ;; Non core zero needs to signal to core 0 to proceed - mov ecx, APIC_BASE_ADDRESS - _RDMSR - mov ebx, eax ; EBX = LAPIC base - and bx, 0F000h ; EBX = LAPIC base, offset 0 - or bx, APIC_MSG_REG - mov eax, APIC_MSG - mov es:[ebx], eax ; Signal for core 0 to complete CAR breakdown - .endif - -fam15_disable_stack_hook_exit: -ENDM - - -;--------------------------------------------------- -; -; GET_NODE_ID_CORE_ID_F15 Macro - Stackless -; -; Read family specific values to determine the node and core -; numbers for the core executing this code. -; -; Inputs: -; none -; Outputs: -; ESI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above) -; MM5 = 32b pointer to family info structure -; Destroyed: -; eax, ebx, ecx, edx, esi, mm5 -;--------------------------------------------------- -GET_NODE_ID_CORE_ID_F15 MACRO - - local node_core_f15_exit - local end_of_f15h_data - - IFNDEF FAM15H_INFO_STRUCT - jmp end_of_f15h_data - ; Family 15h Info Structure: L2Size, #SharedCores, AllocMem, AllocExe, SzAddrBus, pad - FAM15H_INFO_STRUCT CPU_FAMILY_INFO { 512, 2, 0, 0, 48, 0 } -end_of_f15h_data: - ENDIF - - cmp si, -1 ; Has node/core already been discovered? - jnz node_core_f15_exit ; Br if yes - - AMD_CPUID CPUID_MODEL - shr eax, 12 ; AH = cpu extended family - cmp ah, 06h ; Is this family 15h? - jnz node_core_f15_exit ; Br if no - shr al, 4 ; AL = cpu extended model - shr ebx, 16 ; BH = LocalApicId - mov bl, al ; BL = cpu extended model - - LoadTableAddress(FAM15H_INFO_STRUCT) - movd mm5, eax ; load pointer to Family Info Struc - - xor esi, esi ; Assume BSC, clear local flags - mov ecx, APIC_BASE_ADDRESS ; MSR:0000_001B - _RDMSR - bt eax, APIC_BSC ; Is this the BSC? - .if (carry?) - ; This is the BSP. - ; Enable routing tables on BSP (just in case the HT init code has not yet enabled them) - mov eax, 8000C06Ch ; PCI address for D18F0x6C Link Initialization Control Register - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx - btr eax, 0 ; Set LinkInitializationControl[RouteTblDis] = 0 - out dx, eax - .else ; - mov al, bl ; AL = cpu extended model - shr bx, 8 ; BL = CPUID Fn0000_0001_EBX[LocalApicId] - .if (al == 1) || (al == 3) ;del ; Is this single node processor (TN or KV)? - mov si, bx ; SI = [15:8]= Node# = 0; [7:0]= core# - .else - ; This is an AP. Routing tables have been enabled by the HT Init process. - ; Also, the MailBox register was set by the BSP during early init - ; The Mailbox register content is formatted as follows: - ; UINT32 Node:4; // The node id of Core's node. - ; UINT32 Socket:4; // The socket of this Core's node. - ; UINT32 Module:2; // The internal module number for Core's node. - ; UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1. - ; UINT32 :20; // Reserved - ; - mov ecx, 0C0000408h ; Read the family 15h mailbox - _RDMSR ; MC4_MISC1[63:32] - mov si, dx ; SI = raw mailbox contents (will extract node# from this) - mov di, bx ; DI = Initial APIC ID (will extract core# from this) - - AMD_CPUID AMD_CPUID_APIC ; - shr ch, 4 ; CH = ApicIdSize, #bits in APIC ID that show core# - inc cl ; CL = Number of enabled cores in the socket - mov bx, cx - - mov ecx, NB_CFG - _RDMSR ; EDX has InitApicIdCpuIdLo bit - - mov cl, bh ; CL = APIC ID size - mov al, 1 ; Convert APIC ID size to an AND mask - shl al, cl ; AL = 2^APIC ID size - dec al ; AL = mask for relative core number - xor ah, ah ; AX = mask for relative core number - bt edx, (INIT_APIC_ID_CPU_ID_LO-32) ; InitApicIdCpuIdLo == 1? - .if (!carry?) ; Br if yes - mov ch, 8 ; Calculate core number shift count - sub ch, cl ; CH = core shift count - mov cl, ch ; - shr di, cl ; Right justify core number - .endif ; - and di, ax ; DI = socket-relative core number - - mov cx, si ; CX = raw mailbox value - shr cx, 10 ; CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM) - and cl, 3 ; Isolate ModuleType - xor bh, bh ; BX = Number of enabled cores in the socket - shr bx, cl ; BX = Number of enabled cores per node - xor dx, dx ; Clear upper word for div - mov ax, di ; AX = socket-relative core number - div bx ; DX = node-relative core number - movzx eax, si ; Prepare return value - and ax, 000Fh ; AX = node number - shl ax, 8 ; [15:8]=node# - mov al, dl ; [7:0]=core# (relative to node) - mov esi, eax ; ESI = node-relative core number - .endif - .endif ; end - - ; - ; determine if this core shares MTRRs - ; - mov eax, 8000C580h ; Compute Unit Status - mov bx, si ; load node#(bh), core#(bl) - shl bh, 3 ; Move node# to PCI Dev# field - add ah, bh ; Adjust PCI adress for node number - mov dx, 0CF8h - out dx, eax - add dx, 4 - in eax, dx ; [3:0]=Enabled; [19:16]=DualCore - - ; BL is MyCore# , BH is primary flag - mov cx, 06h ; Use CH as 'first of pair' core# - .while (cl > 0) - bt eax, 0 ; Is pair enabled? - .if (carry?) ; - mov bh, 01h ; flag core as primary - bt eax, 16 ; Is there a 2nd in the pair? - .if (carry?) ; - .break .if (ch == bl) ; Does 1st match MyCore#? - inc ch - xor bh, bh ; flag core as NOT primary - .break .if (ch == bl) ; Does 2nd match MyCore#? - .else ; No 2nd core - .break .if (ch == bl) ; Does 1st match MyCore#? - .endif - inc ch - .endif - shr eax, 1 - dec cl - .endw - .if (cl == 0) - ;Error - core# didn't match Compute Unit Status content - bts esi, FLAG_CORE_NOT_IDENTIFIED - bts esi, FLAG_IS_PRIMARY ; Set Is_Primary for unknowns - .endif - .if (bh != 0) ; Check state of primary for the matched core - bts esi, FLAG_IS_PRIMARY ; Set shared flag into return value - .endif -node_core_f15_exit: -ENDM - - -

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Patch set updated for coreboot: 09d6c4c gigabyte/ga-b75m-d3h: Add new Intel mainboard
by Damien Zammit 28 Nov '14

28 Nov '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7341 -gerrit commit 09d6c4c0c8e5e36bf0bd808be655bc9169cb7967 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Nov 28 15:59:10 2014 +1100 gigabyte/ga-b75m-d3h: Add new Intel mainboard This is based on LENOVO X230 port. Board boots to linux via SATA or USB. All USB ports are working. Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS. Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/Kconfig | 3 + src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 76 ++++ src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc | 21 + src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl | 0 .../gigabyte/ga-b75m-d3h/acpi/mainboard.asl | 28 ++ .../gigabyte/ga-b75m-d3h/acpi/platform.asl | 73 ++++ .../gigabyte/ga-b75m-d3h/acpi/superio.asl | 24 ++ .../gigabyte/ga-b75m-d3h/acpi/thermal.asl | 65 ++++ src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl | 1 + src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 83 ++++ src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt | 6 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.default | 9 + src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout | 152 ++++++++ src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb | 117 ++++++ src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl | 24 ++ src/mainboard/gigabyte/ga-b75m-d3h/gpio.c | 433 +++++++++++++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c | 8 + src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 106 +++++ src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c | 94 +++++ src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 211 ++++++++++ src/mainboard/gigabyte/ga-b75m-d3h/thermal.h | 30 ++ 21 files changed, 1564 insertions(+) diff --git a/src/mainboard/gigabyte/Kconfig b/src/mainboard/gigabyte/Kconfig index ff96a17..c46b979 100644 --- a/src/mainboard/gigabyte/Kconfig +++ b/src/mainboard/gigabyte/Kconfig @@ -27,6 +27,8 @@ config BOARD_GIGABYTE_GA_6BXC bool "GA-6BXC" config BOARD_GIGABYTE_GA_6BXE bool "GA-6BXE" +config BOARD_GIGABYTE_GA_B75M_D3H + bool "GA-B75M-D3H" config BOARD_GIGABYTE_M57SLI bool "GA-M57SLI-S4" config BOARD_GIGABYTE_MA785GMT @@ -41,6 +43,7 @@ endchoice source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig" source "src/mainboard/gigabyte/ga-6bxc/Kconfig" source "src/mainboard/gigabyte/ga-6bxe/Kconfig" +source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig" source "src/mainboard/gigabyte/m57sli/Kconfig" source "src/mainboard/gigabyte/ma785gmt/Kconfig" source "src/mainboard/gigabyte/ma785gm/Kconfig" diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig new file mode 100644 index 0000000..b14dce5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -0,0 +1,76 @@ +if BOARD_GIGABYTE_GA_B75M_D3H + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA1155 + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_ITE_IT8728F + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select DYNAMIC_CBMEM + select INTEL_INT15 + select VGA + select INTEL_EDID + select UDELAY_TSC + select EARLY_CBMEM_INIT + select SERIRQ_CONTINUOUS_MODE + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config DRAM_RESET_GATE_GPIO + int + default 25 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config MAINBOARD_DIR + string + default gigabyte/ga-b75m-d3h + +config MAINBOARD_PART_NUMBER + string + default "GA-B75M-D3H" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,0162" + +config VGA_BIOS_FILE + string + default "pci8086,0162.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config IFD_BIOS_SECTION + string + default "0x00600000:0x007fffff" + +config IFD_ME_SECTION + string + default "0x00001000:0x004fffff" + +endif # BOARD_GIGABYTE_GA_B75M_D3H diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc new file mode 100644 index 0000000..a2efadd --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c +romstage-y += gpio.c diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl new file mode 100644 index 0000000..09cff9a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl new file mode 100644 index 0000000..1448aeb --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl new file mode 100644 index 0000000..753fc29 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ + +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // Enable PS/2 Mouse + diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl new file mode 100644 index 0000000..f71611a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/thermal.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x03) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 10 seconds + Name (_TSP, 100) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) + { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl new file mode 100644 index 0000000..f87af3c --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/video.asl @@ -0,0 +1 @@ +// Blank diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c new file mode 100644 index 0000000..73b1c11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt new file mode 100644 index 0000000..312f6ef --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default new file mode 100644 index 0000000..21d75e5 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.default @@ -0,0 +1,9 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +sata_mode=AHCI +hyper_threading=Enable diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout new file mode 100644 index 0000000..7c8af49 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -0,0 +1,152 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 2 r 0 unused + +# coreboot config options: cpu +424 1 e 2 hyper_threading +#425 7 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb new file mode 100644 index 0000000..20f88cb --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -0,0 +1,117 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/socket_LGA1155 + device lapic 0 on end + end + chip cpu/intel/model_206ax + register "pstate_coord_type" = "0xfe" + register "c1_acpower" = "1" + register "c2_acpower" = "3" + register "c3_acpower" = "5" + register "c1_battery" = "1" + register "c2_battery" = "3" + register "c3_battery" = "5" + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + end + end + + device domain 0 on + subsystemid 0x1458 0x5000 inherit + device pci 00.0 on # host bridge + subsystemid 0x1458 0x5000 + end + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on # vga controller + subsystemid 0x1458 0xd000 + end + + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + + # GPI routing + register "alt_gp_smi_en" = "0x0000" + register "gen1_dec" = "0x003c0a01" + + # Set max SATA speed to 6.0 Gb/s + register "sata_port_map" = "0x3f" + register "sata_interface_speed_support" = "0x3" + + register "pcie_port_coalesce" = "0" + register "p_cnt_throttling_supported" = "0" + register "docking_supported" = "0" + register "sata_port_map" = "0x3f" + register "c2_latency" = "0x0065" + + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1458 0x5007 + end + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1458 0x5006 + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + device pci 00.0 on # PCI 10ec:8168 + subsystemid 0x1458 0xe000 + end + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA/LPC bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8728f + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # EC + irq 0x70 = 9 + end + device pnp 2e.5 on # Keyboard + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + irq 0x70 = 0 + end + device pnp 2e.a off end # IR + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMBus + subsystemid 0x1458 0x5001 + end + device pci 1f.4 off end + device pci 1f.5 off end # SATA Controller 2 + end + end +end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl new file mode 100644 index 0000000..84a889a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -0,0 +1,24 @@ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c new file mode 100644 index 0000000..791d7c7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/gpio.c @@ -0,0 +1,433 @@ +#include "southbridge/intel/bd82x6x/gpio.h" +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_NATIVE, + .gpio1 = GPIO_MODE_NATIVE, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_NATIVE, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_NATIVE, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_NATIVE, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_NATIVE, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_NATIVE, + .gpio28 = GPIO_MODE_NATIVE, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_OUTPUT, + .gpio1 = GPIO_DIR_OUTPUT, + .gpio2 = GPIO_DIR_OUTPUT, + .gpio3 = GPIO_DIR_OUTPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_OUTPUT, + .gpio6 = GPIO_DIR_OUTPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_HIGH, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_LOW, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio0 = GPIO_RESET_PWROK, + .gpio1 = GPIO_RESET_PWROK, + .gpio2 = GPIO_RESET_PWROK, + .gpio3 = GPIO_RESET_PWROK, + .gpio4 = GPIO_RESET_PWROK, + .gpio5 = GPIO_RESET_PWROK, + .gpio6 = GPIO_RESET_PWROK, + .gpio7 = GPIO_RESET_PWROK, + .gpio8 = GPIO_RESET_PWROK, + .gpio9 = GPIO_RESET_PWROK, + .gpio10 = GPIO_RESET_PWROK, + .gpio11 = GPIO_RESET_PWROK, + .gpio12 = GPIO_RESET_PWROK, + .gpio13 = GPIO_RESET_PWROK, + .gpio14 = GPIO_RESET_PWROK, + .gpio15 = GPIO_RESET_PWROK, + .gpio16 = GPIO_RESET_PWROK, + .gpio17 = GPIO_RESET_PWROK, + .gpio18 = GPIO_RESET_PWROK, + .gpio19 = GPIO_RESET_PWROK, + .gpio20 = GPIO_RESET_PWROK, + .gpio21 = GPIO_RESET_PWROK, + .gpio22 = GPIO_RESET_PWROK, + .gpio23 = GPIO_RESET_PWROK, + .gpio24 = GPIO_RESET_RSMRST, + .gpio25 = GPIO_RESET_PWROK, + .gpio26 = GPIO_RESET_PWROK, + .gpio27 = GPIO_RESET_PWROK, + .gpio28 = GPIO_RESET_PWROK, + .gpio29 = GPIO_RESET_PWROK, + .gpio30 = GPIO_RESET_PWROK, + .gpio31 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_NO_INVERT, + .gpio1 = GPIO_NO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio0 = GPIO_NO_BLINK, + .gpio1 = GPIO_NO_BLINK, + .gpio2 = GPIO_NO_BLINK, + .gpio3 = GPIO_NO_BLINK, + .gpio4 = GPIO_NO_BLINK, + .gpio5 = GPIO_NO_BLINK, + .gpio6 = GPIO_NO_BLINK, + .gpio7 = GPIO_NO_BLINK, + .gpio8 = GPIO_NO_BLINK, + .gpio9 = GPIO_NO_BLINK, + .gpio10 = GPIO_NO_BLINK, + .gpio11 = GPIO_NO_BLINK, + .gpio12 = GPIO_NO_BLINK, + .gpio13 = GPIO_NO_BLINK, + .gpio14 = GPIO_NO_BLINK, + .gpio15 = GPIO_NO_BLINK, + .gpio16 = GPIO_NO_BLINK, + .gpio17 = GPIO_NO_BLINK, + .gpio18 = GPIO_BLINK, + .gpio19 = GPIO_NO_BLINK, + .gpio20 = GPIO_NO_BLINK, + .gpio21 = GPIO_NO_BLINK, + .gpio22 = GPIO_NO_BLINK, + .gpio23 = GPIO_NO_BLINK, + .gpio24 = GPIO_NO_BLINK, + .gpio25 = GPIO_NO_BLINK, + .gpio26 = GPIO_NO_BLINK, + .gpio27 = GPIO_NO_BLINK, + .gpio28 = GPIO_NO_BLINK, + .gpio29 = GPIO_NO_BLINK, + .gpio30 = GPIO_NO_BLINK, + .gpio31 = GPIO_NO_BLINK, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_HIGH, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_LOW, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_LOW, + .gpio56 = GPIO_LEVEL_LOW, + .gpio57 = GPIO_LEVEL_HIGH, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_LOW, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { + .gpio32 = GPIO_RESET_PWROK, + .gpio33 = GPIO_RESET_PWROK, + .gpio34 = GPIO_RESET_PWROK, + .gpio35 = GPIO_RESET_PWROK, + .gpio36 = GPIO_RESET_PWROK, + .gpio37 = GPIO_RESET_PWROK, + .gpio38 = GPIO_RESET_PWROK, + .gpio39 = GPIO_RESET_PWROK, + .gpio40 = GPIO_RESET_PWROK, + .gpio41 = GPIO_RESET_PWROK, + .gpio42 = GPIO_RESET_PWROK, + .gpio43 = GPIO_RESET_PWROK, + .gpio44 = GPIO_RESET_PWROK, + .gpio45 = GPIO_RESET_PWROK, + .gpio46 = GPIO_RESET_PWROK, + .gpio47 = GPIO_RESET_PWROK, + .gpio48 = GPIO_RESET_PWROK, + .gpio49 = GPIO_RESET_PWROK, + .gpio50 = GPIO_RESET_PWROK, + .gpio51 = GPIO_RESET_PWROK, + .gpio52 = GPIO_RESET_PWROK, + .gpio53 = GPIO_RESET_PWROK, + .gpio54 = GPIO_RESET_PWROK, + .gpio55 = GPIO_RESET_PWROK, + .gpio56 = GPIO_RESET_PWROK, + .gpio57 = GPIO_RESET_PWROK, + .gpio58 = GPIO_RESET_PWROK, + .gpio59 = GPIO_RESET_PWROK, + .gpio60 = GPIO_RESET_PWROK, + .gpio61 = GPIO_RESET_PWROK, + .gpio62 = GPIO_RESET_PWROK, + .gpio63 = GPIO_RESET_PWROK, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_HIGH, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { + .gpio64 = GPIO_RESET_PWROK, + .gpio65 = GPIO_RESET_PWROK, + .gpio66 = GPIO_RESET_PWROK, + .gpio67 = GPIO_RESET_PWROK, + .gpio68 = GPIO_RESET_PWROK, + .gpio69 = GPIO_RESET_PWROK, + .gpio70 = GPIO_RESET_PWROK, + .gpio71 = GPIO_RESET_PWROK, + .gpio72 = GPIO_RESET_PWROK, + .gpio73 = GPIO_RESET_PWROK, + .gpio74 = GPIO_RESET_PWROK, + .gpio75 = GPIO_RESET_PWROK, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c new file mode 100644 index 0000000..253ec08 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/hda_verb.c @@ -0,0 +1,8 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c new file mode 100644 index 0000000..0124baa --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <build.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +const char *smbios_mainboard_bios_version(void) +{ + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + else + return "CBET4000 " COREBOOT_VERSION; +} + + + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c new file mode 100644 index 0000000..35702f0 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard_smi.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <pc80/mc146818rtc.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c new file mode 100644 index 0000000..6fea437 --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -0,0 +1,211 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define SUPERIO_BASE 0x2e +#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0) +#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) +#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) + +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <superio/ite/it8728f/it8728f.h> +#include <superio/ite/common/ite.h> +#include "northbridge/intel/sandybridge/sandybridge.h" +#include "northbridge/intel/sandybridge/raminit_native.h" +#include "southbridge/intel/bd82x6x/pch.h" +#include "southbridge/intel/bd82x6x/gpio.h" +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +static void it8728f_b75md3h_disable_reboot(device_t dev) +{ + /* GPIO SIO settings */ + ite_reg_write(dev, 0xEF, 0x7E); // magic + + ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16 + ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34 + ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port + ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00 + ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear! + ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear! + ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in + ite_reg_write(dev, 0xe9, 0x27); // bus select disable + ite_reg_write(dev, 0xf0, 0x10); // ? + ite_reg_write(dev, 0xf1, 0x42); // ? + ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12) + + /* EC SIO settings */ + ite_reg_write(IT8728F_EC, 0xf1, 0xc0); + ite_reg_write(IT8728F_EC, 0xf6, 0xf0); + ite_reg_write(IT8728F_EC, 0xf9, 0x48); + ite_reg_write(IT8728F_EC, 0x60, 0x0a); + ite_reg_write(IT8728F_EC, 0x61, 0x30); + ite_reg_write(IT8728F_EC, 0x62, 0x0a); + ite_reg_write(IT8728F_EC, 0x63, 0x20); + ite_reg_write(IT8728F_EC, 0x30, 0x01); +} + +void rcba_config(void) +{ +/* + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); + + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x3500) = 0x2000035f; + RCBA32(0x3504) = 0x2000035f; + RCBA32(0x3508) = 0x2000035f; + RCBA32(0x350c) = 0x2000035f; + RCBA32(0x3510) = 0x2000035f; + RCBA32(0x3514) = 0x2000035f; + RCBA32(0x3518) = 0x2000035f; + RCBA32(0x351c) = 0x2000035f; + RCBA32(0x3520) = 0x2000035f; + RCBA32(0x3524) = 0x2000035f; + RCBA32(0x3528) = 0x2000035f; + RCBA32(0x352c) = 0x2000035f; + RCBA32(0x3530) = 0x2000035f; + RCBA32(0x3534) = 0x2000035f; + RCBA32(0x3560) = 0x024c8001; + RCBA32(0x3564) = 0x000024a3; + RCBA32(0x3568) = 0x00040002; + RCBA32(0x356c) = 0x01000050; + RCBA32(0x3570) = 0x02000662; + RCBA32(0x3574) = 0x18000f9f; + RCBA32(0x3578) = 0x1800ff4f; + RCBA32(0x357c) = 0x0001d530; + RCBA32(0x35a0) = 0xc0300c03; + RCBA32(0x35a4) = 0x00241803; + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + outw (0x0000, DEFAULT_PMBASE | 0x003c); + + RCBA32(0x2240) = 0x00330e71; + RCBA32(0x2244) = 0x003f0eb1; + RCBA32(0x2248) = 0x002102cd; + RCBA32(0x224c) = 0x00f60000; + RCBA32(0x2250) = 0x00020000; + RCBA32(0x2254) = 0x00e3004c; + RCBA32(0x2258) = 0x00e20bef; + RCBA32(0x2260) = 0x003304ed; + RCBA32(0x2278) = 0x001107c1; + RCBA32(0x227c) = 0x001d07e9; + RCBA32(0x2280) = 0x00e20000; + RCBA32(0x2284) = 0x00ee0000; + RCBA32(0x2288) = 0x005b05d3; + RCBA32(0x2318) = 0x04b8ff2e; + RCBA32(0x231c) = 0x03930f2e; +// RCBA32(0x3418) = 0x1fee1fe1; + RCBA32(0x3808) = 0x005044a3; + RCBA32(0x3810) = 0x52410000; + RCBA32(0x3814) = 0x0000008a; + RCBA32(0x3818) = 0x00000006; + RCBA32(0x381c) = 0x0000072e; + RCBA32(0x3820) = 0x0000000a; + RCBA32(0x3824) = 0x00000123; + RCBA32(0x3828) = 0x00000009; + RCBA32(0x382c) = 0x00000001; + RCBA32(0x3834) = 0x0000061a; + RCBA32(0x3838) = 0x00000003; + RCBA32(0x383c) = 0x00000a76; + RCBA32(0x3840) = 0x00000004; + RCBA32(0x3844) = 0x0000e5e4; + RCBA32(0x3848) = 0x0000000e; +*/ + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17ee1fe1; + + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; +} + +void pch_enable_lpc(void) +{ + /* + * Enable: + * EC Decode Range PortA30/A20 + * SuperIO Port2E/2F + * PS/2 Keyboard/Mouse Port60/64 + * FDD Port3F0h-3F5h and Port3F7h + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + + /* Initialize SuperIO */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8728f_b75md3h_disable_reboot(SUPERIO_GPIO); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 }, +}; + +void mainboard_get_spd(spd_raw_data *spd) { + read_spd (&spd[0], 0x50); + read_spd (&spd[1], 0x51); + read_spd (&spd[2], 0x52); + read_spd (&spd[3], 0x53); +} + +#if 0 +static void dmi_config(void) +{ + DMIBAR32(0x0218) = 0x06aa0b0c; + DMIBAR32(0x021c) = 0x0b0d0b0d; + DMIBAR32(0x0300) = 0x0011028d; + DMIBAR32(0x0304) = 0x002102cd; + DMIBAR32(0x030c) = 0x007d004b; + DMIBAR32(0x0310) = 0x007e004c; + DMIBAR32(0x0318) = 0x002304ad; + DMIBAR32(0x031c) = 0x003304ed; + DMIBAR32(0x03b8) = 0x005c05a4; + DMIBAR32(0x03bc) = 0x006c05e4; + DMIBAR32(0x0530) = 0x41d3b000; + DMIBAR32(0x0534) = 0x00019f80; + DMIBAR32(0x0ba4) = 0x0000000d; + DMIBAR32(0x0d80) = 0x1c9cfc0b; + DMIBAR32(0x0e1c) = 0x20000000; + DMIBAR32(0x0e2c) = 0x20000000; +} +#endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h new file mode 100644 index 0000000..ed08c8a --- /dev/null +++ b/src/mainboard/gigabyte/ga-b75m-d3h/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GAB75MD3H_THERMAL_H +#define GAB75MD3H_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif

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New patch to review for coreboot: 9b301e2 3rdparty: Update to latest commit in blobs repository
by Paul Menzel 28 Nov '14

28 Nov '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7595 -gerrit commit 9b301e21b2551a8a359f0b09fce956298d77acf8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Nov 27 13:37:37 2014 +0100 3rdparty: Update to latest commit in blobs repository Update to commit 9f68e20e (AMD KaveriPI: Add PI header files to support binary AGESA release), which is the latest commit in the blobs repository. Change-Id: I3d643f7565700272c22b59ed764c3269801f4413 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- 3rdparty | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty b/3rdparty index 27bdb5e..9f68e20 160000 --- a/3rdparty +++ b/3rdparty @@ -1 +1 @@ -Subproject commit 27bdb5e8a61274e3a59a13dd13dd8b4b649de68c +Subproject commit 9f68e20e5ef4b6681fb18bdb4022471bc6810788

1 0

New patch to review for coreboot: 73f57c6 vendorcode/amd/agesa: Make Porting.h common between families
by Edward O'Callaghan 28 Nov '14

28 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7594 -gerrit commit 73f57c6474c699155e24c80c23785439fcbae4a2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Nov 28 22:26:45 2014 +1100 vendorcode/amd/agesa: Make Porting.h common between families Change-Id: Ica17b2452498f30b710533caf610c9f0c1a0452c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/Porting.h | 282 ++++++++++++++++++++++++++++ src/vendorcode/amd/agesa/f10/Makefile.inc | 1 + src/vendorcode/amd/agesa/f10/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f12/Makefile.inc | 1 + src/vendorcode/amd/agesa/f12/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f14/Makefile.inc | 1 + src/vendorcode/amd/agesa/f14/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f15/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 1 + src/vendorcode/amd/agesa/f15tn/Porting.h | 282 ---------------------------- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 1 + src/vendorcode/amd/agesa/f16kb/Porting.h | 282 ---------------------------- 13 files changed, 288 insertions(+), 1692 deletions(-) diff --git a/src/vendorcode/amd/agesa/Porting.h b/src/vendorcode/amd/agesa/Porting.h new file mode 100644 index 0000000..fc65cfc --- /dev/null +++ b/src/vendorcode/amd/agesa/Porting.h @@ -0,0 +1,282 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Describes compiler dependencies - to support several compile time environments + * + * Contains compiler environment porting descriptions + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Includes + * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ + */ +/***************************************************************************** + * + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _PORTING_H_ +#define _PORTING_H_ + +#if defined (_MSC_VER) + #include <intrin.h> + void _disable (void); + void _enable (void); + #pragma warning(disable: 4103 4001 4733) + #pragma intrinsic (_disable, _enable) + #pragma warning(push) + // ----------------------------------------------------------------------- + // Define a code_seg MACRO + // + #define MAKE_AS_A_STRING(arg) #arg + + #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) + + #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) + #define FUNC_ATTRIBUTE(arg) __declspec(arg) + //#include <intrin.h> // MS has built-in functions + + #if _MSC_VER < 900 + // ----------------------------------------------------------------------- + // Assume MSVC 1.52C (16-bit) + // + // NOTE: When using MSVC 1.52C use the following command line: + // + // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> + // + // This will produce 32-bit code in USE16 segment that is optimized for code + // size. + typedef void VOID; + + // Create the universal 32, 16, and 8-bit data types + typedef unsigned long UINTN; + typedef long INT32; + typedef unsigned long UINT32; + typedef int INT16; + typedef unsigned int UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + /// struct for 16-bit environment handling of 64-bit value + typedef struct _UINT64 { + IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value + IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value + } UINT64; + + // Create the Boolean type + #define TRUE 1 + #define FALSE 0 + typedef unsigned char BOOLEAN; + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV __pascal + #define ROMDATA __based( __segname( "_CODE" ) ) + #define _16BYTE_ALIGN __declspec(align(16)) + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning + #pragma pack(1) + + // Disable WORD->BYTE automatic conversion warnings. Example: + // BYTE LocalByte; + // void MyFunc(BYTE val); + // + // MyFunc(LocalByte*2+1); // Warning, automatic conversion + // + // The problem is any time math is performed on a BYTE, it is converted to a + // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning + // is generated. Disable warning C4761 + #pragma warning( disable : 4761 ) + + #else + // ----------------------------------------------------------------------- + // Assume a 32-bit MSVC++ + // + // Disable the following warnings: + // 4100 - 'identifier' : unreferenced formal parameter + // 4276 - 'function' : no prototype provided; assumed no parameters + // 4214 - non standard extension used : bit field types other than int + // 4001 - nonstandard extension 'single line comment' was used + // 4142 - benign redefinition of type for following declaration + // - typedef char INT8 + #if defined (_M_IX86) + #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) + + #ifndef VOID + typedef void VOID; + #endif + // Create the universal 32, 16, and 8-bit data types + #ifndef UINTN + typedef unsigned __w64 UINTN; + #endif + typedef __int64 INT64; + typedef unsigned __int64 UINT64; + typedef int INT32; + typedef unsigned int UINT32; + typedef short INT16; + typedef unsigned short UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + // Create the Boolean type + #ifndef TRUE + #define TRUE 1 + #endif + #ifndef FALSE + #define FALSE 0 + #endif + typedef unsigned char BOOLEAN; + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma pack(1) + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV + #define ROMDATA + #define _16BYTE_ALIGN __declspec(align(64)) + // 64 bit of compiler + #else + #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) + + #ifndef VOID + typedef void VOID; + #endif + // Create the universal 32, 16, and 8-bit data types + #ifndef UINTN + typedef unsigned __int64 UINTN; + #endif + typedef __int64 INT64; + typedef unsigned __int64 UINT64; + typedef int INT32; + typedef unsigned int UINT32; + typedef short INT16; + typedef unsigned short UINT16; + typedef char INT8; + typedef unsigned char UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; + + // Create the Boolean type + #ifndef TRUE + #define TRUE 1 + #endif + #ifndef FALSE + #define FALSE 0 + #endif + typedef unsigned char BOOLEAN; + + // Force tight packing of structures + // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 + #pragma pack(1) + + #define CONST const + #define STATIC static + #define VOLATILE volatile + #define CALLCONV + #define ROMDATA + #endif + #endif + // ----------------------------------------------------------------------- + // End of MS compiler versions + +#elif defined __GNUC__ + + #define IN + #define OUT + #define STATIC static + #define VOLATILE volatile + #define TRUE 1 + #define FALSE 0 +// #undef CONST + #define CONST const + #define ROMDATA + #define CALLCONV + #define _16BYTE_ALIGN __attribute__ ((aligned (16))) + + typedef unsigned char BOOLEAN; + typedef signed char INT8; + typedef signed short INT16; + typedef signed long INT32; + typedef char CHAR8; + typedef unsigned char UINT8; + typedef unsigned short UINT16; + typedef unsigned long UINT32; + typedef unsigned long UINTN; + typedef unsigned long long UINT64; + typedef long long INT64; + typedef void VOID; + //typedef unsigned long size_t; + + //#include <intrin.h> // MingW-w64 library header +#pragma pack(1) + +#define CODE_GROUP(arg) +#define RDATA_GROUP(arg) + +#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) +#define MAKE_AS_A_STRING(arg) #arg +#include <stddef.h> +#include "gcc-intrin.h" + +#include <assert.h> +#include <console/console.h> +#include <console/loglevel.h> + +#ifndef NULL + #define NULL (void *)0 +#endif + +#else + // ----------------------------------------------------------------------- + // Unknown or unsupported compiler + // + #error "Unknown compiler in use" +#endif + +// ----------------------------------------------------------------------- +// Common definitions for all compilers +// + +//Support forward reference construct +#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x + +// The following are use in conformance to the UEFI style guide +#define IN +#define OUT + +#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc index b684a29..2d7e60c 100644 --- a/src/vendorcode/amd/agesa/f10/Makefile.inc +++ b/src/vendorcode/amd/agesa/f10/Makefile.inc @@ -22,6 +22,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f10 AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f10/Porting.h b/src/vendorcode/amd/agesa/f10/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f10/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index b7f9d92..c4578d5 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -32,6 +32,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f12 AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family AGESA_INC += -I$(AGESA_ROOT)/Include diff --git a/src/vendorcode/amd/agesa/f12/Porting.h b/src/vendorcode/amd/agesa/f12/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f12/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 0f570d7..5e36684 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -32,6 +32,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f14 AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f14/Porting.h b/src/vendorcode/amd/agesa/f14/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f14/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index 7c1359e..f086e4e 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -22,6 +22,7 @@ AGESA_ROOT ?= $(PWD) AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f15/Porting.h b/src/vendorcode/amd/agesa/f15/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f15/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 4b44cef..db932e5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -32,6 +32,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f15tn AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f15tn/Porting.h b/src/vendorcode/amd/agesa/f15tn/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f15tn/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 164b305..0708dc3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -32,6 +32,7 @@ AGESA_ROOT = src/vendorcode/amd/agesa/f16kb AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) +AGESA_INC += -I$(AGESA_ROOT)../ AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib AGESA_INC += -I$(AGESA_ROOT)/Legacy diff --git a/src/vendorcode/amd/agesa/f16kb/Porting.h b/src/vendorcode/amd/agesa/f16kb/Porting.h deleted file mode 100644 index fc65cfc..0000000 --- a/src/vendorcode/amd/agesa/f16kb/Porting.h +++ /dev/null @@ -1,282 +0,0 @@ -/* $NoKeywords:$ */ -/** - * @file - * - * Describes compiler dependencies - to support several compile time environments - * - * Contains compiler environment porting descriptions - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Includes - * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $ - */ -/***************************************************************************** - * - * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ***************************************************************************/ - -#ifndef _PORTING_H_ -#define _PORTING_H_ - -#if defined (_MSC_VER) - #include <intrin.h> - void _disable (void); - void _enable (void); - #pragma warning(disable: 4103 4001 4733) - #pragma intrinsic (_disable, _enable) - #pragma warning(push) - // ----------------------------------------------------------------------- - // Define a code_seg MACRO - // - #define MAKE_AS_A_STRING(arg) #arg - - #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg))) - - #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg))) - #define FUNC_ATTRIBUTE(arg) __declspec(arg) - //#include <intrin.h> // MS has built-in functions - - #if _MSC_VER < 900 - // ----------------------------------------------------------------------- - // Assume MSVC 1.52C (16-bit) - // - // NOTE: When using MSVC 1.52C use the following command line: - // - // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C> - // - // This will produce 32-bit code in USE16 segment that is optimized for code - // size. - typedef void VOID; - - // Create the universal 32, 16, and 8-bit data types - typedef unsigned long UINTN; - typedef long INT32; - typedef unsigned long UINT32; - typedef int INT16; - typedef unsigned int UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - /// struct for 16-bit environment handling of 64-bit value - typedef struct _UINT64 { - IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value - IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value - } UINT64; - - // Create the Boolean type - #define TRUE 1 - #define FALSE 0 - typedef unsigned char BOOLEAN; - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV __pascal - #define ROMDATA __based( __segname( "_CODE" ) ) - #define _16BYTE_ALIGN __declspec(align(16)) - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning - #pragma pack(1) - - // Disable WORD->BYTE automatic conversion warnings. Example: - // BYTE LocalByte; - // void MyFunc(BYTE val); - // - // MyFunc(LocalByte*2+1); // Warning, automatic conversion - // - // The problem is any time math is performed on a BYTE, it is converted to a - // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning - // is generated. Disable warning C4761 - #pragma warning( disable : 4761 ) - - #else - // ----------------------------------------------------------------------- - // Assume a 32-bit MSVC++ - // - // Disable the following warnings: - // 4100 - 'identifier' : unreferenced formal parameter - // 4276 - 'function' : no prototype provided; assumed no parameters - // 4214 - non standard extension used : bit field types other than int - // 4001 - nonstandard extension 'single line comment' was used - // 4142 - benign redefinition of type for following declaration - // - typedef char INT8 - #if defined (_M_IX86) - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __w64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #define _16BYTE_ALIGN __declspec(align(64)) - // 64 bit of compiler - #else - #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366) - - #ifndef VOID - typedef void VOID; - #endif - // Create the universal 32, 16, and 8-bit data types - #ifndef UINTN - typedef unsigned __int64 UINTN; - #endif - typedef __int64 INT64; - typedef unsigned __int64 UINT64; - typedef int INT32; - typedef unsigned int UINT32; - typedef short INT16; - typedef unsigned short UINT16; - typedef char INT8; - typedef unsigned char UINT8; - typedef char CHAR8; - typedef unsigned short CHAR16; - - // Create the Boolean type - #ifndef TRUE - #define TRUE 1 - #endif - #ifndef FALSE - #define FALSE 0 - #endif - typedef unsigned char BOOLEAN; - - // Force tight packing of structures - // Note: Entire AGESA (Project / Solution) will be using pragma pack 1 - #pragma pack(1) - - #define CONST const - #define STATIC static - #define VOLATILE volatile - #define CALLCONV - #define ROMDATA - #endif - #endif - // ----------------------------------------------------------------------- - // End of MS compiler versions - -#elif defined __GNUC__ - - #define IN - #define OUT - #define STATIC static - #define VOLATILE volatile - #define TRUE 1 - #define FALSE 0 -// #undef CONST - #define CONST const - #define ROMDATA - #define CALLCONV - #define _16BYTE_ALIGN __attribute__ ((aligned (16))) - - typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; - typedef void VOID; - //typedef unsigned long size_t; - - //#include <intrin.h> // MingW-w64 library header -#pragma pack(1) - -#define CODE_GROUP(arg) -#define RDATA_GROUP(arg) - -#define FUNC_ATTRIBUTE(arg) __attribute__((arg)) -#define MAKE_AS_A_STRING(arg) #arg -#include <stddef.h> -#include "gcc-intrin.h" - -#include <assert.h> -#include <console/console.h> -#include <console/loglevel.h> - -#ifndef NULL - #define NULL (void *)0 -#endif - -#else - // ----------------------------------------------------------------------- - // Unknown or unsupported compiler - // - #error "Unknown compiler in use" -#endif - -// ----------------------------------------------------------------------- -// Common definitions for all compilers -// - -//Support forward reference construct -#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x - -// The following are use in conformance to the UEFI style guide -#define IN -#define OUT - -#endif // _PORTING_H_

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New patch to review for coreboot: daa64ad mainboard/lenovo/g505s/devicetree.cb: Disable pci 14.4 bridge
by Edward O'Callaghan 28 Nov '14

28 Nov '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7593 -gerrit commit daa64ad12b1f337b30b8e37f235336e1752b9470 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Nov 28 20:36:36 2014 +1100 mainboard/lenovo/g505s/devicetree.cb: Disable pci 14.4 bridge 14.4 does not seem to be writed on the board even though it is enabled in the vendor BIOS. Disable as it seems to help with S3 working for some reason. It is also a bad idea to drive unconnected pins. Change-Id: Ibd95e3fb4bed6a9ff7d98e76c07139c81b4e4df5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 4dc4a14..cc0bedc 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -64,7 +64,7 @@ chip northbridge/amd/agesa/family15rl/root_complex device pnp ff.1 on end # dummy address end end - device pci 14.4 on end # FCH PCI Bridge [1022:780f] + device pci 14.4 off end # FCH PCI Bridge [1022:780f] (disabled for S3 to work) device pci 14.5 off end # USB 2 device pci 14.6 off end # Gec device pci 14.7 off end # SD

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coreboot-gerrit November 2014