coreboot-gerrit November 2014

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Patch set updated for coreboot: d05f2b1 AGESA: Report events with AGESA_EVENTLOG()
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7154 -gerrit commit d05f2b15d4d7d3104d6f691cbfaba6d560a59bad Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 14:19:04 2014 +0300 AGESA: Report events with AGESA_EVENTLOG() NOTE: For fam12 and fam14 ASSERT() is defined empty so execution may fall through critical failures. Change-Id: Ifef65d749d340f1df3a43b5fcb38c4315ef944e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/agesawrapper.c | 23 ++++++-------- src/mainboard/amd/inagua/agesawrapper.c | 22 ++++++------- src/mainboard/amd/olivehill/agesawrapper.c | 35 ++++++++------------- src/mainboard/amd/parmer/agesawrapper.c | 35 ++++++++------------- src/mainboard/amd/persimmon/agesawrapper.c | 36 +++++++++------------- src/mainboard/amd/south_station/agesawrapper.c | 22 ++++++------- src/mainboard/amd/thatcher/agesawrapper.c | 35 ++++++++------------- src/mainboard/amd/torpedo/agesawrapper.c | 18 +++++------ src/mainboard/amd/union_station/agesawrapper.c | 22 ++++++------- src/mainboard/asrock/e350m1/agesawrapper.c | 22 ++++++------- src/mainboard/asrock/imb-a180/agesawrapper.c | 35 ++++++++------------- src/mainboard/asus/f2a85-m/agesawrapper.c | 35 ++++++++------------- src/mainboard/gizmosphere/gizmo/agesawrapper.c | 36 +++++++++------------- src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 35 ++++++++------------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 36 +++++++++------------- src/mainboard/lenovo/g505s/agesawrapper.c | 35 ++++++++------------- .../lippert/frontrunner-af/agesawrapper.c | 36 +++++++++------------- src/mainboard/lippert/toucan-af/agesawrapper.c | 36 +++++++++------------- src/mainboard/supermicro/h8qgi/agesawrapper.c | 30 +++++++----------- src/mainboard/supermicro/h8scm/agesawrapper.c | 28 ++++++----------- src/mainboard/tyan/s8226/agesawrapper.c | 28 ++++++----------- src/northbridge/amd/agesa/agesawrapper.h | 1 + src/northbridge/amd/agesa/agesawrapper_call.h | 9 ++++++ 23 files changed, 252 insertions(+), 398 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index fd9f637..07cbcb9 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -280,7 +280,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); #else status = AGESA_SUCCESS; @@ -312,7 +312,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -369,7 +369,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -396,7 +396,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -454,7 +454,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -485,11 +485,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate(AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - //agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; AcpiSrat = AmdLateParamsPtr->AcpiSrat; @@ -527,10 +524,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *Conf AmdLateParams.StdHeader.ImageBasePtr = 0; Status = AmdLateRunApTask (&AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c index cee9d6c..343f22c 100644 --- a/src/mainboard/amd/inagua/agesawrapper.c +++ b/src/mainboard/amd/inagua/agesawrapper.c @@ -167,7 +167,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -194,7 +194,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -218,7 +218,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -246,7 +246,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -371,7 +371,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -400,10 +400,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -445,10 +443,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index f58c6bb..22522db 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -165,7 +165,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -193,7 +193,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -220,7 +220,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost (PostParams); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -249,7 +249,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv (EnvParam); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -309,7 +309,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -338,10 +338,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; Status = AmdInitLate(AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; AcpiPstate = AmdLateParams->AcpiPState; @@ -386,10 +384,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - /* agesawrapper_amdreadeventlog(); */ - ASSERT(Status == AGESA_SUCCESS); - } + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -426,7 +421,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -487,10 +482,8 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -560,10 +553,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 2f58f38..c457fa3 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -165,7 +165,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -193,7 +193,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -220,7 +220,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost (PostParams); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -250,7 +250,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv (EnvParam); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -310,7 +310,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -339,10 +339,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; Status = AmdInitLate(AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; AcpiPstate = AmdLateParams->AcpiPState; @@ -387,10 +385,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - /* agesawrapper_amdreadeventlog(); */ - ASSERT(Status == AGESA_SUCCESS); - } + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -427,7 +422,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -489,10 +484,8 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -563,10 +556,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index a9eda6b..991e080 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -166,7 +166,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -193,7 +193,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -217,7 +217,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -245,7 +245,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -370,7 +370,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -399,10 +399,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -456,7 +454,7 @@ AGESA_STATUS agesawrapper_amdinitresume ( status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -492,10 +490,8 @@ AGESA_STATUS agesawrapper_amds3laterestore ( (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -525,10 +521,8 @@ AGESA_STATUS agesawrapper_amdS3Save ( AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save (AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; @@ -573,10 +567,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c index f743202..8a7a243 100644 --- a/src/mainboard/amd/south_station/agesawrapper.c +++ b/src/mainboard/amd/south_station/agesawrapper.c @@ -167,7 +167,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -194,7 +194,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -218,7 +218,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -246,7 +246,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -371,7 +371,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -400,10 +400,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -440,10 +438,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 289f078..cc3c069 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -165,7 +165,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -193,7 +193,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -220,7 +220,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost (PostParams); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -249,7 +249,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv (EnvParam); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -309,7 +309,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -338,10 +338,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; Status = AmdInitLate(AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; AcpiPstate = AmdLateParams->AcpiPState; @@ -386,10 +384,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - /* agesawrapper_amdreadeventlog(); */ - ASSERT(Status == AGESA_SUCCESS); - } + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -428,7 +423,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -491,10 +486,8 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) #endif Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -564,10 +557,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 30a919c..0538797 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -293,7 +293,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -323,7 +323,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -350,7 +350,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -379,7 +379,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -438,7 +438,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -462,10 +462,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( AmdLateParams.StdHeader.ImageBasePtr = 0; Status = AmdInitLate (&AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(Status); ASSERT(Status == AGESA_SUCCESS); - } DmiTable = AmdLateParams.DmiTable; AcpiPstate = AmdLateParams.AcpiPState; @@ -495,10 +493,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *Conf ApExeParams.StdHeader.ImageBasePtr = 0; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(Status); ASSERT(Status == AGESA_SUCCESS); - } return Status; } diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c index f743202..8a7a243 100644 --- a/src/mainboard/amd/union_station/agesawrapper.c +++ b/src/mainboard/amd/union_station/agesawrapper.c @@ -167,7 +167,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -194,7 +194,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -218,7 +218,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -246,7 +246,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -371,7 +371,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -400,10 +400,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -440,10 +438,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index ed0b5dd..fc19e1d 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -223,7 +223,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -247,7 +247,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -275,7 +275,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -400,7 +400,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -429,10 +429,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -469,10 +467,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 8c24a7f..62fc053 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -194,7 +194,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -249,7 +249,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost (PostParams); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -278,7 +278,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv (EnvParam); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -338,7 +338,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -367,10 +367,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; Status = AmdInitLate(AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; AcpiPstate = AmdLateParams->AcpiPState; @@ -415,10 +413,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - /* agesawrapper_amdreadeventlog(); */ - ASSERT(Status == AGESA_SUCCESS); - } + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -455,7 +450,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -516,10 +511,8 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -589,10 +582,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index 4f4d2f8..2a5f5c8 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -178,7 +178,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -206,7 +206,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -233,7 +233,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost (PostParams); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -262,7 +262,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv (EnvParam); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -322,7 +322,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -351,10 +351,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; Status = AmdInitLate(AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; AcpiPstate = AmdLateParams->AcpiPState; @@ -399,10 +397,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - /* agesawrapper_amdreadeventlog(); */ - ASSERT(Status == AGESA_SUCCESS); - } + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -441,7 +436,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -504,10 +499,8 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) #endif Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -577,10 +570,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", diff --git a/src/mainboard/gizmosphere/gizmo/agesawrapper.c b/src/mainboard/gizmosphere/gizmo/agesawrapper.c index 129c162..1ec8782 100755 --- a/src/mainboard/gizmosphere/gizmo/agesawrapper.c +++ b/src/mainboard/gizmosphere/gizmo/agesawrapper.c @@ -186,7 +186,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -213,7 +213,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -237,7 +237,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -265,7 +265,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -390,7 +390,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -419,10 +419,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -476,7 +474,7 @@ AGESA_STATUS agesawrapper_amdinitresume ( status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -512,10 +510,8 @@ AGESA_STATUS agesawrapper_amds3laterestore ( (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -545,10 +541,8 @@ AGESA_STATUS agesawrapper_amdS3Save ( AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save (AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; @@ -593,10 +587,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 024011b..5de359e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -179,7 +179,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -207,7 +207,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -234,7 +234,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost (PostParams); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -263,7 +263,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv (EnvParam); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -323,7 +323,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -352,10 +352,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; Status = AmdInitLate(AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; AcpiPstate = AmdLateParams->AcpiPState; @@ -400,10 +398,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - /* agesawrapper_amdreadeventlog(); */ - ASSERT(Status == AGESA_SUCCESS); - } + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -440,7 +435,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -502,10 +497,8 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -576,10 +569,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index f82388d..46c0faf 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -173,7 +173,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -195,7 +195,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -221,7 +221,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -341,7 +341,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -368,10 +368,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); status = AmdInitLate (AmdLateParamsPtr); - if (status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(status); + ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -423,7 +421,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -457,10 +455,8 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(status); + ASSERT(status == AGESA_SUCCESS); return status; } @@ -488,10 +484,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; status = AmdS3Save (AmdS3SaveParamsPtr); - if (status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(status); + ASSERT(status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; @@ -532,10 +526,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *Conf ApExeParams.RelatedDataBlock = ConfigPtr; status = AmdLateRunApTask (&ApExeParams); - if (status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(status); + ASSERT(status == AGESA_SUCCESS); return status; } diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c index 024011b..5de359e 100644 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ b/src/mainboard/lenovo/g505s/agesawrapper.c @@ -179,7 +179,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -207,7 +207,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -234,7 +234,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost (PostParams); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -263,7 +263,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv (EnvParam); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -323,7 +323,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -352,10 +352,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; Status = AmdInitLate(AmdLateParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; AcpiPstate = AmdLateParams->AcpiPState; @@ -400,10 +398,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - /* agesawrapper_amdreadeventlog(); */ - ASSERT(Status == AGESA_SUCCESS); - } + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -440,7 +435,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); return status; @@ -502,10 +497,8 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -576,10 +569,8 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", diff --git a/src/mainboard/lippert/frontrunner-af/agesawrapper.c b/src/mainboard/lippert/frontrunner-af/agesawrapper.c index ffeb08d..480ad27 100644 --- a/src/mainboard/lippert/frontrunner-af/agesawrapper.c +++ b/src/mainboard/lippert/frontrunner-af/agesawrapper.c @@ -185,7 +185,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -212,7 +212,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -236,7 +236,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -264,7 +264,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -389,7 +389,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -418,10 +418,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -475,7 +473,7 @@ AGESA_STATUS agesawrapper_amdinitresume ( status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -511,10 +509,8 @@ AGESA_STATUS agesawrapper_amds3laterestore ( (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -544,10 +540,8 @@ AGESA_STATUS agesawrapper_amdS3Save ( AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save (AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; @@ -592,10 +586,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/lippert/toucan-af/agesawrapper.c b/src/mainboard/lippert/toucan-af/agesawrapper.c index ffeb08d..480ad27 100644 --- a/src/mainboard/lippert/toucan-af/agesawrapper.c +++ b/src/mainboard/lippert/toucan-af/agesawrapper.c @@ -185,7 +185,7 @@ AGESA_STATUS agesawrapper_amdinitreset ( AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; } @@ -212,7 +212,7 @@ AGESA_STATUS agesawrapper_amdinitearly ( OemCustomizeInitEarly (AmdEarlyParamsPtr); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -236,7 +236,7 @@ AGESA_STATUS agesawrapper_amdinitpost ( AmdCreateStruct (&AmdParamStruct); status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); /* Initialize heap space */ @@ -264,7 +264,7 @@ AGESA_STATUS agesawrapper_amdinitenv ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -389,7 +389,7 @@ AGESA_STATUS agesawrapper_amdinitmid ( AmdCreateStruct (&AmdParamStruct); status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -418,10 +418,8 @@ AGESA_STATUS agesawrapper_amdinitlate ( printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate (AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; @@ -475,7 +473,7 @@ AGESA_STATUS agesawrapper_amdinitresume ( status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); + AGESA_EVENTLOG(status); AmdReleaseStruct (&AmdParamStruct); return status; @@ -511,10 +509,8 @@ AGESA_STATUS agesawrapper_amds3laterestore ( (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } @@ -544,10 +540,8 @@ AGESA_STATUS agesawrapper_amdS3Save ( AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; Status = AmdS3Save (AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; @@ -592,10 +586,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( ApExeParams.RelatedDataBlock = ConfigPtr; Status = AmdLateRunApTask (&ApExeParams); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status); + ASSERT(Status == AGESA_SUCCESS); return Status; } diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 6facc19..30bb996 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -237,8 +237,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); #endif - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -272,8 +271,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly(AmdEarlyParamsPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); @@ -309,9 +307,8 @@ AGESA_STATUS agesawrapper_amdinitpost(void) } PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - if (status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); - } + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -348,8 +345,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) } EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParams); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -407,8 +403,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) return status; } status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -438,10 +433,9 @@ AGESA_STATUS agesawrapper_amdinitlate(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate(AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParamsPtr->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; AcpiSrat = AmdLateParamsPtr->AcpiSrat; @@ -485,10 +479,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *Conf printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data); Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); - ASSERT(Status <= AGESA_UNSUPPORTED); - } + AGESA_EVENTLOG(Status, AmdLateParams.StdHeader.HeapStatus); + ASSERT((Status == AGESA_SUCCESS) || (Status == AGESA_UNSUPPORTED)); return Status; } diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index f738f42..d7a1c23 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -237,8 +237,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); #endif - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -272,8 +271,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly(AmdEarlyParamsPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); @@ -309,9 +307,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) } PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - if (status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); - } + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -348,8 +344,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) } EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParams); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -407,8 +402,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) return status; } status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -438,10 +432,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate(AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParamsPtr->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; AcpiSrat = AmdLateParamsPtr->AcpiSrat; @@ -485,10 +477,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *Conf printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data); Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); - ASSERT(Status <= AGESA_UNSUPPORTED); - } + AGESA_EVENTLOG(Status, AmdLateParams.StdHeader.HeapStatus); + ASSERT((Status == AGESA_SUCCESS) || (Status == AGESA_UNSUPPORTED)); return Status; } diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 4cc8e18..36aa35a 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -244,8 +244,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); #endif - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -279,8 +278,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly(AmdEarlyParamsPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); @@ -316,9 +314,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) } PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - if (status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); - } + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -355,8 +351,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) } EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParams); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -414,8 +409,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) return status; } status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - if (status != AGESA_SUCCESS) - agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct(&AmdParamStruct); return status; @@ -445,10 +439,8 @@ AGESA_STATUS agesawrapper_amdinitlate(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); Status = AmdInitLate(AmdLateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } + AGESA_EVENTLOG(Status, AmdLateParamsPtr->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; AcpiPstate = AmdLateParamsPtr->AcpiPState; AcpiSrat = AmdLateParamsPtr->AcpiSrat; @@ -492,10 +484,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *Conf printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data); Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); - ASSERT(Status <= AGESA_UNSUPPORTED); - } + AGESA_EVENTLOG(Status, AmdLateParams.StdHeader.HeapStatus); + ASSERT((Status == AGESA_SUCCESS) || (Status == AGESA_UNSUPPORTED)); return Status; } diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index 72c9673..b18f43d 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -23,6 +23,7 @@ #include <stdint.h> #include "Porting.h" #include "AGESA.h" +#include <northbridge/amd/agesa/agesawrapper_call.h> /* Define AMD Ontario APPU SSID/SVID */ #define AMD_APU_SVID 0x1022 diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h index 792c3b1..0ddeb76 100644 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ b/src/northbridge/amd/agesa/agesawrapper_call.h @@ -59,4 +59,13 @@ static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) #define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func() +#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_BOARD_AMD_DINAR + /* TODO: These families do not pass valid HeapStatus. */ +#define AGESA_EVENTLOG(status) \ + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog() +#else +#define AGESA_EVENTLOG(status, heapstatus) \ + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus) +#endif + #endif

1 0

Patch set updated for coreboot: 6951457 AGESA fam15: Common agesawrapper
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7155 -gerrit commit 695145725186738decb14741d88802eccef27fcf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Oct 22 15:53:34 2014 +0300 AGESA fam15: Common agesawrapper Place empty OemCustomizeInitEarly() and OemCustomInitPost() in a common file for now and split eventlog parser to a separate file. Change-Id: Ia8277ad13a800898b3e1a4e9c8fbd838ae2efeae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/agesawrapper.c | 459 ++------ src/mainboard/supermicro/h8qgi/Makefile.inc | 4 - src/mainboard/supermicro/h8qgi/agesawrapper.c | 1181 --------------------- src/mainboard/supermicro/h8qgi/platform_oem.c | 49 - src/mainboard/supermicro/h8scm/Makefile.inc | 4 - src/mainboard/supermicro/h8scm/agesawrapper.c | 1179 -------------------- src/mainboard/supermicro/h8scm/platform_oem.c | 49 - src/mainboard/tyan/s8226/Makefile.inc | 4 - src/mainboard/tyan/s8226/agesawrapper.c | 1179 -------------------- src/mainboard/tyan/s8226/platform_oem.c | 49 - src/northbridge/amd/agesa/Makefile.inc | 3 + src/northbridge/amd/agesa/agesawrapper.h | 2 +- src/northbridge/amd/agesa/agesawrapper_call.h | 2 +- src/northbridge/amd/agesa/eventlog.c | 700 ++++++++++++ src/northbridge/amd/agesa/family15/Makefile.inc | 2 + src/northbridge/amd/agesa/family15/agesawrapper.c | 448 ++++++++ 16 files changed, 1222 insertions(+), 4092 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 07cbcb9..9454e17 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -38,18 +38,6 @@ #define FILECODE UNASSIGNED_FILE_FILECODE -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - /*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ /* BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the @@ -62,17 +50,13 @@ Bits Buses Bits Buses 3h 8 8h 256 4h 16 Fh-9h Reserved */ -STATIC -UINT8 -GetEndBusNum ( - VOID - ) +STATIC UINT8 GetEndBusNum(VOID) { - UINT64 BusNum; - UINT8 Index; - for (Index = 1; Index <= 8; Index ++ ) { + UINT64 BusNum; + UINT8 Index; + for (Index = 1; Index <= 8; Index++) { BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index; - if (BusNum == 1 ) { + if (BusNum == 1) { break; } } @@ -81,93 +65,92 @@ GetEndBusNum ( AGESA_STATUS agesawrapper_amdinitcpuio(void) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 TopMem; - UINT32 NodeCnt; - UINT32 Node; - UINT32 SbLink; - UINT32 Index; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 TopMem; + UINT32 nodes; + UINT32 node; + UINT32 SbLink; + UINT32 i; /* get the number of coherent nodes in the system */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60); LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - NodeCnt = ((PciData >> 4) & 7) + 1; //NodeCnt[6:4] + nodes = ((PciData >> 4) & 7) + 1; //nodes[6:4] /* Find out the Link ID of Node0 that connects to the * Southbridge (system IO hub). e.g. family10 MCM Processor, * SbLink is Processor0 Link2, internal Node0 Link3 */ PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64); LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - SbLink = (PciData >> 8) & 3; //assume ganged + SbLink = (PciData >> 8) & 3; //assume ganged /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ - for (Node = 0; Node < NodeCnt; Node ++) { + for (node = 0; node < nodes; node++) { /* clear all MMIO Mapped Base/Limit Registers */ - for (Index = 0; Index < 8; Index ++) { + for (i = 0; i < 8; i++) { PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x80 + Index * 8); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x84 + Index * 8); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } /* clear all IO Space Base/Limit Registers */ - for (Index = 0; Index < 4; Index ++) { + for (i = 0; i < 4; i++) { PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC0 + Index * 8); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC4 + Index * 8); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } /* Enable MMIO on AMD CPU Address Map Controller */ /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x80); - PciData = (0xA0000 >> 8) |3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); + PciData = (0xA0000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x84); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); PciData = 0xB0000 >> 8; PciData &= (~0xFF); PciData |= SbLink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set UMA MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x88); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - TopMem = (UINT32)MsrReg; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + TopMem = (UINT32) MsrReg; MsrReg = (MsrReg >> 8) | 3; - PciData = (UINT32)MsrReg; + PciData = (UINT32) MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x8c); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8c); if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) { - PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; - } - else { - PciData = (0x100000000ull - 1) >> 8; + PciData = (CONFIG_MMCONF_BASE_ADDRESS - 1) >> 8; + } else { + PciData = (0x100000000ull - 1) >> 8; } PciData &= (~0xFF); PciData |= SbLink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set PCIE MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x90); - PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x90); + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x94); - PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) & (~0xFF); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x94); + PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) & (~0xFF); PciData &= (~0xFF); PciData |= MMIO_NP_BIT; PciData |= SbLink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set XAPIC MMIO. 24K */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x98); - PciData = (0xFEC00000 >> 8) |3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x98); + PciData = (0xFEC00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x9c); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x9c); PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8); PciData &= (~0xFF); PciData |= MMIO_NP_BIT; @@ -175,21 +158,21 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void) LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA0); - PciData = (0xFEE00000 >> 8) |3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA0); + PciData = (0xFEE00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA8); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xA8); PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8; PciData &= (~0xFF); PciData |= MMIO_NP_BIT; PciData |= SbLink << 4; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO*/ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC0); + /* Set PCIO: 0x0 - 0xFFF000 and enabled VGA IO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); PciData = 0x13; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); PciData = 0x00FFF000; PciData &= (~0x7F); PciData |= SbLink << 4; @@ -201,356 +184,48 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void) AGESA_STATUS agesawrapper_amdinitmmio(void) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + AGESA_STATUS Status; + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; /* Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum () << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum() << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); MsrReg = MsrReg | BIT46; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* Set PCIE MMIO. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x90); - - PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x90); + PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x94); - PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) | MMIO_NP_BIT; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x94); + PciData = ((CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 * 256 - 1) >> 8) | MMIO_NP_BIT; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Enable memory access */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); - PciData |= BIT1; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20E, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20F, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; return Status; } - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; -#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; -#endif - -#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); - AmdReleaseStruct (&AmdParamStruct); -#else - status = AGESA_SUCCESS; -#endif - - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) -{ - //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; -} - -static VOID -OemCustomizeInitPost ( - IN AMD_POST_PARAMS *InitPost - ) -{ - InitPost->MemConfig.UmaMode = UMA_AUTO; - InitPost->MemConfig.BottomIo = 0xE0; - InitPost->MemConfig.UmaSize = 0xE0-0xC0; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - /* OEM Should Customize the defaults through this hook */ - OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - - status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); - AmdReleaseStruct (&AmdParamStruct); - - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - - case PICK_PSTATE: - return AcpiPstate; - - case PICK_SRAT: - return AcpiSrat; - - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - printk(BIOS_DEBUG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParamsPtr; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - - AmdCreateStruct (&AmdParamStruct); - AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - - printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); - - Status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(Status); - ASSERT(Status == AGESA_SUCCESS); - DmiTable = AmdLateParamsPtr->DmiTable; - AcpiPstate = AmdLateParamsPtr->AcpiPState; - AcpiSrat = AmdLateParamsPtr->AcpiSrat; - AcpiSlit = AmdLateParamsPtr->AcpiSlit; - AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; - AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; - AcpiAlib = AmdLateParamsPtr->AcpiAlib; - - printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", - __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, - AcpiWheaMce, AcpiWheaCmc, AcpiAlib); - - /* Don't release the structure until coreboot has copied the ACPI tables. - * AmdReleaseStruct (&AmdLateParams); - */ - - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS AmdLateParams; - - LibAmdMemFill (&AmdLateParams, - 0, - sizeof (AP_EXE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - - Status = AmdLateRunApTask (&AmdLateParams); - AGESA_EVENTLOG(Status); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -AGESA_STATUS agesawrapper_amdreadeventlog(void) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass, AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1, AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3, AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc index df65487..9a4d419 100644 --- a/src/mainboard/supermicro/h8qgi/Makefile.inc +++ b/src/mainboard/supermicro/h8qgi/Makefile.inc @@ -20,16 +20,12 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c -romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c -ramstage-y += platform_oem.c AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c deleted file mode 100644 index 30bb996..0000000 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ /dev/null @@ -1,1181 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "Filecode.h" -#include "heapManager.h" -#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */ - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 nodes; - UINT32 node; - UINT32 sblink; - UINT32 i; - UINT32 TOM; - - /* get the number of coherent nodes in the system */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] - - /* Find out the Link ID of Node0 that connects to the - * Southbridge (system IO hub). e.g. family10 MCM Processor, - * sbLink is Processor0 Link2, internal Node0 Link3 - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - sblink = (PciData >> 8) & 3; //assume ganged - - /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ - for (node = 0; node < nodes; node++) { - /* clear all MMIO Mapped Base/Limit Registers */ - for (i = 0; i < 8; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* clear all IO Space Base/Limit Registers */ - for (i = 0; i < 4; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); - PciData = 0x00000B00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set TOM1-FFFFFFFF to Node0 sbLink. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); - PciData = 0x00FFFF00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - TOM = (UINT32)MsrRead(TOP_MEM); - PciData = (TOM >> 8) | 0x03; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set MMCONF space to Node0 sbLink with NP set. - * default E0000000-EFFFFFFF - * Just have all mmio set to non-posted, - * coreboot not implemente the range by range setting yet. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); - PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus - PciData = (PciData >> 8) & 0xFFFFFF00; - PciData |= 0x80; //NP - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - - /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x00FFF000; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00000033; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address and Bus Range onto - * MMIO configuration base Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); - - /* - * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | (1ULL << 46); - LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill(&AmdResetParams, - 0, - sizeof(AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - AmdResetParams.HtConfig.Depth = 0; - - //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default - //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work -#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) - status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); -#endif - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - UINT32 TscRateInMhz; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly(AmdEarlyParamsPtr); - - status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - - GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); - FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - UINT32 TscRateInMhz; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - - AmdReleaseStruct(&AmdParamStruct); - - /* Initialize heap space */ - EmptyHeap(); - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParams; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitEnv(EnvParams); - AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -VOID * agesawrapper_getlateinitptr(int pick) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - - case PICK_PSTATE: - return AcpiPstate; - - case PICK_SRAT: - return AcpiSrat; - - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } - - return NULL; -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParamsPtr; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - - printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); - - Status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(Status, AmdLateParamsPtr->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParamsPtr->DmiTable; - AcpiPstate = AmdLateParamsPtr->AcpiPState; - AcpiSrat = AmdLateParamsPtr->AcpiSrat; - AcpiSlit = AmdLateParamsPtr->AcpiSlit; - AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; - AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; - AcpiAlib = AmdLateParamsPtr->AcpiAlib; - - printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", - __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, - AcpiWheaMce, AcpiWheaCmc, AcpiAlib); - - /* Don't release the structure until coreboot has copied the ACPI tables. - * AmdReleaseStruct (&AmdLateParams); - */ - - return Status; -} - -/** - * @param[in] UINTN ApicIdOfCore, - * @param[in] AP_EXE_PARAMS *LaunchApParams - */ -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill(&AmdLateParams, - 0, - sizeof(AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM; - - printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data); - Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr); - AGESA_EVENTLOG(Status, AmdLateParams.StdHeader.HeapStatus); - ASSERT((Status == AGESA_SUCCESS) || (Status == AGESA_UNSUPPORTED)); - - return Status; -} - -/** - * - */ -static void agesa_bound_check(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case CPU_ERROR_HEAP_IS_FULL: - printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED: - printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT: - printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT: - printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n"); - break; - - default: - break; - } -} - -/** - * - */ -static void agesa_alert(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case MEM_ALERT_USER_TMG_MODE_OVERRULED: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case MEM_ALERT_ORG_MISMATCH_DIMM: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "DIMM organization miss-match\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case MEM_ALERT_BK_INT_DIS: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "Bank interleaving disable for internal issue\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case CPU_EVENT_BIST_ERROR: - printk(BIOS_DEBUG, "BIST error: %x reported on Socket %x Core %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_HW_SYNCFLOOD: - printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %x Link %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case HT_EVENT_HW_HTCRC: - printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %x Link %x Lanemask:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - default: - break; - } -} - -/** - * - */ -static void agesa_warning(EVENT_PARAMS *event) -{ -/* - if (event->EventInfo == CPU_EVENT_STACK_REENTRY) { - printk(BIOS_DEBUG, - "The stack has already been enabled and this is a - redundant invocation of AMD_ENABLE_STACK. There is no event logged and - no data values. The event sub-class is returned along with the status code\n"); - return; - } -*/ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_WARNING_UNSUPPORTED_QRDIMM: - printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n"); - break; - - case MEM_WARNING_UNSUPPORTED_UDIMM: - printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n"); - break; - - case MEM_WARNING_UNSUPPORTED_SODIMM: - printk(BIOS_DEBUG, "SO-DIMMs detected but not supported"); - break; - - case MEM_WARNING_UNSUPPORTED_X4DIMM: - printk(BIOS_DEBUG, "x4 DIMMs detected but not supported"); - break; - - case MEM_WARNING_UNSUPPORTED_RDIMM: - printk(BIOS_DEBUG, "Registered DIMMs detected but not supported"); - break; - -/* - case MEM_WARNING_UNSUPPORTED_LRDIMM: - printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported"); - break; -*/ - - case MEM_WARNING_NO_SPDTRC_FOUND: - printk(BIOS_DEBUG, "NO_SPDTRC_FOUND"); - break; - - case MEM_WARNING_EMP_NOT_SUPPORTED: - printk(BIOS_DEBUG, "Processor is not capable for EMP");// - break; - - case MEM_WARNING_EMP_CONFLICT: - printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");// - break; - - case MEM_WARNING_EMP_NOT_ENABLED: - printk(BIOS_DEBUG, "Memory size is not power of two\n");// - break; - - case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED: - printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n"); - break; - - case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED: - printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n"); - break; - -/* - case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO: - printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n"); - break; - - case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO: - printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n"); - break; -*/ - - case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: - printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); - if ((event->EventInfo & 0x000000FF) == 0x01) { - printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x02) { - printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x03) { - printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); - } - printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case CPU_WARNING_ADJUSTED_LEVELING_MODE: - printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " - "requested: %x, actual level:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case CPU_EVENT_PM_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " - "Socket: %x, Pstate:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: - printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n"); - break; - -/* - case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION: - printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n", - event->DataParam1, - event->DataParam2); - break; -*/ - - case HT_EVENT_OPT_REQUIRED_CAP_RETRY: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); - break; - - case HT_EVENT_OPT_REQUIRED_CAP_GEN3: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %x Link %x Depth %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_OPT_UNUSED_LINKS: - printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%x LinkA%x SocketB%x LinkB%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - break; - - case HT_EVENT_OPT_LINK_PAIR_EXCEED: - printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%x MasterLink%x SocketB%x AltLink%x\n", - - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} - -/** - * - */ -static void agesa_error(EVENT_PARAMS *event) -{ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_ERROR_NO_DQS_POS_RD_WINDOW: - printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n"); - break; - - case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW: - printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n"); - break; - - case MEM_ERROR_NO_DQS_POS_WR_WINDOW: - printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n"); - break; - - case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW: - printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); - break; - - case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: - printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); - break; - - case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE: - printk(BIOS_DEBUG, "Receive Enable value is too large\n"); - break; - case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW: - printk(BIOS_DEBUG, "There is no DQS receiver enable window\n"); - break; - - case MEM_ERROR_DRAM_ENABLED_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n"); - break; - - case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n"); - break; - - case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n"); - break; - - case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n"); - break; - - case MEM_ERROR_ENTER_SELF_REF_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n"); - break; - - case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n"); - break; - - case MEM_ERROR_EXIT_SELF_REF_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n"); - break; - - case MEM_ERROR_SEND_MRS_CMD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n"); - break; - - case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n"); - break; - - case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n"); - break; - - case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n"); - break; - - case MEM_ERROR_MEM_CLEARED_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n"); - break; - - case MEM_ERROR_FLUSH_WR_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n"); - break; - - case MEM_ERROR_MAX_LAT_NO_WINDOW: - printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n"); - break; - - case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL: - printk(BIOS_DEBUG, "Fail to launch training code on an AP\n"); - break; - - case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT: - printk(BIOS_DEBUG, "Fail to finish parallel training\n"); - break; - - case MEM_ERROR_NO_ADDRESS_MAPPING: - printk(BIOS_DEBUG, "No address mapping found for a dimm\n"); - break; - - case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT: - printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n"); - break; - - case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE: - printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n"); - break; - - case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR: - printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n"); - break; - - case MEM_ERROR_NO_CHIPSELECT: - printk(BIOS_DEBUG, "No chipselects found\n"); - break; - - case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM: - printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n"); - break; - - case MEM_ERROR_WL_PRE_OUT_OF_RANGE: - printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n"); - break; - - case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE: - printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n"); - break; - - case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED: - printk(BIOS_DEBUG, "Unable to load micro code patch\n"); - break; - - case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE: - printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n"); - break; - -/* - case CPU_ERROR_PM_NB_PSTATE_MISMATCH: - printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n"); - break; -*/ - - case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: - printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); - if ((event->EventInfo & 0x000000FF) == 0x04) { - printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x05) { - printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x06) { - printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x07) { - printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); - } - printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_COH_NO_TOPOLOGY: - printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %x\n", - (unsigned int)event->DataParam1); - break; - - case HT_EVENT_NCOH_BUID_EXCEED: - printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%x Link%x Depth%x" - "Current BUID: %x, Unit Count: %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4 >> 16, - (unsigned int)event->DataParam4 & 0x0000FFFF); - break; - - case HT_EVENT_NCOH_BUS_MAX_EXCEED: - printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %x Link %x Bus %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %x Link %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case HT_EVENT_NCOH_DEVICE_FAILED: - printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" - "Socket %x Link %x Depth %x DeviceID %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} -/** - * - */ -static void agesa_critical(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: - printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR3\n", - (unsigned int)event->DataParam1); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: - printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR2\n", - (unsigned int)event->DataParam1); - break; - - case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: - printk(BIOS_DEBUG, "Socket: %x, Dimm population is not supported\n", - (unsigned int)event->DataParam1); - break; - - case HT_EVENT_COH_PROCESSOR_TYPE_MIX: - printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_COH_MPCAP_MISMATCH: - printk(BIOS_DEBUG, "Socket %x Link %x MpCap %x TotalSockets %x, HT_EVENT_COH_MPCAP_MISMATCH\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} - -/** - * - */ -static void agesa_fatal(EVENT_PARAMS *event) -{ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_ERROR_MINIMUM_MODE: - printk(BIOS_DEBUG, "Running in minimum mode\n"); - break; - - case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM: - printk(BIOS_DEBUG, "DIMM modules are missmatched\n"); - break; - - case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM: - printk(BIOS_DEBUG, "No DIMMs have been foun\n"); - break; - - case MEM_ERROR_MISMATCH_DIMM_CLOCKS: - printk(BIOS_DEBUG, "DIMM clocks miss-matched\n"); - break; - - case MEM_ERROR_NO_CYC_TIME: - printk(BIOS_DEBUG, "No cycle time found\n"); - break; - case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS: - printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs: - printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV: - printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD: - printk(BIOS_DEBUG, "Heap allocation error for SPD data\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA: - printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS: - printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA: - printk(BIOS_DEBUG, "Heap allocation error for Training Data\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK: - printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n"); - break; - - case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM: - printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n"); - break; - - case MEM_ERROR_VDDIO_UNSUPPORTED: - printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n"); - break; - - case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "Socket: %x, All PStates exceeded the motherboard current limit on specified socket\n", - (unsigned int)event->DataParam1); - break; - - default: - break; - } -} - -/** - * - * Interprte the agesa event log to an user readable string - */ -static void interpret_agesa_eventlog(EVENT_PARAMS *event) -{ - switch (event->EventClass) { - case AGESA_BOUNDS_CHK: - agesa_bound_check(event); - break; - - case AGESA_ALERT: - agesa_alert(event); - break; - - case AGESA_WARNING: - agesa_warning(event); - break; - - case AGESA_ERROR: - agesa_error(event); - break; - - case AGESA_CRITICAL: - agesa_critical(event); - break; - - case AGESA_FATAL: - agesa_fatal(event); - break; - - default: - break; - } -} - -/** - * @param HeapStatus -the current HeapStatus - */ -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - printk(BIOS_DEBUG, "enter in %s\n", __func__); - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, - 0, - sizeof(EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */ - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, - (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, - (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, - (unsigned int)AmdEventParams.DataParam4); - interpret_agesa_eventlog(&AmdEventParams); - Status = AmdReadEventLog(&AmdEventParams); - } - - printk(BIOS_DEBUG, "exit %s\n", __func__); - return Status; -} diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c deleted file mode 100644 index c31bf74..0000000 --- a/src/mainboard/supermicro/h8qgi/platform_oem.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Filecode.h" - -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE - - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) -{ - //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; -} diff --git a/src/mainboard/supermicro/h8scm/Makefile.inc b/src/mainboard/supermicro/h8scm/Makefile.inc index df65487..9a4d419 100644 --- a/src/mainboard/supermicro/h8scm/Makefile.inc +++ b/src/mainboard/supermicro/h8scm/Makefile.inc @@ -20,16 +20,12 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c -romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c -ramstage-y += platform_oem.c AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c deleted file mode 100644 index d7a1c23..0000000 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ /dev/null @@ -1,1179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "Filecode.h" -#include "heapManager.h" -#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */ - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 nodes; - UINT32 node; - UINT32 sblink; - UINT32 i; - UINT32 TOM; - - /* get the number of coherent nodes in the system */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] - - /* Find out the Link ID of Node0 that connects to the - * Southbridge (system IO hub). e.g. family10 MCM Processor, - * sbLink is Processor0 Link2, internal Node0 Link3 - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - sblink = (PciData >> 8) & 3; //assume ganged - - /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ - for (node = 0; node < nodes; node++) { - /* clear all MMIO Mapped Base/Limit Registers */ - for (i = 0; i < 8; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* clear all IO Space Base/Limit Registers */ - for (i = 0; i < 4; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); - PciData = 0x00000B00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set TOM1-FFFFFFFF to Node0 sbLink. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); - PciData = 0x00FFFF00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - TOM = (UINT32)MsrRead(TOP_MEM); - PciData = (TOM >> 8) | 0x03; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set MMCONF space to Node0 sbLink with NP set. - * default E0000000-EFFFFFFF - * Just have all mmio set to non-posted, - * coreboot not implemente the range by range setting yet. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); - PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus - PciData = (PciData >> 8) & 0xFFFFFF00; - PciData |= 0x80; //NP - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - - /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x00FFF000; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00000033; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - * Set the MMIO Configuration Base Address and Bus Range onto - * MMIO configuration base Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); - - /* - * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | (1ULL << 46); - LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill(&AmdResetParams, - 0, - sizeof(AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - AmdResetParams.HtConfig.Depth = 0; - - //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default - //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work -#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) - status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); -#endif - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - UINT32 TscRateInMhz; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly(AmdEarlyParamsPtr); - - status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - - GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); - FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - UINT32 TscRateInMhz; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - /* Initialize heap space */ - EmptyHeap(); - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParams; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitEnv(EnvParams); - AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -VOID * agesawrapper_getlateinitptr(int pick) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - - case PICK_PSTATE: - return AcpiPstate; - - case PICK_SRAT: - return AcpiSrat; - - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } - - return NULL; -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParamsPtr; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - - printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); - - Status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(Status, AmdLateParamsPtr->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - DmiTable = AmdLateParamsPtr->DmiTable; - AcpiPstate = AmdLateParamsPtr->AcpiPState; - AcpiSrat = AmdLateParamsPtr->AcpiSrat; - AcpiSlit = AmdLateParamsPtr->AcpiSlit; - AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; - AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; - AcpiAlib = AmdLateParamsPtr->AcpiAlib; - - printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", - __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, - AcpiWheaMce, AcpiWheaCmc, AcpiAlib); - - /* Don't release the structure until coreboot has copied the ACPI tables. - * AmdReleaseStruct (&AmdLateParams); - */ - - return Status; -} - -/** - * @param[in] UINTN ApicIdOfCore, - * @param[in] AP_EXE_PARAMS *LaunchApParams - */ -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill(&AmdLateParams, - 0, - sizeof(AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM; - - printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data); - Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr); - AGESA_EVENTLOG(Status, AmdLateParams.StdHeader.HeapStatus); - ASSERT((Status == AGESA_SUCCESS) || (Status == AGESA_UNSUPPORTED)); - - return Status; -} - -/** - * - */ -static void agesa_bound_check(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case CPU_ERROR_HEAP_IS_FULL: - printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED: - printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT: - printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT: - printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n"); - break; - - default: - break; - } -} - -/** - * - */ -static void agesa_alert(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case MEM_ALERT_USER_TMG_MODE_OVERRULED: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case MEM_ALERT_ORG_MISMATCH_DIMM: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "DIMM organization miss-match\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case MEM_ALERT_BK_INT_DIS: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "Bank interleaving disable for internal issue\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case CPU_EVENT_BIST_ERROR: - printk(BIOS_DEBUG, "BIST error: %x reported on Socket %x Core %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_HW_SYNCFLOOD: - printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %x Link %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case HT_EVENT_HW_HTCRC: - printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %x Link %x Lanemask:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - default: - break; - } -} - -/** - * - */ -static void agesa_warning(EVENT_PARAMS *event) -{ -/* - if (event->EventInfo == CPU_EVENT_STACK_REENTRY) { - printk(BIOS_DEBUG, - "The stack has already been enabled and this is a - redundant invocation of AMD_ENABLE_STACK. There is no event logged and - no data values. The event sub-class is returned along with the status code\n"); - return; - } -*/ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_WARNING_UNSUPPORTED_QRDIMM: - printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n"); - break; - - case MEM_WARNING_UNSUPPORTED_UDIMM: - printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n"); - break; - - case MEM_WARNING_UNSUPPORTED_SODIMM: - printk(BIOS_DEBUG, "SO-DIMMs detected but not supported"); - break; - - case MEM_WARNING_UNSUPPORTED_X4DIMM: - printk(BIOS_DEBUG, "x4 DIMMs detected but not supported"); - break; - - case MEM_WARNING_UNSUPPORTED_RDIMM: - printk(BIOS_DEBUG, "Registered DIMMs detected but not supported"); - break; - -/* - case MEM_WARNING_UNSUPPORTED_LRDIMM: - printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported"); - break; -*/ - - case MEM_WARNING_NO_SPDTRC_FOUND: - printk(BIOS_DEBUG, "NO_SPDTRC_FOUND"); - break; - - case MEM_WARNING_EMP_NOT_SUPPORTED: - printk(BIOS_DEBUG, "Processor is not capable for EMP");// - break; - - case MEM_WARNING_EMP_CONFLICT: - printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");// - break; - - case MEM_WARNING_EMP_NOT_ENABLED: - printk(BIOS_DEBUG, "Memory size is not power of two\n");// - break; - - case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED: - printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n"); - break; - - case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED: - printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n"); - break; - -/* - case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO: - printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n"); - break; - - case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO: - printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n"); - break; -*/ - - case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: - printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); - if ((event->EventInfo & 0x000000FF) == 0x01) { - printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x02) { - printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x03) { - printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); - } - printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case CPU_WARNING_ADJUSTED_LEVELING_MODE: - printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " - "requested: %x, actual level:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case CPU_EVENT_PM_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " - "Socket: %x, Pstate:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: - printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n"); - break; - -/* - case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION: - printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n", - event->DataParam1, - event->DataParam2); - break; -*/ - - case HT_EVENT_OPT_REQUIRED_CAP_RETRY: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %x Link %x Depth %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_OPT_REQUIRED_CAP_GEN3: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %x Link %x Depth %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_OPT_UNUSED_LINKS: - printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%x LinkA%x SocketB%x LinkB%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - break; - - case HT_EVENT_OPT_LINK_PAIR_EXCEED: - printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%x MasterLink%x SocketB%x AltLink%x\n", - - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} - -/** - * - */ -static void agesa_error(EVENT_PARAMS *event) -{ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_ERROR_NO_DQS_POS_RD_WINDOW: - printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n"); - break; - - case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW: - printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n"); - break; - - case MEM_ERROR_NO_DQS_POS_WR_WINDOW: - printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n"); - break; - - case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW: - printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); - break; - - case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: - printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); - break; - - case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE: - printk(BIOS_DEBUG, "Receive Enable value is too large\n"); - break; - case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW: - printk(BIOS_DEBUG, "There is no DQS receiver enable window\n"); - break; - - case MEM_ERROR_DRAM_ENABLED_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n"); - break; - - case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n"); - break; - - case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n"); - break; - - case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n"); - break; - - case MEM_ERROR_ENTER_SELF_REF_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n"); - break; - - case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n"); - break; - - case MEM_ERROR_EXIT_SELF_REF_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n"); - break; - - case MEM_ERROR_SEND_MRS_CMD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n"); - break; - - case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n"); - break; - - case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n"); - break; - - case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n"); - break; - - case MEM_ERROR_MEM_CLEARED_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n"); - break; - - case MEM_ERROR_FLUSH_WR_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n"); - break; - - case MEM_ERROR_MAX_LAT_NO_WINDOW: - printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n"); - break; - - case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL: - printk(BIOS_DEBUG, "Fail to launch training code on an AP\n"); - break; - - case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT: - printk(BIOS_DEBUG, "Fail to finish parallel training\n"); - break; - - case MEM_ERROR_NO_ADDRESS_MAPPING: - printk(BIOS_DEBUG, "No address mapping found for a dimm\n"); - break; - - case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT: - printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n"); - break; - - case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE: - printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n"); - break; - - case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR: - printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n"); - break; - - case MEM_ERROR_NO_CHIPSELECT: - printk(BIOS_DEBUG, "No chipselects found\n"); - break; - - case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM: - printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n"); - break; - - case MEM_ERROR_WL_PRE_OUT_OF_RANGE: - printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n"); - break; - - case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE: - printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n"); - break; - - case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED: - printk(BIOS_DEBUG, "Unable to load micro code patch\n"); - break; - - case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE: - printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n"); - break; - -/* - case CPU_ERROR_PM_NB_PSTATE_MISMATCH: - printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n"); - break; -*/ - - case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: - printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); - if ((event->EventInfo & 0x000000FF) == 0x04) { - printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x05) { - printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x06) { - printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x07) { - printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); - } - printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_COH_NO_TOPOLOGY: - printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %x\n", - (unsigned int)event->DataParam1); - break; - - case HT_EVENT_NCOH_BUID_EXCEED: - printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%x Link%x Depth%x" - "Current BUID: %x, Unit Count: %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4 >> 16, - (unsigned int)event->DataParam4 & 0x0000FFFF); - break; - - case HT_EVENT_NCOH_BUS_MAX_EXCEED: - printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %x Link %x Bus %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %x Link %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case HT_EVENT_NCOH_DEVICE_FAILED: - printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" - "Socket %x Link %x Depth %x DeviceID %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} -/** - * - */ -static void agesa_critical(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: - printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR3\n", - (unsigned int)event->DataParam1); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: - printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR2\n", - (unsigned int)event->DataParam1); - break; - - case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: - printk(BIOS_DEBUG, "Socket: %x, Dimm population is not supported\n", - (unsigned int)event->DataParam1); - break; - - case HT_EVENT_COH_PROCESSOR_TYPE_MIX: - printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_COH_MPCAP_MISMATCH: - printk(BIOS_DEBUG, "Socket %x Link %x MpCap %x TotalSockets %x, HT_EVENT_COH_MPCAP_MISMATCH\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} - -/** - * - */ -static void agesa_fatal(EVENT_PARAMS *event) -{ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_ERROR_MINIMUM_MODE: - printk(BIOS_DEBUG, "Running in minimum mode\n"); - break; - - case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM: - printk(BIOS_DEBUG, "DIMM modules are missmatched\n"); - break; - - case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM: - printk(BIOS_DEBUG, "No DIMMs have been foun\n"); - break; - - case MEM_ERROR_MISMATCH_DIMM_CLOCKS: - printk(BIOS_DEBUG, "DIMM clocks miss-matched\n"); - break; - - case MEM_ERROR_NO_CYC_TIME: - printk(BIOS_DEBUG, "No cycle time found\n"); - break; - case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS: - printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs: - printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV: - printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD: - printk(BIOS_DEBUG, "Heap allocation error for SPD data\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA: - printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS: - printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA: - printk(BIOS_DEBUG, "Heap allocation error for Training Data\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK: - printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n"); - break; - - case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM: - printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n"); - break; - - case MEM_ERROR_VDDIO_UNSUPPORTED: - printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n"); - break; - - case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "Socket: %x, All PStates exceeded the motherboard current limit on specified socket\n", - (unsigned int)event->DataParam1); - break; - - default: - break; - } -} - -/** - * - * Interprte the agesa event log to an user readable string - */ -static void interpret_agesa_eventlog(EVENT_PARAMS *event) -{ - switch (event->EventClass) { - case AGESA_BOUNDS_CHK: - agesa_bound_check(event); - break; - - case AGESA_ALERT: - agesa_alert(event); - break; - - case AGESA_WARNING: - agesa_warning(event); - break; - - case AGESA_ERROR: - agesa_error(event); - break; - - case AGESA_CRITICAL: - agesa_critical(event); - break; - - case AGESA_FATAL: - agesa_fatal(event); - break; - - default: - break; - } -} - -/** - * @param HeapStatus -the current HeapStatus - */ -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - printk(BIOS_DEBUG, "enter in %s\n", __func__); - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, - 0, - sizeof(EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */ - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, - (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, - (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, - (unsigned int)AmdEventParams.DataParam4); - interpret_agesa_eventlog(&AmdEventParams); - Status = AmdReadEventLog(&AmdEventParams); - } - - printk(BIOS_DEBUG, "exit %s\n", __func__); - return Status; -} diff --git a/src/mainboard/supermicro/h8scm/platform_oem.c b/src/mainboard/supermicro/h8scm/platform_oem.c deleted file mode 100644 index c31bf74..0000000 --- a/src/mainboard/supermicro/h8scm/platform_oem.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Filecode.h" - -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE - - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) -{ - //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; -} diff --git a/src/mainboard/tyan/s8226/Makefile.inc b/src/mainboard/tyan/s8226/Makefile.inc index df65487..9a4d419 100644 --- a/src/mainboard/tyan/s8226/Makefile.inc +++ b/src/mainboard/tyan/s8226/Makefile.inc @@ -20,16 +20,12 @@ romstage-y += rd890_cfg.c romstage-y += sb700_cfg.c romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c -romstage-y += platform_oem.c ramstage-y += rd890_cfg.c ramstage-y += sb700_cfg.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c -ramstage-y += platform_oem.c AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c deleted file mode 100644 index 0600f89..0000000 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ /dev/null @@ -1,1179 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "Filecode.h" -#include "heapManager.h" -#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */ - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - UINT32 nodes; - UINT32 node; - UINT32 sblink; - UINT32 i; - UINT32 TOM; - - /* get the number of coherent nodes in the system */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] - - /* Find out the Link ID of Node0 that connects to the - * Southbridge (system IO hub). e.g. family10 MCM Processor, - * sbLink is Processor0 Link2, internal Node0 Link3 - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); - LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); - sblink = (PciData >> 8) & 3; //assume ganged - - /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ - for (node = 0; node < nodes; node++) { - /* clear all MMIO Mapped Base/Limit Registers */ - for (i = 0; i < 8; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* clear all IO Space Base/Limit Registers */ - for (i = 0; i < 4; i++) { - PciData = 0x00000000; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); - PciData = 0x00000B00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); - PciData = 0x00000A03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set TOM1-FFFFFFFF to Node0 sbLink. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); - PciData = 0x00FFFF00; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - TOM = (UINT32)MsrRead(TOP_MEM); - PciData = (TOM >> 8) | 0x03; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Set MMCONF space to Node0 sbLink with NP set. - * default E0000000-EFFFFFFF - * Just have all mmio set to non-posted, - * coreboot not implemente the range by range setting yet. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); - PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus - PciData = (PciData >> 8) & 0xFFFFFF00; - PciData |= 0x80; //NP - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); - PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - - /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); - PciData = 0x00FFF000; - PciData |= sblink << 4; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); - PciData = 0x00000033; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - } - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill(&AmdResetParams, - 0, - sizeof(AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = NULL; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - AmdResetParams.HtConfig.Depth = 0; - - //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default - //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work -#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) - status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); -#endif - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - UINT32 TscRateInMhz; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly(AmdEarlyParamsPtr); - - status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - - GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); - FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - UINT32 TscRateInMhz; - CPU_SPECIFIC_SERVICES *FamilySpecificServices; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - /* Initialize heap space */ - EmptyHeap(); - - GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); - FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); - printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParams; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitEnv(EnvParams); - AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); - - AmdReleaseStruct(&AmdParamStruct); - return status; -} - -VOID * agesawrapper_getlateinitptr(int pick) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - - case PICK_PSTATE: - return AcpiPstate; - - case PICK_SRAT: - return AcpiSrat; - - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - default: - return NULL; - } - - return NULL; -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - status = AmdCreateStruct(&AmdParamStruct); - if (status != AGESA_SUCCESS) { - return status; - } - status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParamsPtr; - - LibAmdMemFill(&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; - - printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); - - Status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(Status, AmdLateParamsPtr->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - DmiTable = AmdLateParamsPtr->DmiTable; - AcpiPstate = AmdLateParamsPtr->AcpiPState; - AcpiSrat = AmdLateParamsPtr->AcpiSrat; - AcpiSlit = AmdLateParamsPtr->AcpiSlit; - AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; - AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; - AcpiAlib = AmdLateParamsPtr->AcpiAlib; - - printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" - " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" - " Mce:%p\n Cmc:%p\n Alib:%p\n", - __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, - AcpiWheaMce, AcpiWheaCmc, AcpiAlib); - - /* Don't release the structure until coreboot has copied the ACPI tables. - * AmdReleaseStruct (&AmdLateParams); - */ - - return Status; -} - -/** - * @param[in] UINTN ApicIdOfCore, - * @param[in] AP_EXE_PARAMS *LaunchApParams - */ -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; - - LibAmdMemFill(&AmdLateParams, - 0, - sizeof(AMD_LATE_PARAMS), - &(AmdLateParams.StdHeader)); - - AmdLateParams.StdHeader.AltImageBasePtr = 0; - AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdLateParams.StdHeader.Func = 0; - AmdLateParams.StdHeader.ImageBasePtr = 0; - AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM; - - printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data); - Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr); - AGESA_EVENTLOG(Status, AmdLateParams.StdHeader.HeapStatus); - ASSERT((Status == AGESA_SUCCESS) || (Status == AGESA_UNSUPPORTED)); - - return Status; -} - -/** - * - */ -static void agesa_bound_check(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case CPU_ERROR_HEAP_IS_FULL: - printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED: - printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT: - printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n"); - break; - - case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT: - printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n"); - break; - - default: - break; - } -} - -/** - * - */ -static void agesa_alert(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case MEM_ALERT_USER_TMG_MODE_OVERRULED: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case MEM_ALERT_ORG_MISMATCH_DIMM: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "DIMM organization miss-match\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case MEM_ALERT_BK_INT_DIS: - printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " - "Bank interleaving disable for internal issue\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case CPU_EVENT_BIST_ERROR: - printk(BIOS_DEBUG, "BIST error: %x reported on Socket %x Core %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_HW_SYNCFLOOD: - printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %x Link %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case HT_EVENT_HW_HTCRC: - printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %x Link %x Lanemask:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - default: - break; - } -} - -/** - * - */ -static void agesa_warning(EVENT_PARAMS *event) -{ -/* - if (event->EventInfo == CPU_EVENT_STACK_REENTRY) { - printk(BIOS_DEBUG, - "The stack has already been enabled and this is a - redundant invocation of AMD_ENABLE_STACK. There is no event logged and - no data values. The event sub-class is returned along with the status code\n"); - return; - } -*/ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_WARNING_UNSUPPORTED_QRDIMM: - printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n"); - break; - - case MEM_WARNING_UNSUPPORTED_UDIMM: - printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n"); - break; - - case MEM_WARNING_UNSUPPORTED_SODIMM: - printk(BIOS_DEBUG, "SO-DIMMs detected but not supported"); - break; - - case MEM_WARNING_UNSUPPORTED_X4DIMM: - printk(BIOS_DEBUG, "x4 DIMMs detected but not supported"); - break; - - case MEM_WARNING_UNSUPPORTED_RDIMM: - printk(BIOS_DEBUG, "Registered DIMMs detected but not supported"); - break; - -/* - case MEM_WARNING_UNSUPPORTED_LRDIMM: - printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported"); - break; -*/ - - case MEM_WARNING_NO_SPDTRC_FOUND: - printk(BIOS_DEBUG, "NO_SPDTRC_FOUND"); - break; - - case MEM_WARNING_EMP_NOT_SUPPORTED: - printk(BIOS_DEBUG, "Processor is not capable for EMP");// - break; - - case MEM_WARNING_EMP_CONFLICT: - printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");// - break; - - case MEM_WARNING_EMP_NOT_ENABLED: - printk(BIOS_DEBUG, "Memory size is not power of two\n");// - break; - - case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED: - printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n"); - break; - - case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED: - printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n"); - break; - - case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED: - printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n"); - break; - -/* - case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO: - printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n"); - break; - - case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO: - printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n"); - break; -*/ - - case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: - printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); - if ((event->EventInfo & 0x000000FF) == 0x01) { - printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x02) { - printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x03) { - printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); - } - printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case CPU_WARNING_ADJUSTED_LEVELING_MODE: - printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " - "requested: %x, actual level:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case CPU_EVENT_PM_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " - "Socket: %x, Pstate:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: - printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n"); - break; - -/* - case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION: - printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n", - event->DataParam1, - event->DataParam2); - break; -*/ - - case HT_EVENT_OPT_REQUIRED_CAP_RETRY: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); - break; - - case HT_EVENT_OPT_REQUIRED_CAP_GEN3: - printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %x Link %x Depth %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_OPT_UNUSED_LINKS: - printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%x LinkA%x SocketB%x LinkB%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - break; - - case HT_EVENT_OPT_LINK_PAIR_EXCEED: - printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%x MasterLink%x SocketB%x AltLink%x\n", - - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} - -/** - * - */ -static void agesa_error(EVENT_PARAMS *event) -{ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_ERROR_NO_DQS_POS_RD_WINDOW: - printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n"); - break; - - case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW: - printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n"); - break; - - case MEM_ERROR_NO_DQS_POS_WR_WINDOW: - printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n"); - break; - - case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW: - printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); - break; - - case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: - printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); - break; - - case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE: - printk(BIOS_DEBUG, "Receive Enable value is too large\n"); - break; - case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW: - printk(BIOS_DEBUG, "There is no DQS receiver enable window\n"); - break; - - case MEM_ERROR_DRAM_ENABLED_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n"); - break; - - case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n"); - break; - - case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n"); - break; - - case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n"); - break; - - case MEM_ERROR_ENTER_SELF_REF_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n"); - break; - - case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n"); - break; - - case MEM_ERROR_EXIT_SELF_REF_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n"); - break; - - case MEM_ERROR_SEND_MRS_CMD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n"); - break; - - case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n"); - break; - - case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n"); - break; - - case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n"); - break; - - case MEM_ERROR_MEM_CLEARED_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n"); - break; - - case MEM_ERROR_FLUSH_WR_TIME_OUT: - printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n"); - break; - - case MEM_ERROR_MAX_LAT_NO_WINDOW: - printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n"); - break; - - case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL: - printk(BIOS_DEBUG, "Fail to launch training code on an AP\n"); - break; - - case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT: - printk(BIOS_DEBUG, "Fail to finish parallel training\n"); - break; - - case MEM_ERROR_NO_ADDRESS_MAPPING: - printk(BIOS_DEBUG, "No address mapping found for a dimm\n"); - break; - - case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT: - printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n"); - break; - - case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE: - printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n"); - break; - - case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR: - printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n"); - break; - - case MEM_ERROR_NO_CHIPSELECT: - printk(BIOS_DEBUG, "No chipselects found\n"); - break; - - case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM: - printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n"); - break; - - case MEM_ERROR_WL_PRE_OUT_OF_RANGE: - printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n"); - break; - - case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE: - printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n"); - break; - - case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED: - printk(BIOS_DEBUG, "Unable to load micro code patch\n"); - break; - - case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE: - printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n"); - break; - -/* - case CPU_ERROR_PM_NB_PSTATE_MISMATCH: - printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n"); - break; -*/ - - case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: - printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); - if ((event->EventInfo & 0x000000FF) == 0x04) { - printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x05) { - printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x06) { - printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n"); - } else if ((event->EventInfo & 0x000000FF) == 0x07) { - printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); - } - printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_COH_NO_TOPOLOGY: - printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %x\n", - (unsigned int)event->DataParam1); - break; - - case HT_EVENT_NCOH_BUID_EXCEED: - printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%x Link%x Depth%x" - "Current BUID: %x, Unit Count: %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4 >> 16, - (unsigned int)event->DataParam4 & 0x0000FFFF); - break; - - case HT_EVENT_NCOH_BUS_MAX_EXCEED: - printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %x Link %x Bus %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_NCOH_CFG_MAP_EXCEED: - printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %x Link %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2); - break; - - case HT_EVENT_NCOH_DEVICE_FAILED: - printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" - "Socket %x Link %x Depth %x DeviceID %x\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} -/** - * - */ -static void agesa_critical(EVENT_PARAMS *event) -{ - switch (event->EventInfo) { - case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: - printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR3\n", - (unsigned int)event->DataParam1); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: - printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR2\n", - (unsigned int)event->DataParam1); - break; - - case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: - printk(BIOS_DEBUG, "Socket: %x, Dimm population is not supported\n", - (unsigned int)event->DataParam1); - break; - - case HT_EVENT_COH_PROCESSOR_TYPE_MIX: - printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case HT_EVENT_COH_MPCAP_MISMATCH: - printk(BIOS_DEBUG, "Socket %x Link %x MpCap %x TotalSockets %x, HT_EVENT_COH_MPCAP_MISMATCH\n", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3, - (unsigned int)event->DataParam4); - default: - break; - } -} - -/** - * - */ -static void agesa_fatal(EVENT_PARAMS *event) -{ - - switch (event->EventInfo >> 24) { - case 0x04: - printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", - (unsigned int)event->DataParam1, - (unsigned int)event->DataParam2, - (unsigned int)event->DataParam3); - break; - - case 0x08: - printk(BIOS_DEBUG, "Processor: "); - break; - - case 0x10: - printk(BIOS_DEBUG, "Hyper Transport: "); - break; - - default: - break; - } - - switch (event->EventInfo) { - case MEM_ERROR_MINIMUM_MODE: - printk(BIOS_DEBUG, "Running in minimum mode\n"); - break; - - case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM: - printk(BIOS_DEBUG, "DIMM modules are missmatched\n"); - break; - - case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM: - printk(BIOS_DEBUG, "No DIMMs have been foun\n"); - break; - - case MEM_ERROR_MISMATCH_DIMM_CLOCKS: - printk(BIOS_DEBUG, "DIMM clocks miss-matched\n"); - break; - - case MEM_ERROR_NO_CYC_TIME: - printk(BIOS_DEBUG, "No cycle time found\n"); - break; - case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS: - printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs: - printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV: - printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD: - printk(BIOS_DEBUG, "Heap allocation error for SPD data\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA: - printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS: - printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA: - printk(BIOS_DEBUG, "Heap allocation error for Training Data\n"); - break; - - case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK: - printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n"); - break; - - case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM: - printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n"); - break; - - case MEM_ERROR_VDDIO_UNSUPPORTED: - printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n"); - break; - - case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: - printk(BIOS_DEBUG, "Socket: %x, All PStates exceeded the motherboard current limit on specified socket\n", - (unsigned int)event->DataParam1); - break; - - default: - break; - } -} - -/** - * - * Interprte the agesa event log to an user readable string - */ -static void interpret_agesa_eventlog(EVENT_PARAMS *event) -{ - switch (event->EventClass) { - case AGESA_BOUNDS_CHK: - agesa_bound_check(event); - break; - - case AGESA_ALERT: - agesa_alert(event); - break; - - case AGESA_WARNING: - agesa_warning(event); - break; - - case AGESA_ERROR: - agesa_error(event); - break; - - case AGESA_CRITICAL: - agesa_critical(event); - break; - - case AGESA_FATAL: - agesa_fatal(event); - break; - - default: - break; - } -} - -/** - * @param HeapStatus -the current HeapStatus - */ -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - printk(BIOS_DEBUG, "enter in %s\n", __func__); - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, - 0, - sizeof(EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */ - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, - (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, - (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, - (unsigned int)AmdEventParams.DataParam4); - interpret_agesa_eventlog(&AmdEventParams); - Status = AmdReadEventLog(&AmdEventParams); - } - - printk(BIOS_DEBUG, "exit %s\n", __func__); - return Status; -} diff --git a/src/mainboard/tyan/s8226/platform_oem.c b/src/mainboard/tyan/s8226/platform_oem.c deleted file mode 100644 index c31bf74..0000000 --- a/src/mainboard/tyan/s8226/platform_oem.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" -#include "Filecode.h" - -#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE - - -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) -{ - //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; -} diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 1681207..6eb4941 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -26,3 +26,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb romstage-y += def_callouts.c ramstage-y += def_callouts.c + +romstage-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += eventlog.c +ramstage-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += eventlog.c diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index b18f43d..b94ddf7 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -48,7 +48,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void); AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_BOARD_AMD_DINAR +#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 AGESA_STATUS agesawrapper_amdreadeventlog(void); #else AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h index 0ddeb76..71997a8 100644 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ b/src/northbridge/amd/agesa/agesawrapper_call.h @@ -59,7 +59,7 @@ static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) #define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func() -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_BOARD_AMD_DINAR +#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 /* TODO: These families do not pass valid HeapStatus. */ #define AGESA_EVENTLOG(status) \ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog() diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c new file mode 100644 index 0000000..1deb343 --- /dev/null +++ b/src/northbridge/amd/agesa/eventlog.c @@ -0,0 +1,700 @@ + +#include <console/console.h> + +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "amdlib.h" + +#if 0 + +/** + * + */ +static void agesa_bound_check(EVENT_PARAMS *event) +{ + switch (event->EventInfo) { + case CPU_ERROR_HEAP_IS_FULL: + printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n"); + break; + + case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED: + printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n"); + break; + + case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT: + printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n"); + break; + + case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT: + printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n"); + break; + + default: + break; + } +} + +/** + * + */ +static void agesa_alert(EVENT_PARAMS *event) +{ + switch (event->EventInfo) { + case MEM_ALERT_USER_TMG_MODE_OVERRULED: + printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " + "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case MEM_ALERT_ORG_MISMATCH_DIMM: + printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " + "DIMM organization miss-match\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case MEM_ALERT_BK_INT_DIS: + printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " + "Bank interleaving disable for internal issue\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case CPU_EVENT_BIST_ERROR: + printk(BIOS_DEBUG, "BIST error: %x reported on Socket %x Core %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case HT_EVENT_HW_SYNCFLOOD: + printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %x Link %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2); + break; + + case HT_EVENT_HW_HTCRC: + printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %x Link %x Lanemask:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + default: + break; + } +} + +/** + * + */ +static void agesa_warning(EVENT_PARAMS *event) +{ +/* + if (event->EventInfo == CPU_EVENT_STACK_REENTRY) { + printk(BIOS_DEBUG, + "The stack has already been enabled and this is a + redundant invocation of AMD_ENABLE_STACK. There is no event logged and + no data values. The event sub-class is returned along with the status code\n"); + return; + } +*/ + + switch (event->EventInfo >> 24) { + case 0x04: + printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case 0x08: + printk(BIOS_DEBUG, "Processor: "); + break; + + case 0x10: + printk(BIOS_DEBUG, "Hyper Transport: "); + break; + + default: + break; + } + + switch (event->EventInfo) { + case MEM_WARNING_UNSUPPORTED_QRDIMM: + printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n"); + break; + + case MEM_WARNING_UNSUPPORTED_UDIMM: + printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n"); + break; + + case MEM_WARNING_UNSUPPORTED_SODIMM: + printk(BIOS_DEBUG, "SO-DIMMs detected but not supported"); + break; + + case MEM_WARNING_UNSUPPORTED_X4DIMM: + printk(BIOS_DEBUG, "x4 DIMMs detected but not supported"); + break; + + case MEM_WARNING_UNSUPPORTED_RDIMM: + printk(BIOS_DEBUG, "Registered DIMMs detected but not supported"); + break; + +/* + case MEM_WARNING_UNSUPPORTED_LRDIMM: + printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported"); + break; +*/ + + case MEM_WARNING_NO_SPDTRC_FOUND: + printk(BIOS_DEBUG, "NO_SPDTRC_FOUND"); + break; + + case MEM_WARNING_EMP_NOT_SUPPORTED: + printk(BIOS_DEBUG, "Processor is not capable for EMP");// + break; + + case MEM_WARNING_EMP_CONFLICT: + printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");// + break; + + case MEM_WARNING_EMP_NOT_ENABLED: + printk(BIOS_DEBUG, "Memory size is not power of two\n");// + break; + + case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED: + printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n"); + break; + + case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED: + printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n"); + break; + + case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED: + printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n"); + break; + + case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED: + printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n"); + break; + + case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED: + printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n"); + break; + +/* + case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO: + printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n"); + break; + + case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO: + printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n"); + break; +*/ + + case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: + printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); + if ((event->EventInfo & 0x000000FF) == 0x01) { + printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x02) { + printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x03) { + printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); + } + printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case CPU_WARNING_ADJUSTED_LEVELING_MODE: + printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " + "requested: %x, actual level:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2); + break; + + case CPU_EVENT_PM_PSTATE_OVERCURRENT: + printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " + "Socket: %x, Pstate:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2); + break; + + case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: + printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n"); + break; + +/* + case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION: + printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n", + event->DataParam1, + event->DataParam2); + break; +*/ + + case HT_EVENT_OPT_REQUIRED_CAP_RETRY: + printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case HT_EVENT_OPT_REQUIRED_CAP_GEN3: + printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %x Link %x Depth %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case HT_EVENT_OPT_UNUSED_LINKS: + printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%x LinkA%x SocketB%x LinkB%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4); + break; + + case HT_EVENT_OPT_LINK_PAIR_EXCEED: + printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%x MasterLink%x SocketB%x AltLink%x\n", + + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4); + default: + break; + } +} + +/** + * + */ +static void agesa_error(EVENT_PARAMS *event) +{ + + switch (event->EventInfo >> 24) { + case 0x04: + printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case 0x08: + printk(BIOS_DEBUG, "Processor: "); + break; + + case 0x10: + printk(BIOS_DEBUG, "Hyper Transport: "); + break; + + default: + break; + } + + switch (event->EventInfo) { + case MEM_ERROR_NO_DQS_POS_RD_WINDOW: + printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n"); + break; + + case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW: + printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n"); + break; + + case MEM_ERROR_NO_DQS_POS_WR_WINDOW: + printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n"); + break; + + case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW: + printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); + break; + + case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: + printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); + break; + + case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE: + printk(BIOS_DEBUG, "Receive Enable value is too large\n"); + break; + case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW: + printk(BIOS_DEBUG, "There is no DQS receiver enable window\n"); + break; + + case MEM_ERROR_DRAM_ENABLED_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n"); + break; + + case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n"); + break; + + case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n"); + break; + + case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n"); + break; + + case MEM_ERROR_ENTER_SELF_REF_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n"); + break; + + case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n"); + break; + + case MEM_ERROR_EXIT_SELF_REF_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n"); + break; + + case MEM_ERROR_SEND_MRS_CMD_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n"); + break; + + case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n"); + break; + + case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n"); + break; + + case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n"); + break; + + case MEM_ERROR_MEM_CLEARED_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n"); + break; + + case MEM_ERROR_FLUSH_WR_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n"); + break; + + case MEM_ERROR_MAX_LAT_NO_WINDOW: + printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n"); + break; + + case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL: + printk(BIOS_DEBUG, "Fail to launch training code on an AP\n"); + break; + + case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT: + printk(BIOS_DEBUG, "Fail to finish parallel training\n"); + break; + + case MEM_ERROR_NO_ADDRESS_MAPPING: + printk(BIOS_DEBUG, "No address mapping found for a dimm\n"); + break; + + case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT: + printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n"); + break; + + case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE: + printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n"); + break; + + case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR: + printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n"); + break; + + case MEM_ERROR_NO_CHIPSELECT: + printk(BIOS_DEBUG, "No chipselects found\n"); + break; + + case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM: + printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n"); + break; + + case MEM_ERROR_WL_PRE_OUT_OF_RANGE: + printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n"); + break; + + case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE: + printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n"); + break; + + case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED: + printk(BIOS_DEBUG, "Unable to load micro code patch\n"); + break; + + case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE: + printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n"); + break; + +/* + case CPU_ERROR_PM_NB_PSTATE_MISMATCH: + printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n"); + break; +*/ + + case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: + printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); + if ((event->EventInfo & 0x000000FF) == 0x04) { + printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x05) { + printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x06) { + printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x07) { + printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); + } + printk(BIOS_DEBUG, "cache region index:%x, start:%x size:%x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case HT_EVENT_COH_NO_TOPOLOGY: + printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %x\n", + (unsigned int)event->DataParam1); + break; + + case HT_EVENT_NCOH_BUID_EXCEED: + printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%x Link%x Depth%x" + "Current BUID: %x, Unit Count: %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4 >> 16, + (unsigned int)event->DataParam4 & 0x0000FFFF); + break; + + case HT_EVENT_NCOH_BUS_MAX_EXCEED: + printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %x Link %x Bus %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case HT_EVENT_NCOH_CFG_MAP_EXCEED: + printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %x Link %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2); + break; + + case HT_EVENT_NCOH_DEVICE_FAILED: + printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" + "Socket %x Link %x Depth %x DeviceID %x\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4); + default: + break; + } +} +/** + * + */ +static void agesa_critical(EVENT_PARAMS *event) +{ + switch (event->EventInfo) { + case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: + printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR3\n", + (unsigned int)event->DataParam1); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: + printk(BIOS_DEBUG, "Socket: %x, Heap allocation error for DMI table for DDR2\n", + (unsigned int)event->DataParam1); + break; + + case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: + printk(BIOS_DEBUG, "Socket: %x, Dimm population is not supported\n", + (unsigned int)event->DataParam1); + break; + + case HT_EVENT_COH_PROCESSOR_TYPE_MIX: + printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case HT_EVENT_COH_MPCAP_MISMATCH: + printk(BIOS_DEBUG, "Socket %x Link %x MpCap %x TotalSockets %x, HT_EVENT_COH_MPCAP_MISMATCH\n", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3, + (unsigned int)event->DataParam4); + default: + break; + } +} + +/** + * + */ +static void agesa_fatal(EVENT_PARAMS *event) +{ + + switch (event->EventInfo >> 24) { + case 0x04: + printk(BIOS_DEBUG, "Memory: Socket %x Dct %x Channel%x ", + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); + break; + + case 0x08: + printk(BIOS_DEBUG, "Processor: "); + break; + + case 0x10: + printk(BIOS_DEBUG, "Hyper Transport: "); + break; + + default: + break; + } + + switch (event->EventInfo) { + case MEM_ERROR_MINIMUM_MODE: + printk(BIOS_DEBUG, "Running in minimum mode\n"); + break; + + case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM: + printk(BIOS_DEBUG, "DIMM modules are missmatched\n"); + break; + + case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM: + printk(BIOS_DEBUG, "No DIMMs have been foun\n"); + break; + + case MEM_ERROR_MISMATCH_DIMM_CLOCKS: + printk(BIOS_DEBUG, "DIMM clocks miss-matched\n"); + break; + + case MEM_ERROR_NO_CYC_TIME: + printk(BIOS_DEBUG, "No cycle time found\n"); + break; + case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS: + printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs: + printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV: + printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD: + printk(BIOS_DEBUG, "Heap allocation error for SPD data\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA: + printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS: + printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA: + printk(BIOS_DEBUG, "Heap allocation error for Training Data\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK: + printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n"); + break; + + case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM: + printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n"); + break; + + case MEM_ERROR_VDDIO_UNSUPPORTED: + printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n"); + break; + + case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: + printk(BIOS_DEBUG, "Socket: %x, All PStates exceeded the motherboard current limit on specified socket\n", + (unsigned int)event->DataParam1); + break; + + default: + break; + } +} + +/** + * + * Interprte the agesa event log to an user readable string + */ +static void interpret_agesa_eventlog(EVENT_PARAMS *event) +{ + switch (event->EventClass) { + case AGESA_BOUNDS_CHK: + agesa_bound_check(event); + break; + + case AGESA_ALERT: + agesa_alert(event); + break; + + case AGESA_WARNING: + agesa_warning(event); + break; + + case AGESA_ERROR: + agesa_error(event); + break; + + case AGESA_CRITICAL: + agesa_critical(event); + break; + + case AGESA_FATAL: + agesa_fatal(event); + break; + + default: + break; + } +} +#endif + +/** + * @param HeapStatus -the current HeapStatus + */ +AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill(&AmdEventParams, + 0, + sizeof(EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog(&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", + (unsigned int)AmdEventParams.EventClass, + (unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n", + (unsigned int)AmdEventParams.DataParam1, + (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", + (unsigned int)AmdEventParams.DataParam3, + (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog(&AmdEventParams); + } + + return Status; +} diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc index 4a75499..f821940 100644 --- a/src/northbridge/amd/agesa/family15/Makefile.inc +++ b/src/northbridge/amd/agesa/family15/Makefile.inc @@ -18,5 +18,7 @@ # romstage-y += dimmSpd.c +romstage-y += agesawrapper.c ramstage-y += northbridge.c +ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c new file mode 100644 index 0000000..74f9cb9 --- /dev/null +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -0,0 +1,448 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */ + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + +/* TODO: Function body should be in mainboard directory. */ +static VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS * InitEarly) +{ +} + +static VOID OemCustomizeInitPost(AMD_POST_PARAMS *InitPost) +{ +#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR) + InitPost->MemConfig.UmaMode = UMA_AUTO; + InitPost->MemConfig.BottomIo = 0xE0; + InitPost->MemConfig.UmaSize = 0xE0-0xC0; +#endif +} + +#if !IS_ENABLED(CONFIG_BOARD_AMD_DINAR) +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 nodes; + UINT32 node; + UINT32 sblink; + UINT32 i; + UINT32 TOM; + + /* get the number of coherent nodes in the system */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] + + /* Find out the Link ID of Node0 that connects to the + * Southbridge (system IO hub). e.g. family10 MCM Processor, + * sbLink is Processor0 Link2, internal Node0 Link3 + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + sblink = (PciData >> 8) & 3; //assume ganged + + /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ + for (node = 0; node < nodes; node++) { + /* clear all MMIO Mapped Base/Limit Registers */ + for (i = 0; i < 8; i++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + /* clear all IO Space Base/Limit Registers */ + for (i = 0; i < 4; i++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i * 8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); + PciData = 0x00000B00; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); + PciData = 0x00000A03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set TOM1-FFFFFFFF to Node0 sbLink. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); + PciData = 0x00FFFF00; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + TOM = (UINT32) MsrRead(TOP_MEM); + PciData = (TOM >> 8) | 0x03; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set MMCONF space to Node0 sbLink with NP set. + * default E0000000-EFFFFFFF + * Just have all mmio set to non-posted, + * coreboot not implemente the range by range setting yet. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); + PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; //1MB each bus + PciData = (PciData >> 8) & 0xFFFFFF00; + PciData |= 0x80; //NP + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); + PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); + PciData = 0x00FFF000; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); + PciData = 0x00000033; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader; + + /* + * Set the MMIO Configuration Base Address and Bus Range onto + * MMIO configuration base Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* + * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | (1ULL << 46); + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000 - CACHE_ROM_SIZE) | 5; + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + return AGESA_SUCCESS; +} +#endif + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status = AGESA_SUCCESS; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return status; + } + AmdResetParams.HtConfig.Depth = 0; + + //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default + //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) + status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); +#endif + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + UINT32 TscRateInMhz; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return status; + } + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + + /* OEM Should Customize the defaults through this hook */ + OemCustomizeInitEarly(AmdEarlyParamsPtr); + + status = AmdInitEarly(AmdEarlyParamsPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + + GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices, + &AmdParamStruct.StdHeader); + FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); + printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); + + AmdReleaseStruct(&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + UINT32 TscRateInMhz; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return status; + } + PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + + /* OEM Should Customize the defaults through this hook */ + OemCustomizeInitPost(PostParams); + + status = AmdInitPost(PostParams); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + + AmdReleaseStruct(&AmdParamStruct); + + /* Initialize heap space */ + EmptyHeap(); + + GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices, + &AmdParamStruct.StdHeader); + FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); + printk(BIOS_DEBUG, "BSP Frequency: %uMHz\n", (unsigned int)TscRateInMhz); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return status; + } + EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitEnv(EnvParams); + AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); + + AmdReleaseStruct(&AmdParamStruct); + return status; +} + +VOID *agesawrapper_getlateinitptr(int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + + case PICK_PSTATE: + return AcpiPstate; + + case PICK_SRAT: + return AcpiSrat; + + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } + + return NULL; +} + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return status; + } + status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr); + + status = AmdInitLate(AmdLateParamsPtr); + AGESA_EVENTLOG(status, AmdLateParamsPtr->StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ + + return status; +} + +/** + * @param[in] UINTN ApicIdOfCore, + * @param[in] AP_EXE_PARAMS *LaunchApParams + */ +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ + AGESA_STATUS status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill(&AmdLateParams, 0, sizeof(AMD_LATE_PARAMS), &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM; + + printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data); + status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr); + AGESA_EVENTLOG(status, AmdLateParams.StdHeader.HeapStatus); + ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED)); + + return status; +}

1 0

Patch set updated for coreboot: d928f95 AGESA: Use common header for agesawrapper
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7153 -gerrit commit d928f95890b4338cebea20ca1e076a477767fde5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 19 09:35:18 2014 +0300 AGESA: Use common header for agesawrapper Change-Id: I5189d0c55635aeb29553fd04a67490cfee3d88d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 2 +- src/mainboard/amd/dinar/acpi_tables.c | 2 +- src/mainboard/amd/dinar/agesawrapper.c | 11 ++-- src/mainboard/amd/dinar/agesawrapper.h | 56 ------------------ src/mainboard/amd/dinar/romstage.c | 2 +- src/mainboard/amd/inagua/acpi_tables.c | 2 +- src/mainboard/amd/inagua/agesawrapper.c | 2 +- src/mainboard/amd/inagua/agesawrapper.h | 57 ------------------ src/mainboard/amd/inagua/romstage.c | 2 +- src/mainboard/amd/olivehill/acpi_tables.c | 2 +- src/mainboard/amd/olivehill/agesawrapper.c | 2 +- src/mainboard/amd/olivehill/agesawrapper.h | 61 -------------------- src/mainboard/amd/olivehill/mainboard.c | 2 +- src/mainboard/amd/olivehill/romstage.c | 2 +- src/mainboard/amd/parmer/acpi_tables.c | 2 +- src/mainboard/amd/parmer/agesawrapper.c | 2 +- src/mainboard/amd/parmer/agesawrapper.h | 61 -------------------- src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/parmer/romstage.c | 2 +- src/mainboard/amd/persimmon/acpi_tables.c | 2 +- src/mainboard/amd/persimmon/agesawrapper.c | 2 +- src/mainboard/amd/persimmon/agesawrapper.h | 59 ------------------- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/south_station/acpi_tables.c | 2 +- src/mainboard/amd/south_station/agesawrapper.c | 2 +- src/mainboard/amd/south_station/agesawrapper.h | 57 ------------------ src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/amd/thatcher/acpi_tables.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.c | 2 +- src/mainboard/amd/thatcher/agesawrapper.h | 61 -------------------- src/mainboard/amd/thatcher/mainboard.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/amd/torpedo/acpi_tables.c | 2 +- src/mainboard/amd/torpedo/agesawrapper.c | 2 +- src/mainboard/amd/torpedo/agesawrapper.h | 57 ------------------ src/mainboard/amd/torpedo/romstage.c | 2 +- src/mainboard/amd/union_station/acpi_tables.c | 2 +- src/mainboard/amd/union_station/agesawrapper.c | 2 +- src/mainboard/amd/union_station/agesawrapper.h | 57 ------------------ src/mainboard/amd/union_station/romstage.c | 2 +- src/mainboard/asrock/e350m1/acpi_tables.c | 2 +- src/mainboard/asrock/e350m1/agesawrapper.c | 2 +- src/mainboard/asrock/e350m1/agesawrapper.h | 57 ------------------ src/mainboard/asrock/e350m1/romstage.c | 2 +- src/mainboard/asrock/imb-a180/acpi_tables.c | 2 +- src/mainboard/asrock/imb-a180/agesawrapper.c | 2 +- src/mainboard/asrock/imb-a180/agesawrapper.h | 61 -------------------- src/mainboard/asrock/imb-a180/mainboard.c | 2 +- src/mainboard/asrock/imb-a180/romstage.c | 2 +- src/mainboard/asus/f2a85-m/acpi_tables.c | 2 +- src/mainboard/asus/f2a85-m/agesawrapper.c | 2 +- src/mainboard/asus/f2a85-m/agesawrapper.h | 60 ------------------- src/mainboard/asus/f2a85-m/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/f2a85-m_le/agesawrapper.h | 1 - src/mainboard/gizmosphere/gizmo/acpi_tables.c | 2 +- src/mainboard/gizmosphere/gizmo/agesawrapper.c | 2 +- src/mainboard/gizmosphere/gizmo/agesawrapper.h | 60 ------------------- src/mainboard/gizmosphere/gizmo/romstage.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h | 60 ------------------- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 8 +-- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 62 -------------------- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 2 +- src/mainboard/lenovo/g505s/acpi_tables.c | 2 +- src/mainboard/lenovo/g505s/agesawrapper.c | 2 +- src/mainboard/lenovo/g505s/agesawrapper.h | 60 ------------------- src/mainboard/lenovo/g505s/mainboard.c | 2 +- src/mainboard/lenovo/g505s/romstage.c | 2 +- src/mainboard/lippert/frontrunner-af/acpi_tables.c | 2 +- .../lippert/frontrunner-af/agesawrapper.c | 2 +- .../lippert/frontrunner-af/agesawrapper.h | 59 ------------------- src/mainboard/lippert/frontrunner-af/romstage.c | 2 +- src/mainboard/lippert/toucan-af/acpi_tables.c | 2 +- src/mainboard/lippert/toucan-af/agesawrapper.c | 2 +- src/mainboard/lippert/toucan-af/agesawrapper.h | 59 ------------------- src/mainboard/lippert/toucan-af/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/acpi_tables.c | 2 +- src/mainboard/supermicro/h8qgi/agesawrapper.c | 4 +- src/mainboard/supermicro/h8qgi/agesawrapper.h | 54 ----------------- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/acpi_tables.c | 2 +- src/mainboard/supermicro/h8scm/agesawrapper.c | 4 +- src/mainboard/supermicro/h8scm/agesawrapper.h | 53 ----------------- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/tyan/s8226/acpi_tables.c | 2 +- src/mainboard/tyan/s8226/agesawrapper.c | 4 +- src/mainboard/tyan/s8226/agesawrapper.h | 52 ----------------- src/mainboard/tyan/s8226/romstage.c | 2 +- src/northbridge/amd/agesa/agesawrapper.h | 67 ++++++++++++++++++++++ src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/agesa/family12/northbridge.c | 2 +- src/northbridge/amd/agesa/family14/northbridge.c | 2 +- src/northbridge/amd/agesa/family15/northbridge.c | 2 +- src/northbridge/amd/agesa/family15rl/northbridge.c | 2 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 2 +- 101 files changed, 153 insertions(+), 1315 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 4fa2e4e..a0a3516 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -24,7 +24,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> -#include <agesawrapper.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #if CONFIG_AMD_SB_CIMX diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index 1a72135..27635d1 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/amdfam15.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index c86e430..fd9f637 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -20,7 +20,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" @@ -48,8 +48,7 @@ VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; -extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -extern VOID OemCustomizeInitPost(IN AMD_POST_PARAMS *InitPost); +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); /*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ /* @@ -80,7 +79,7 @@ GetEndBusNum ( return Index; } -static UINT32 amdinitcpuio(void) +AGESA_STATUS agesawrapper_amdinitcpuio(void) { AGESA_STATUS Status; UINT64 MsrReg; @@ -337,7 +336,7 @@ VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; } -VOID +static VOID OemCustomizeInitPost ( IN AMD_POST_PARAMS *InitPost ) @@ -438,7 +437,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) printk(BIOS_DEBUG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__); /* Enable MMIO on AMD CPU Address Map Controller */ - amdinitcpuio (); + agesawrapper_amdinitcpuio (); LibAmdMemFill (&AmdParamStruct, 0, diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h deleted file mode 100644 index efce9c2..0000000 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - - -//void brazos_platform_stage(void); -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 5058ebe..3b13ee6 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -29,7 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/sch4037/sch4037.h> diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c index 03f0511..8974c37 100644 --- a/src/mainboard/amd/inagua/acpi_tables.c +++ b/src/mainboard/amd/inagua/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c index 75a1c2f..cee9d6c 100644 --- a/src/mainboard/amd/inagua/agesawrapper.c +++ b/src/mainboard/amd/inagua/agesawrapper.c @@ -19,7 +19,7 @@ #include <stdint.h> #include <string.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h deleted file mode 100644 index 3f7549e..0000000 --- a/src/mainboard/amd/inagua/agesawrapper.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); - -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index baebbe9..e0cf1d3 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index 6aa976a..6c3d54b 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -28,7 +28,7 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam16.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index 604278b..f58c6bb 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -20,7 +20,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/amd/olivehill/agesawrapper.h b/src/mainboard/amd/olivehill/agesawrapper.h deleted file mode 100644 index 9e4617d..0000000 --- a/src/mainboard/amd/olivehill/agesawrapper.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitcpuio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index ac40c84..cf02528 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -27,7 +27,7 @@ #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> /********************************************** * enable the dedicated function in mainboard. diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 4622fe0..0a982b6 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -30,7 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index 19001d8..a530e4f 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <console/console.h> #include <string.h> diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 6581215..2f58f38 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -20,7 +20,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/amd/parmer/agesawrapper.h b/src/mainboard/amd/parmer/agesawrapper.h deleted file mode 100644 index 9e4617d..0000000 --- a/src/mainboard/amd/parmer/agesawrapper.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitcpuio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 2ba714a..250df61 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> /************************************************* * enable the dedicated function in parmer board. diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 095b1ad..886ca57 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -30,7 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c index 4c178a5..8f1b413 100644 --- a/src/mainboard/amd/persimmon/acpi_tables.c +++ b/src/mainboard/amd/persimmon/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c index 2c82ad1..a9eda6b 100644 --- a/src/mainboard/amd/persimmon/agesawrapper.c +++ b/src/mainboard/amd/persimmon/agesawrapper.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "PlatformGnbPcieComplex.h" diff --git a/src/mainboard/amd/persimmon/agesawrapper.h b/src/mainboard/amd/persimmon/agesawrapper.h deleted file mode 100644 index d14603e..0000000 --- a/src/mainboard/amd/persimmon/agesawrapper.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); - -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5564161..fbe60fc 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c index 03f0511..8974c37 100644 --- a/src/mainboard/amd/south_station/acpi_tables.c +++ b/src/mainboard/amd/south_station/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c index 2c7549b..f743202 100644 --- a/src/mainboard/amd/south_station/agesawrapper.c +++ b/src/mainboard/amd/south_station/agesawrapper.c @@ -19,7 +19,7 @@ #include <stdint.h> #include <string.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/amd/south_station/agesawrapper.h b/src/mainboard/amd/south_station/agesawrapper.h deleted file mode 100644 index 65c14e9..0000000 --- a/src/mainboard/amd/south_station/agesawrapper.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); - -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 525e303..a64ba60 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index 19001d8..a530e4f 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <console/console.h> #include <string.h> diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index ba32692..289f078 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -20,7 +20,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/amd/thatcher/agesawrapper.h b/src/mainboard/amd/thatcher/agesawrapper.h deleted file mode 100644 index 9e4617d..0000000 --- a/src/mainboard/amd/thatcher/agesawrapper.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitcpuio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 834117e..c8aa887 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> /************************************************* * enable the dedicated function in thatcher board. diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 43095e5..0dee909 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -30,7 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/amd/torpedo/acpi_tables.c b/src/mainboard/amd/torpedo/acpi_tables.c index 5068d56..87336d7 100644 --- a/src/mainboard/amd/torpedo/acpi_tables.c +++ b/src/mainboard/amd/torpedo/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam12.h> diff --git a/src/mainboard/amd/torpedo/agesawrapper.c b/src/mainboard/amd/torpedo/agesawrapper.c index 9e1bbfd..30a919c 100644 --- a/src/mainboard/amd/torpedo/agesawrapper.c +++ b/src/mainboard/amd/torpedo/agesawrapper.c @@ -20,7 +20,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/amd/torpedo/agesawrapper.h b/src/mainboard/amd/torpedo/agesawrapper.h deleted file mode 100644 index 3a0aa0b..0000000 --- a/src/mainboard/amd/torpedo/agesawrapper.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 4c8789e..682a76e 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -28,7 +28,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c index 03f0511..8974c37 100644 --- a/src/mainboard/amd/union_station/acpi_tables.c +++ b/src/mainboard/amd/union_station/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c index 2c7549b..f743202 100644 --- a/src/mainboard/amd/union_station/agesawrapper.c +++ b/src/mainboard/amd/union_station/agesawrapper.c @@ -19,7 +19,7 @@ #include <stdint.h> #include <string.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/amd/union_station/agesawrapper.h b/src/mainboard/amd/union_station/agesawrapper.h deleted file mode 100644 index 65c14e9..0000000 --- a/src/mainboard/amd/union_station/agesawrapper.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); - -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 5988cf0..7745338 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c index d174955..6cad944 100644 --- a/src/mainboard/asrock/e350m1/acpi_tables.c +++ b/src/mainboard/asrock/e350m1/acpi_tables.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c index 68da91c..ed0b5dd 100644 --- a/src/mainboard/asrock/e350m1/agesawrapper.c +++ b/src/mainboard/asrock/e350m1/agesawrapper.c @@ -24,7 +24,7 @@ #include <stdint.h> #include <string.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/asrock/e350m1/agesawrapper.h b/src/mainboard/asrock/e350m1/agesawrapper.h deleted file mode 100644 index 9937fb2..0000000 --- a/src/mainboard/asrock/e350m1/agesawrapper.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 0cfd2e8..f297da6 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -30,7 +30,7 @@ #include <console/loglevel.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/nuvoton/common/nuvoton.h> diff --git a/src/mainboard/asrock/imb-a180/acpi_tables.c b/src/mainboard/asrock/imb-a180/acpi_tables.c index 23f7e12..bed62a3 100644 --- a/src/mainboard/asrock/imb-a180/acpi_tables.c +++ b/src/mainboard/asrock/imb-a180/acpi_tables.c @@ -28,7 +28,7 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam16.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 5b8c97f..8c24a7f 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -25,7 +25,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.h b/src/mainboard/asrock/imb-a180/agesawrapper.h deleted file mode 100644 index acaa2b3..0000000 --- a/src/mainboard/asrock/imb-a180/agesawrapper.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitcpuio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -#endif diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index ac40c84..cf02528 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -27,7 +27,7 @@ #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> /********************************************** * enable the dedicated function in mainboard. diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 93fb03b..877d458 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -30,7 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/asus/f2a85-m/acpi_tables.c b/src/mainboard/asus/f2a85-m/acpi_tables.c index 93b2c5b..c54cffa 100644 --- a/src/mainboard/asus/f2a85-m/acpi_tables.c +++ b/src/mainboard/asus/f2a85-m/acpi_tables.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index e02ca14..4f4d2f8 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -22,7 +22,7 @@ *---------------------------------------------------------------------------------------- */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "PlatformGnbPcieComplex.h" diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.h b/src/mainboard/asus/f2a85-m/agesawrapper.h deleted file mode 100644 index d4a6106..0000000 --- a/src/mainboard/asus/f2a85-m/agesawrapper.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include <vendorcode/amd/agesa/f15tn/AGESA.h> - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitcpuio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -#endif diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 191eea8..d820631 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <arch/acpi.h> diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 02777e3..385dad4 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> diff --git a/src/mainboard/asus/f2a85-m_le/agesawrapper.h b/src/mainboard/asus/f2a85-m_le/agesawrapper.h deleted file mode 100644 index a1da0e4..0000000 --- a/src/mainboard/asus/f2a85-m_le/agesawrapper.h +++ /dev/null @@ -1 +0,0 @@ -#include "../f2a85-m/agesawrapper.h" diff --git a/src/mainboard/gizmosphere/gizmo/acpi_tables.c b/src/mainboard/gizmosphere/gizmo/acpi_tables.c index 778e0de..aeaf014 100755 --- a/src/mainboard/gizmosphere/gizmo/acpi_tables.c +++ b/src/mainboard/gizmosphere/gizmo/acpi_tables.c @@ -26,7 +26,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/gizmosphere/gizmo/agesawrapper.c b/src/mainboard/gizmosphere/gizmo/agesawrapper.c index 2a40d53..129c162 100755 --- a/src/mainboard/gizmosphere/gizmo/agesawrapper.c +++ b/src/mainboard/gizmosphere/gizmo/agesawrapper.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "PlatformGnbPcieComplex.h" diff --git a/src/mainboard/gizmosphere/gizmo/agesawrapper.h b/src/mainboard/gizmosphere/gizmo/agesawrapper.h deleted file mode 100755 index b8c3f6c..0000000 --- a/src/mainboard/gizmosphere/gizmo/agesawrapper.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); - -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -#endif diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 19f0e8d..95c7041 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -32,7 +32,7 @@ #include <console/loglevel.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <cpu/x86/cache.h> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c index 5bbd0ec..a8156e3 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi_tables.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 4cbaeaa..024011b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -22,7 +22,7 @@ *---------------------------------------------------------------------------------------- */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "PlatformGnbPcieComplex.h" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h deleted file mode 100644 index 29c0ee8..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include <vendorcode/amd/agesa/f15tn/AGESA.h> - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -uint32_t agesawrapper_amdinitcpuio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -#endif diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index f858455..d3941ef 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "ec.h" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 01f463a..5ae2c68 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index d174955..6cad944 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index 31c8e72..f82388d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "PlatformGnbPcieComplex.h" @@ -517,11 +517,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void) } #endif /* #ifndef __PRE_RAM__ */ -AGESA_STATUS agesawrapper_amdlaterunaptask ( - uint32_t Func, - uint32_t Data, - void *ConfigPtr - ) +AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS status; AP_EXE_PARAMS ApExeParams; diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h deleted file mode 100644 index 720f3be..0000000 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include <vendorcode/amd/agesa/f14/AGESA.h> - - -/** - * Define AMD Ontario APU SSID/SVID - */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /**< DMI Interface */ - PICK_PSTATE, /**< Acpi Pstate SSDT Table */ - PICK_SRAT, /**< SRAT Table */ - PICK_SLIT, /**< SLIT Table */ - PICK_WHEA_MCE, /**< WHEA MCE table */ - PICK_WHEA_CMC, /**< WHEA CMV table */ - PICK_ALIB, /**< SACPI SSDT table with ALIB implementation */ -}; - - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); - -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amdlaterunaptask(uint32_t, uint32_t, void *); -void * agesawrapper_getlateinitptr(int); - -#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 7f91714..30215ce 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> diff --git a/src/mainboard/lenovo/g505s/acpi_tables.c b/src/mainboard/lenovo/g505s/acpi_tables.c index 5bbd0ec..a8156e3 100644 --- a/src/mainboard/lenovo/g505s/acpi_tables.c +++ b/src/mainboard/lenovo/g505s/acpi_tables.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <arch/acpi.h> #include <arch/acpigen.h> diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c index 4cbaeaa..024011b 100644 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ b/src/mainboard/lenovo/g505s/agesawrapper.c @@ -22,7 +22,7 @@ *---------------------------------------------------------------------------------------- */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "PlatformGnbPcieComplex.h" diff --git a/src/mainboard/lenovo/g505s/agesawrapper.h b/src/mainboard/lenovo/g505s/agesawrapper.h deleted file mode 100644 index 29c0ee8..0000000 --- a/src/mainboard/lenovo/g505s/agesawrapper.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include <vendorcode/amd/agesa/f15tn/AGESA.h> - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ - PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -uint32_t agesawrapper_amdinitcpuio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); - -AGESA_STATUS agesawrapper_fchs3earlyrestore(void); -AGESA_STATUS agesawrapper_fchs3laterestore(void); - -#endif diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index 4bc3dfe..ebce58f 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "ec.h" diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 01f463a..5ae2c68 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> diff --git a/src/mainboard/lippert/frontrunner-af/acpi_tables.c b/src/mainboard/lippert/frontrunner-af/acpi_tables.c index 03f0511..8974c37 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi_tables.c +++ b/src/mainboard/lippert/frontrunner-af/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/lippert/frontrunner-af/agesawrapper.c b/src/mainboard/lippert/frontrunner-af/agesawrapper.c index fc0bee2..ffeb08d 100644 --- a/src/mainboard/lippert/frontrunner-af/agesawrapper.c +++ b/src/mainboard/lippert/frontrunner-af/agesawrapper.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "PlatformGnbPcieComplex.h" diff --git a/src/mainboard/lippert/frontrunner-af/agesawrapper.h b/src/mainboard/lippert/frontrunner-af/agesawrapper.h deleted file mode 100644 index a74a800..0000000 --- a/src/mainboard/lippert/frontrunner-af/agesawrapper.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); - -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -#endif diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 694b142..02f4bc7 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/lippert/toucan-af/acpi_tables.c b/src/mainboard/lippert/toucan-af/acpi_tables.c index 03f0511..8974c37 100644 --- a/src/mainboard/lippert/toucan-af/acpi_tables.c +++ b/src/mainboard/lippert/toucan-af/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/x86/msr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam14.h> diff --git a/src/mainboard/lippert/toucan-af/agesawrapper.c b/src/mainboard/lippert/toucan-af/agesawrapper.c index fc0bee2..ffeb08d 100644 --- a/src/mainboard/lippert/toucan-af/agesawrapper.c +++ b/src/mainboard/lippert/toucan-af/agesawrapper.c @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "PlatformGnbPcieComplex.h" diff --git a/src/mainboard/lippert/toucan-af/agesawrapper.h b/src/mainboard/lippert/toucan-af/agesawrapper.h deleted file mode 100644 index a74a800..0000000 --- a/src/mainboard/lippert/toucan-af/agesawrapper.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -/* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); - -AGESA_STATUS agesawrapper_amdreadeventlog(void); - -AGESA_STATUS agesawrapper_amdinitcpuio(void); -AGESA_STATUS agesawrapper_amdinitmmio(void); -AGESA_STATUS agesawrapper_amdinitresume(void); -AGESA_STATUS agesawrapper_amdS3Save(void); -AGESA_STATUS agesawrapper_amds3laterestore(void); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -void *agesawrapper_getlateinitptr (int pick); - -#endif diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 181f654..2714d7f 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c index db6b336..92948b8 100644 --- a/src/mainboard/supermicro/h8qgi/acpi_tables.c +++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index c4629c6..6facc19 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -25,7 +25,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" @@ -78,7 +78,7 @@ VOID *AcpiAlib = NULL; */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -static AGESA_STATUS agesawrapper_amdinitcpuio(void) +AGESA_STATUS agesawrapper_amdinitcpuio(void) { AGESA_STATUS Status; UINT32 PciData; diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h deleted file mode 100644 index fec1ada..0000000 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - - - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 27eb039..d584a4c 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -27,7 +27,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> diff --git a/src/mainboard/supermicro/h8scm/acpi_tables.c b/src/mainboard/supermicro/h8scm/acpi_tables.c index db6b336..92948b8 100644 --- a/src/mainboard/supermicro/h8scm/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm/acpi_tables.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index bbf19ad..f738f42 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -25,7 +25,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" @@ -78,7 +78,7 @@ VOID *AcpiAlib = NULL; */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -static AGESA_STATUS agesawrapper_amdinitcpuio(void) +AGESA_STATUS agesawrapper_amdinitcpuio(void) { AGESA_STATUS Status; UINT32 PciData; diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.h b/src/mainboard/supermicro/h8scm/agesawrapper.h deleted file mode 100644 index e01c2ac..0000000 --- a/src/mainboard/supermicro/h8scm/agesawrapper.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 1cf16f7..c67a926 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -27,7 +27,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> diff --git a/src/mainboard/tyan/s8226/acpi_tables.c b/src/mainboard/tyan/s8226/acpi_tables.c index db6b336..92948b8 100644 --- a/src/mainboard/tyan/s8226/acpi_tables.c +++ b/src/mainboard/tyan/s8226/acpi_tables.c @@ -28,7 +28,7 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> unsigned long acpi_fill_madt(unsigned long current) { diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 597aa59..4cc8e18 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -25,7 +25,7 @@ #include <stdint.h> #include <string.h> #include <cpu/x86/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "cpuRegisters.h" #include "cpuCacheInit.h" @@ -78,7 +78,7 @@ VOID *AcpiAlib = NULL; */ extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); -static AGESA_STATUS agesawrapper_amdinitcpuio(void) +AGESA_STATUS agesawrapper_amdinitcpuio(void) { AGESA_STATUS Status; UINT32 PciData; diff --git a/src/mainboard/tyan/s8226/agesawrapper.h b/src/mainboard/tyan/s8226/agesawrapper.h deleted file mode 100644 index 66a827d..0000000 --- a/src/mainboard/tyan/s8226/agesawrapper.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ - -#include <stdint.h> -#include "Porting.h" -#include "AGESA.h" - -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS - -enum { - PICK_DMI, /* DMI Interface */ - PICK_PSTATE, /* Acpi Pstate SSDT Table */ - PICK_SRAT, /* SRAT Table */ - PICK_SLIT, /* SLIT Table */ - PICK_WHEA_MCE, /* WHEA MCE table */ - PICK_WHEA_CMC, /* WHEA CMV table */ - PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ -}; - - -AGESA_STATUS agesawrapper_amdinitreset(void); -AGESA_STATUS agesawrapper_amdinitearly(void); -AGESA_STATUS agesawrapper_amdinitenv(void); -AGESA_STATUS agesawrapper_amdinitlate(void); -AGESA_STATUS agesawrapper_amdinitpost(void); -AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus); -AGESA_STATUS agesawrapper_amdinitmmio(void); -void *agesawrapper_getlateinitptr (int pick); -AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); - -static inline AGESA_STATUS agesawrapper_amdS3Save(void) { return 0; } -#endif diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index bdc469e..e7a808e 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -27,7 +27,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h new file mode 100644 index 0000000..72c9673 --- /dev/null +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include <stdint.h> +#include "Porting.h" +#include "AGESA.h" + +/* Define AMD Ontario APPU SSID/SVID */ +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ + PICK_IVRS, /* IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table */ +}; + +AGESA_STATUS agesawrapper_amdinitreset(void); +AGESA_STATUS agesawrapper_amdinitearly(void); +AGESA_STATUS agesawrapper_amdinitenv(void); +AGESA_STATUS agesawrapper_amdinitlate(void); +AGESA_STATUS agesawrapper_amdinitpost(void); +AGESA_STATUS agesawrapper_amdinitmid(void); + +#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_BOARD_AMD_DINAR +AGESA_STATUS agesawrapper_amdreadeventlog(void); +#else +AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); +#endif + +AGESA_STATUS agesawrapper_amdinitcpuio(void); +AGESA_STATUS agesawrapper_amdinitmmio(void); +AGESA_STATUS agesawrapper_amdinitresume(void); +AGESA_STATUS agesawrapper_amdS3Save(void); +AGESA_STATUS agesawrapper_amds3laterestore(void); +AGESA_STATUS agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +void *agesawrapper_getlateinitptr (int pick); + +AGESA_STATUS agesawrapper_fchs3earlyrestore(void); +AGESA_STATUS agesawrapper_fchs3laterestore(void); + +#endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index d569229..d0aacd4 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -24,7 +24,7 @@ #include "AGESA.h" #include "amdlib.h" #include "Ids.h" -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include "BiosCallOuts.h" #include "dimmSpd.h" diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index bc7f7ae..1e22025 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -36,7 +36,7 @@ #include <cpu/amd/mtrr.h> #include "sb_cimx.h" -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> //#define FX_DEVS NODE_NUMS diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 1f056fa..a604718 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -35,7 +35,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 4ce8e33..5a53371 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -41,7 +41,7 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #include "sb_cimx.h" diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index e9992f2..a0f299b 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -42,7 +42,7 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 9d80987..a98d1e9 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -41,7 +41,7 @@ #include <Topology.h> #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 23bfcab..72967c1 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -41,7 +41,7 @@ #include <Topology.h> #include <cpu/amd/amdfam16.h> #include <cpuRegisters.h> -#include "agesawrapper.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)

1 0

Patch set updated for coreboot: 9fbc884 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7602 -gerrit commit 9fbc8846d426c09e314274dc3577185b437a9595 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 21 17:40:37 2014 +0200 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/agesawrapper.c | 7 ------- src/mainboard/amd/olivehill/romstage.c | 3 +++ src/mainboard/amd/parmer/agesawrapper.c | 7 ------- src/mainboard/amd/parmer/romstage.c | 3 +++ src/mainboard/amd/thatcher/agesawrapper.c | 7 ------- src/mainboard/amd/thatcher/romstage.c | 14 ++++++-------- src/mainboard/asrock/imb-a180/agesawrapper.c | 7 ------- src/mainboard/asrock/imb-a180/romstage.c | 4 ++++ src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 7 ------- src/mainboard/lenovo/g505s/agesawrapper.c | 7 ------- 10 files changed, 16 insertions(+), 50 deletions(-) diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index 22522db..242aa27 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 0a982b6..3f5d3c0 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -56,7 +56,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + device_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); post_code(0x31); console_init(); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index c457fa3..b4b39d0 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 886ca57..ea627b8 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -48,7 +48,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + device_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); post_code(0x31); console_init(); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index cc3c069..7425eac 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 0dee909..573a003 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -45,20 +45,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - u8 byte; - device_t dev; AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); hudson_lpc_port80(); - //__asm__ volatile ("1: jmp 1b"); - /* TODO: */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); if (!cpu_init_detectedx && boot_cpu()) { + device_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + u8 byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); post_code(0x31); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 62fc053..1412392 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -133,8 +133,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -151,11 +149,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 877d458..c92d753 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -77,7 +77,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { + device_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + post_code(0x31); /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 5de359e..1ceffa0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c index 5de359e..1ceffa0 100644 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ b/src/mainboard/lenovo/g505s/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

1 0

Patch set updated for coreboot: 8df36da AGESA Hudson/Yangtze: Remove unused GPP configuration in devicetree
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7600 -gerrit commit 8df36da6834bb442a4ed02f93376ab7caf0e86ab Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 21 08:40:55 2014 +0200 AGESA Hudson/Yangtze: Remove unused GPP configuration in devicetree GPP config from devicetree.cb is not implemented for fam15tn/fam16kb. Also only for asus/f2a85-m the configuration value matched the actual programming. Change-Id: Ic7a9aa1360f4ba35d202f3f7dd1fc3c20a52dde0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/parmer/devicetree.cb | 1 - src/mainboard/amd/thatcher/devicetree.cb | 1 - src/mainboard/asus/f2a85-m/devicetree.cb | 1 - src/mainboard/asus/f2a85-m_le/devicetree.cb | 1 - src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb | 1 - src/mainboard/lenovo/g505s/devicetree.cb | 1 - src/southbridge/amd/agesa/hudson/chip.h | 1 - 7 files changed, 7 deletions(-) diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index b63ba12..b37691c 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 15.1 off end # PCIe 1 device pci 15.2 off end # PCIe 2 device pci 15.3 off end # PCIe 3 - register "gpp_configuration" = "4" end #chip southbridge/amd/hudson device pci 18.0 on end diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index 5fc4648..25210ba 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -83,7 +83,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 15.1 off end # PCIe 1 device pci 15.2 off end # PCIe 2 device pci 15.3 off end # PCIe 3 - register "gpp_configuration" = "4" end #chip southbridge/amd/hudson device pci 18.0 on end diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 5158f19..b08a63d 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -116,7 +116,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 15.2 off end # unused device pci 15.3 off end # unused - register "gpp_configuration" = "4" end #chip southbridge/amd/hudson device pci 18.0 on end diff --git a/src/mainboard/asus/f2a85-m_le/devicetree.cb b/src/mainboard/asus/f2a85-m_le/devicetree.cb index 84c8a0e..245fcaa 100644 --- a/src/mainboard/asus/f2a85-m_le/devicetree.cb +++ b/src/mainboard/asus/f2a85-m_le/devicetree.cb @@ -115,7 +115,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 15.1 on end # PCIe 1 onboard gigabit device pci 15.2 off end # unused device pci 15.3 off end # unused - register "gpp_configuration" = "4" end #chip southbridge/amd/hudson device pci 18.0 on end diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index 895437b..2791262 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -68,7 +68,6 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 15.1 off end # PCIe 1 device pci 15.2 off end # PCIe 2 device pci 15.3 off end # PCIe 3 - register "gpp_configuration" = "4" end #chip southbridge/amd/hudson device pci 18.0 on end diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 3a518ab..e9718ba 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -72,7 +72,6 @@ chip northbridge/amd/agesa/family15rl/root_complex device pci 15.1 off end # PCIe 1 device pci 15.2 off end # PCIe 2 device pci 15.3 off end # PCIe 3 - register "gpp_configuration" = "4" end #chip southbridge/amd/hudson device pci 18.0 on end diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h index 21b8cd2..4a832ff 100644 --- a/src/southbridge/amd/agesa/hudson/chip.h +++ b/src/southbridge/amd/agesa/hudson/chip.h @@ -22,7 +22,6 @@ struct southbridge_amd_agesa_hudson_config { - u8 gpp_configuration; u8 sd_mode; };

1 0

Patch set updated for coreboot: 456b4de AGESA fam15: Move LPC decode enable for serial port
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7601 -gerrit commit 456b4de1e2289f49d3877cc698f3dd35e438a884 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 21 17:40:37 2014 +0200 AGESA fam15: Move LPC decode enable for serial port Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19c6a9c7d71c9899fdc898c09c337d747424fcec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/tyan/s8226/agesawrapper.c | 7 ------- src/mainboard/tyan/s8226/romstage.c | 4 ++++ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 36aa35a..0600f89 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -176,8 +176,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -194,11 +192,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index e7a808e..a0e8bfd 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -47,6 +47,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); post_code(0x31); + /* For serial port. */ + device_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist);

1 0

New patch to review for coreboot: c530e86 AGESA: Trace execution with AGESA_EVENTLOG()
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7604 -gerrit commit c530e862efe547034eb1fdca99b1ddda93e386ce Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 14:19:04 2014 +0300 AGESA: Trace execution with AGESA_EVENTLOG() Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/agesawrapper_s3.c | 6 +- src/cpu/amd/agesa/amd_late_init.c | 5 +- src/mainboard/amd/dinar/romstage.c | 11 ++-- src/mainboard/amd/inagua/romstage.c | 11 ++-- src/mainboard/amd/olivehill/romstage.c | 15 +++-- src/mainboard/amd/parmer/romstage.c | 15 +++-- src/mainboard/amd/persimmon/romstage.c | 15 +++-- src/mainboard/amd/south_station/romstage.c | 11 ++-- src/mainboard/amd/thatcher/romstage.c | 16 ++--- src/mainboard/amd/torpedo/romstage.c | 11 ++-- src/mainboard/amd/union_station/romstage.c | 11 ++-- src/mainboard/asrock/e350m1/romstage.c | 11 ++-- src/mainboard/asrock/imb-a180/romstage.c | 15 +++-- src/mainboard/asus/f2a85-m/romstage.c | 15 +++-- src/mainboard/gizmosphere/gizmo/romstage.c | 15 +++-- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 15 +++-- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 15 +++-- src/mainboard/lenovo/g505s/romstage.c | 15 +++-- src/mainboard/lippert/frontrunner-af/romstage.c | 15 +++-- src/mainboard/lippert/toucan-af/romstage.c | 15 +++-- src/mainboard/supermicro/h8qgi/romstage.c | 11 ++-- src/mainboard/supermicro/h8scm/romstage.c | 11 ++-- src/mainboard/tyan/s8226/romstage.c | 11 ++-- src/northbridge/amd/agesa/agesawrapper.h | 5 +- src/northbridge/amd/agesa/agesawrapper_call.h | 73 ---------------------- src/northbridge/amd/agesa/eventlog.c | 71 +++++++++++++++++---- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/agesawrapper.c | 14 ++--- src/northbridge/amd/agesa/family12/northbridge.c | 3 +- src/northbridge/amd/agesa/family14/agesawrapper.c | 16 ++--- src/northbridge/amd/agesa/family14/northbridge.c | 3 +- src/northbridge/amd/agesa/family15/agesawrapper.c | 14 ++--- src/northbridge/amd/agesa/family15/northbridge.c | 3 +- .../amd/agesa/family15rl/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family15rl/northbridge.c | 5 +- .../amd/agesa/family15tn/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 5 +- .../amd/agesa/family16kb/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 5 +- 39 files changed, 247 insertions(+), 299 deletions(-) diff --git a/src/cpu/amd/agesa/agesawrapper_s3.c b/src/cpu/amd/agesa/agesawrapper_s3.c index b9f5051..72bcf42 100644 --- a/src/cpu/amd/agesa/agesawrapper_s3.c +++ b/src/cpu/amd/agesa/agesawrapper_s3.c @@ -59,7 +59,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG_(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -93,7 +93,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; @@ -122,7 +122,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); ASSERT(status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 26442f4..53c2759 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -21,7 +21,6 @@ #include <bootstate.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> @@ -32,7 +31,7 @@ static void agesawrapper_post_device(void *unused) if (acpi_is_wakeup_s3()) return; - AGESAWRAPPER(amdinitlate); + agesawrapper_amdinitlate(); #if CONFIG_AMD_SB_CIMX sb_Late_Post(); @@ -40,7 +39,7 @@ static void agesawrapper_post_device(void *unused) if (!acpi_s3_resume_allowed()) return; - AGESAWRAPPER(amdS3Save); + agesawrapper_amdS3Save(); } BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 3b13ee6..b1e9a61 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -30,7 +30,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> @@ -64,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x32); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); /* Halt if there was a built in self test failure */ post_code(0x33); @@ -81,10 +80,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x35); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x36); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x37); nb_Poweron_Init(); @@ -93,10 +92,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x40); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x43); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index e0cf1d3..3a5c761 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index f94f35c..71b28c0 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -51,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = inb(0xcd6); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 788a31c..a87ef7c 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -43,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -67,25 +66,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index fbe60fc..5434ed3 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> @@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index a64ba60..7dcd9b2 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 227593d..bc21e17 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -45,7 +44,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -78,25 +78,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 682a76e..f2bcccc 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -29,7 +29,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" @@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x35); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); @@ -72,13 +71,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x36); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x37); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x38); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x39); printk(BIOS_DEBUG, "sb_before_pci_init "); @@ -86,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x43); copy_and_run(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 7745338..ac583dd 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include <sb_cimx.h> @@ -69,19 +68,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index f297da6..c7c71a1 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -31,7 +31,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 150efc2..e760fa5 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -105,29 +104,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = inb(0xcd6); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 57450ee..fbc89a7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -19,7 +19,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -76,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { @@ -128,24 +127,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 95c7041..92b5292 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -33,7 +33,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <cpu/x86/cache.h> #include <sb_cimx.h> @@ -88,29 +87,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 76c08e0..d142a9d 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -18,7 +18,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -39,7 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -60,25 +59,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 30215ce..534bdc4 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -19,7 +19,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -96,29 +95,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 76c08e0..d142a9d 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -18,7 +18,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -39,7 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -60,25 +59,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 02f4bc7..c4bf978 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/smscsuperio/smscsuperio.h> #include "cpu/x86/lapic.h" @@ -79,33 +78,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ - val = AGESAWRAPPER(amdinitpost); + val = agesawrapper_amdinitpost(); if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 2714d7f..9d99894 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> @@ -80,33 +79,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ - val = AGESAWRAPPER(amdinitpost); + val = agesawrapper_amdinitpost(); if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index d584a4c..9c48601 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -46,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ @@ -66,7 +65,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -81,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. @@ -101,10 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index c67a926..2f4c828 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ @@ -65,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -80,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); nb_Ht_Init(); @@ -95,10 +94,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index a0e8bfd..8587ed1 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -44,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* For serial port. */ @@ -69,7 +68,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -84,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. @@ -104,10 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index e1eb69b..7b61b4c 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -23,7 +23,6 @@ #include <stdint.h> #include "Porting.h" #include "AGESA.h" -#include <northbridge/amd/agesa/agesawrapper_call.h> /* Define AMD Ontario APPU SSID/SVID */ #define AMD_APU_SVID 0x1022 @@ -48,7 +47,9 @@ AGESA_STATUS agesawrapper_amdinitlate(void); AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); +#define AGESA_EVENTLOG(status, stdheader) \ + agesawrapper_trace(status, stdheader, __func__) AGESA_STATUS agesawrapper_amdinitcpuio(void); AGESA_STATUS agesawrapper_amdinitmmio(void); diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h deleted file mode 100644 index 55742d4..0000000 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_CALL_H_ -#define _AGESAWRAPPER_CALL_H_ - -#include <stdint.h> -#include <console/console.h> -#include "AGESA.h" - -/* - * Possible AGESA_STATUS values: - * - * 0x0 = AGESA_SUCCESS - * 0x1 = AGESA_UNSUPPORTED - * 0x2 = AGESA_BOUNDS_CHK - * 0x3 = AGESA_ALERT - * 0x4 = AGESA_WARNING - * 0x5 = AGESA_ERROR - * 0x6 = AGESA_CRITICAL - * 0x7 = AGESA_FATAL - */ -static const char * decodeAGESA_STATUS(AGESA_STATUS sret) -{ - const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", - "AGESA_BOUNDS_CHK", "AGESA_ALERT", - "AGESA_WARNING", "AGESA_ERROR", - "AGESA_CRITICAL", "AGESA_FATAL" - }; - if (sret > 7) return "unknown"; /* Non-AGESA error code */ - return statusStrings[sret]; -} - -static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) -{ - AGESA_STATUS ret; - printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); - ret = func(); - printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n", - name, decodeAGESA_STATUS(ret)); - return (u32)ret; -} - -#define AGESAWRAPPER(func) do_agesawrapper(agesawrapper_ ## func, #func) - -#define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func() - -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 - /* TODO: These families do not pass valid HeapStatus. */ -#define AGESA_EVENTLOG(status) \ - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0) -#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x) -#else -#define AGESA_EVENTLOG(status, heapstatus) \ - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus) -#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x,y) -#endif - -#endif diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 1deb343..90640d9 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -1,9 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <console/console.h> +#include <stdint.h> +#include <string.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" +#include "AGESA.h" +#include "AMD.h" + + +/* + * Possible AGESA_STATUS values: + * + * 0x0 = AGESA_SUCCESS + * 0x1 = AGESA_UNSUPPORTED + * 0x2 = AGESA_BOUNDS_CHK + * 0x3 = AGESA_ALERT + * 0x4 = AGESA_WARNING + * 0x5 = AGESA_ERROR + * 0x6 = AGESA_CRITICAL + * 0x7 = AGESA_FATAL + */ +static const char * decodeAGESA_STATUS(AGESA_STATUS sret) +{ + const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", + "AGESA_BOUNDS_CHK", "AGESA_ALERT", + "AGESA_WARNING", "AGESA_ERROR", + "AGESA_CRITICAL", "AGESA_FATAL" + }; + if (sret > 7) return "unknown"; /* Non-AGESA error code */ + return statusStrings[sret]; +} #if 0 @@ -42,6 +86,7 @@ static void agesa_alert(EVENT_PARAMS *event) switch (event->EventInfo) { case MEM_ALERT_USER_TMG_MODE_OVERRULED: printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " + "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", (unsigned int)event->DataParam1, (unsigned int)event->DataParam2, @@ -664,25 +709,19 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event) } #endif -/** - * @param HeapStatus -the current HeapStatus - */ -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) { - AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill(&AmdEventParams, - 0, - sizeof(EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); + AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus; + + AmdReadEventLog(&AmdEventParams); while (AmdEventParams.EventClass != 0) { printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass, @@ -693,8 +732,14 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); + AmdReadEventLog(&AmdEventParams); } +} - return Status; + +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func) +{ + printk(BIOS_DEBUG, "%s() returned %s\n", func, decodeAGESA_STATUS(ret)); + if (ret != AGESA_SUCCESS) + amd_readeventlog(StdHeader); } diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 1f615e5..2c46129 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -832,7 +832,7 @@ static void amdfam10_domain_enable_resources(device_t dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index c23b283..1893471 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -249,7 +249,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -275,7 +275,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -298,7 +298,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -323,7 +323,7 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -372,7 +372,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -391,7 +391,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID) AmdLateParams.StdHeader.ImageBasePtr = 0; status = AmdInitLate(&AmdLateParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdLateParams.StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams.DmiTable; @@ -419,7 +419,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf ApExeParams.StdHeader.ImageBasePtr = 0; status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index bcebcd9..8d82925 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -37,7 +37,6 @@ #include "sb_cimx.h" #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 @@ -777,7 +776,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index e182830..8d80ef1 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -157,7 +157,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -182,7 +182,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -204,7 +204,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -229,8 +229,10 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); + status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); + /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -347,7 +349,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -375,7 +377,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID) (u32) AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; @@ -414,7 +416,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf ApExeParams.RelatedDataBlock = ConfigPtr; status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &ApExeParams.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index aec7157..8d95dc4 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -36,7 +36,6 @@ #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -775,7 +774,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c index 4641881..0552a02 100644 --- a/src/northbridge/amd/agesa/family15/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -210,7 +210,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); #endif - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -243,7 +243,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices, &AmdParamStruct.StdHeader); @@ -281,7 +281,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) OemCustomizeInitPost(PostParams); status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); @@ -317,7 +317,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) } EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParams); - AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -369,7 +369,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) return status; } status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -396,7 +396,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(status, AmdLateParamsPtr->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParamsPtr->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; @@ -438,7 +438,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data); status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr); - AGESA_EVENTLOG(status, AmdLateParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams.StdHeader); ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED)); return status; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index de7d026..0700a5d 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "sb_cimx.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -710,7 +709,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index c5924d2..9d2fa9f 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -43,7 +43,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -697,14 +696,14 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 54a5c69..ac8d72a 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -695,14 +694,14 @@ static void domain_read_resources(device_t dev) static void domain_enable_resources(device_t dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 849f40c..db12fc3 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam16.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -737,14 +736,14 @@ static void domain_read_resources(device_t dev) static void domain_enable_resources(device_t dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); }

1 0

New patch to review for coreboot: 5001414 AGESA fam16kb: Move clearing of NoSnoopEnable bit
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7603 -gerrit commit 500141491be94b3cae0fad6d2a34cd278d4cf9ee Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 25 16:03:12 2014 +0200 AGESA fam16kb: Move clearing of NoSnoopEnable bit Originally from commit 4ca72139 move this code now from cpu/ to northbridge/. Change-Id: I38517cff273dd8f78bf5eda1d48fd1cd820ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 18 ------------------ src/northbridge/amd/agesa/family16kb/northbridge.c | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index a0a3516..26442f4 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -19,10 +19,6 @@ #include <arch/acpi.h> #include <bootstate.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> @@ -38,20 +34,6 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdinitlate); -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB) - device_t dev; - u32 value; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); -#endif - #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 72967c1..def29d1 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -653,9 +653,25 @@ static const struct pci_driver family10_northbridge __pci_driver = { .device = PCI_DEVICE_ID_AMD_10H_NB_HT, }; +static void fam16_finalize(void *chip_info) +{ + device_t dev; + u32 value; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); +} + struct chip_operations northbridge_amd_agesa_family16kb_ops = { CHIP_NAME("AMD FAM16 Northbridge") .enable_dev = 0, + .final = fam16_finalize, }; static void domain_read_resources(device_t dev)

1 0

New patch to review for coreboot: 614b5e8 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7602 -gerrit commit 614b5e875d99af9c157c5e5e04d54b98c0653caf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 21 17:40:37 2014 +0200 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/agesawrapper.c | 7 ------- src/mainboard/amd/olivehill/romstage.c | 3 +++ src/mainboard/amd/parmer/agesawrapper.c | 7 ------- src/mainboard/amd/parmer/romstage.c | 3 +++ src/mainboard/amd/thatcher/agesawrapper.c | 7 ------- src/mainboard/amd/thatcher/romstage.c | 14 ++++++-------- src/mainboard/asrock/imb-a180/agesawrapper.c | 7 ------- src/mainboard/asrock/imb-a180/romstage.c | 4 ++++ src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 7 ------- src/mainboard/lenovo/g505s/agesawrapper.c | 7 ------- 10 files changed, 16 insertions(+), 50 deletions(-) diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index 22522db..242aa27 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 0a982b6..3f5d3c0 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -56,7 +56,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + device_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); post_code(0x31); console_init(); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index c457fa3..b4b39d0 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 886ca57..ea627b8 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -48,7 +48,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + device_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); post_code(0x31); console_init(); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index cc3c069..7425eac 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 0dee909..573a003 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -45,20 +45,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - u8 byte; - device_t dev; AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); hudson_lpc_port80(); - //__asm__ volatile ("1: jmp 1b"); - /* TODO: */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); if (!cpu_init_detectedx && boot_cpu()) { + device_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + u8 byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); post_code(0x31); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 62fc053..1412392 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -133,8 +133,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -151,11 +149,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 877d458..c92d753 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -77,7 +77,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { + device_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + post_code(0x31); /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 5de359e..1ceffa0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c index 5de359e..1ceffa0 100644 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ b/src/mainboard/lenovo/g505s/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

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New patch to review for coreboot: c1b74ae AGESA fam15: Move LPC decode enable for serial port
by Kyösti Mälkki 28 Nov '14

28 Nov '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7601 -gerrit commit c1b74ae3ba5d7aed01bbbb4263f29fa3ba5b23b3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 21 17:40:37 2014 +0200 AGESA fam15: Move LPC decode enable for serial port Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19c6a9c7d71c9899fdc898c09c337d747424fcec Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/tyan/s8226/agesawrapper.c | 7 ------- src/mainboard/tyan/s8226/romstage.c | 4 ++++ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 36aa35a..0600f89 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -176,8 +176,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -194,11 +192,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index e7a808e..a0e8bfd 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -47,6 +47,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); post_code(0x31); + /* For serial port. */ + device_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist);

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coreboot-gerrit November 2014