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coreboot-gerrit@coreboot.org
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New patch to review for coreboot: 9b1913d mainboard: Test watchdog.c
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7281
-gerrit commit 9b1913dd6bcf59345f8999593f82370d322b0f11 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 07:13:17 2014 +1100 mainboard: Test watchdog.c Change-Id: Ib9f04c3936b38b536ee72e0cce361a3e025ca3b7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/jarrell/watchdog.c | 8 ++++---- src/mainboard/supermicro/x6dai_g/watchdog.c | 2 +- src/mainboard/supermicro/x6dhe_g/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhe_g2/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhr_ig/watchdog.c | 6 +++--- src/mainboard/supermicro/x6dhr_ig2/watchdog.c | 6 +++--- 6 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index 7f7a039..9722c04 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -6,7 +6,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { /* FIXME move me somewhere more appropriate */ pnp_set_logical_device(dev); @@ -20,7 +20,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -48,7 +48,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -97,7 +97,7 @@ static void disable_watchdogs(void) static void ich5_watchdog_on(void) { - device_t dev; + pci_devfn_t dev; unsigned long value, base; unsigned char byte; diff --git a/src/mainboard/supermicro/x6dai_g/watchdog.c b/src/mainboard/supermicro/x6dai_g/watchdog.c index 2fd3274..bf9f9f1 100644 --- a/src/mainboard/supermicro/x6dai_g/watchdog.c +++ b/src/mainboard/supermicro/x6dai_g/watchdog.c @@ -8,7 +8,7 @@ static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhe_g/watchdog.c b/src/mainboard/supermicro/x6dhe_g/watchdog.c index 1d34f7d..3fab7f9 100644 --- a/src/mainboard/supermicro/x6dhe_g/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g/watchdog.c @@ -5,7 +5,7 @@ #define ESB6300_WDBASE 0x400 #define ESB6300_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_esb6300_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhe_g2/watchdog.c b/src/mainboard/supermicro/x6dhe_g2/watchdog.c index 1d34f7d..3fab7f9 100644 --- a/src/mainboard/supermicro/x6dhe_g2/watchdog.c +++ b/src/mainboard/supermicro/x6dhe_g2/watchdog.c @@ -5,7 +5,7 @@ #define ESB6300_WDBASE 0x400 #define ESB6300_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_esb6300_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_esb6300_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhr_ig/watchdog.c b/src/mainboard/supermicro/x6dhr_ig/watchdog.c index a451c32..259ea79 100644 --- a/src/mainboard/supermicro/x6dhr_ig/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig/watchdog.c @@ -5,7 +5,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c index a451c32..259ea79 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/watchdog.c +++ b/src/mainboard/supermicro/x6dhr_ig2/watchdog.c @@ -5,7 +5,7 @@ #define ICH5_WDBASE 0x400 #define ICH5_GPIOBASE 0x500 -static void disable_sio_watchdog(device_t dev) +static void disable_sio_watchdog(pci_devfn_t dev) { #if 0 /* FIXME move me somewhere more appropriate */ @@ -21,7 +21,7 @@ static void disable_sio_watchdog(device_t dev) static void disable_ich5_watchdog(void) { /* FIXME move me somewhere more appropriate */ - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) { @@ -50,7 +50,7 @@ static void disable_ich5_watchdog(void) static void disable_jarell_frb3(void) { #if 0 - device_t dev; + pci_devfn_t dev; unsigned long value, base; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) {
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Patch set updated for coreboot: 0af464f mainboard: Don't hide pointer behind typedef
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7139
-gerrit commit 0af464f1d310b5d3477e469a17fd604f154030d9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 21 09:54:41 2014 +1100 mainboard: Don't hide pointer behind typedef Change-Id: I4a0e4e1598e16e13b43401c7e834b292121b63ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/get_bus_conf.c | 2 +- src/mainboard/advansus/a785e-i/mainboard.c | 2 +- src/mainboard/amd/bimini_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/bimini_fam10/mainboard.c | 4 ++-- src/mainboard/amd/dbm690t/get_bus_conf.c | 2 +- src/mainboard/amd/dbm690t/mainboard.c | 4 ++-- src/mainboard/amd/dbm690t/mptable.c | 2 +- src/mainboard/amd/dinar/mainboard.c | 2 +- src/mainboard/amd/dinar/mptable.c | 2 +- src/mainboard/amd/inagua/mainboard.c | 2 +- src/mainboard/amd/inagua/mptable.c | 2 +- src/mainboard/amd/mahogany/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany/mainboard.c | 8 ++++---- src/mainboard/amd/mahogany/mptable.c | 2 +- src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany_fam10/mainboard.c | 8 ++++---- src/mainboard/amd/mahogany_fam10/mptable.c | 2 +- src/mainboard/amd/olivehill/mainboard.c | 2 +- src/mainboard/amd/olivehill/mptable.c | 2 +- src/mainboard/amd/olivehillplus/mainboard.c | 2 +- src/mainboard/amd/olivehillplus/mptable.c | 2 +- src/mainboard/amd/parmer/mainboard.c | 2 +- src/mainboard/amd/parmer/mptable.c | 2 +- src/mainboard/amd/persimmon/mainboard.c | 2 +- src/mainboard/amd/persimmon/mptable.c | 2 +- src/mainboard/amd/pistachio/get_bus_conf.c | 2 +- src/mainboard/amd/pistachio/mainboard.c | 4 ++-- src/mainboard/amd/pistachio/mptable.c | 2 +- src/mainboard/amd/rumba/mainboard.c | 2 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 4 ++-- src/mainboard/amd/serengeti_cheetah/mainboard.c | 2 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 4 ++-- .../amd/serengeti_cheetah_fam10/get_bus_conf.c | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/mptable.c | 4 ++-- src/mainboard/amd/south_station/mainboard.c | 2 +- src/mainboard/amd/south_station/mptable.c | 2 +- src/mainboard/amd/thatcher/mainboard.c | 2 +- src/mainboard/amd/thatcher/mptable.c | 2 +- src/mainboard/amd/tilapia_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/tilapia_fam10/mainboard.c | 14 +++++++------- src/mainboard/amd/tilapia_fam10/mptable.c | 2 +- src/mainboard/amd/torpedo/mainboard.c | 2 +- src/mainboard/amd/torpedo/mptable.c | 2 +- src/mainboard/amd/union_station/mainboard.c | 2 +- src/mainboard/amd/union_station/mptable.c | 2 +- src/mainboard/apple/macbook21/mainboard.c | 4 ++-- src/mainboard/arima/hdama/mptable.c | 10 +++++----- src/mainboard/asrock/939a785gmh/get_bus_conf.c | 2 +- src/mainboard/asrock/939a785gmh/mainboard.c | 4 ++-- src/mainboard/asrock/939a785gmh/mptable.c | 2 +- src/mainboard/asrock/e350m1/mainboard.c | 2 +- src/mainboard/asrock/e350m1/mptable.c | 2 +- src/mainboard/asrock/imb-a180/mainboard.c | 2 +- src/mainboard/asrock/imb-a180/mptable.c | 2 +- src/mainboard/asus/a8n_e/get_bus_conf.c | 2 +- src/mainboard/asus/a8n_e/mptable.c | 2 +- src/mainboard/asus/dsbf/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mainboard.c | 2 +- src/mainboard/asus/f2a85-m/mptable.c | 2 +- src/mainboard/asus/k8v-x/mainboard.c | 2 +- src/mainboard/asus/m2n-e/get_bus_conf.c | 2 +- src/mainboard/asus/m2n-e/mainboard.c | 2 +- src/mainboard/asus/m2n-e/mptable.c | 2 +- src/mainboard/asus/m2v/mainboard.c | 2 +- src/mainboard/asus/m4a78-em/get_bus_conf.c | 2 +- src/mainboard/asus/m4a78-em/mainboard.c | 8 ++++---- src/mainboard/asus/m4a78-em/mptable.c | 2 +- src/mainboard/asus/m4a785-m/get_bus_conf.c | 2 +- src/mainboard/asus/m4a785-m/mainboard.c | 10 +++++----- src/mainboard/asus/m4a785-m/mptable.c | 2 +- src/mainboard/asus/m5a88-v/get_bus_conf.c | 2 +- src/mainboard/asus/m5a88-v/mainboard.c | 2 +- src/mainboard/avalue/eax-785e/get_bus_conf.c | 2 +- src/mainboard/avalue/eax-785e/mainboard.c | 2 +- src/mainboard/bachmann/ot200/mainboard.c | 2 +- src/mainboard/broadcom/blast/get_bus_conf.c | 2 +- src/mainboard/broadcom/blast/mptable.c | 4 ++-- src/mainboard/dmp/vortex86ex/mainboard.c | 2 +- src/mainboard/emulation/qemu-armv7/mainboard.c | 2 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- src/mainboard/getac/p470/mainboard.c | 6 +++--- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 2 +- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 2 +- src/mainboard/gigabyte/m57sli/mainboard.c | 2 +- src/mainboard/gigabyte/m57sli/mptable.c | 2 +- src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gm/mainboard.c | 8 ++++---- src/mainboard/gigabyte/ma785gm/mptable.c | 2 +- src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gmt/mainboard.c | 12 ++++++------ src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +- src/mainboard/gigabyte/ma78gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma78gm/mainboard.c | 6 +++--- src/mainboard/gigabyte/ma78gm/mptable.c | 2 +- src/mainboard/gizmosphere/gizmo/mainboard.c | 4 ++-- src/mainboard/gizmosphere/gizmo/mptable.c | 2 +- src/mainboard/google/bolt/mainboard.c | 6 +++--- src/mainboard/google/butterfly/mainboard.c | 6 +++--- src/mainboard/google/daisy/mainboard.c | 4 ++-- src/mainboard/google/falco/mainboard.c | 6 +++--- src/mainboard/google/link/mainboard.c | 6 +++--- src/mainboard/google/nyan/mainboard.c | 4 ++-- src/mainboard/google/nyan_big/mainboard.c | 4 ++-- src/mainboard/google/panther/mainboard.c | 4 ++-- src/mainboard/google/parrot/mainboard.c | 6 +++--- src/mainboard/google/peach_pit/mainboard.c | 4 ++-- src/mainboard/google/peppy/mainboard.c | 6 +++--- src/mainboard/google/rambi/mainboard.c | 6 +++--- src/mainboard/google/samus/mainboard.c | 6 +++--- src/mainboard/google/slippy/mainboard.c | 6 +++--- src/mainboard/google/storm/mainboard.c | 4 ++-- src/mainboard/google/stout/mainboard.c | 4 ++-- src/mainboard/hp/dl145_g1/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g1/mptable.c | 2 +- src/mainboard/hp/dl145_g3/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g3/mptable.c | 8 ++++---- src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 2 +- src/mainboard/hp/dl165_g6_fam10/mptable.c | 8 ++++---- src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 2 +- src/mainboard/ibase/mb899/mainboard.c | 2 +- src/mainboard/ibm/e325/mptable.c | 4 ++-- src/mainboard/ibm/e326/mptable.c | 4 ++-- src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mainboard.c | 2 +- src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +- src/mainboard/intel/baskingridge/mainboard.c | 2 +- src/mainboard/intel/bayleybay_fsp/mainboard.c | 2 +- src/mainboard/intel/cougar_canyon2/mainboard.c | 2 +- src/mainboard/intel/eagleheights/mptable.c | 2 +- src/mainboard/intel/emeraldlake2/mainboard.c | 2 +- src/mainboard/intel/jarrell/mptable.c | 4 ++-- src/mainboard/intel/minnowmax/mainboard.c | 2 +- src/mainboard/intel/mohonpeak/mainboard.c | 2 +- src/mainboard/intel/truxton/mptable.c | 2 +- src/mainboard/intel/wtm2/mainboard.c | 2 +- src/mainboard/intel/xe7501devkit/mptable.c | 2 +- src/mainboard/iwave/iWRainbowG6/mainboard.c | 2 +- src/mainboard/iwave/iWRainbowG6/mptable.c | 2 +- src/mainboard/iwill/dk8_htx/get_bus_conf.c | 4 ++-- src/mainboard/iwill/dk8_htx/mainboard.c | 2 +- src/mainboard/iwill/dk8_htx/mptable.c | 4 ++-- src/mainboard/iwill/dk8s2/mptable.c | 4 ++-- src/mainboard/iwill/dk8x/mptable.c | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/mptable.c | 2 +- src/mainboard/jetway/pa78vm5/get_bus_conf.c | 2 +- src/mainboard/jetway/pa78vm5/mainboard.c | 8 ++++---- src/mainboard/jetway/pa78vm5/mptable.c | 2 +- src/mainboard/kontron/986lcd-m/mainboard.c | 2 +- src/mainboard/kontron/kt690/get_bus_conf.c | 2 +- src/mainboard/kontron/kt690/mainboard.c | 4 ++-- src/mainboard/kontron/kt690/mptable.c | 2 +- src/mainboard/kontron/ktqm77/mainboard.c | 6 +++--- src/mainboard/lenovo/t520/mainboard.c | 4 ++-- src/mainboard/lenovo/t530/mainboard.c | 4 ++-- src/mainboard/lenovo/t60/mainboard.c | 7 ++++--- src/mainboard/lenovo/x200/mainboard.c | 4 ++-- src/mainboard/lenovo/x201/mainboard.c | 6 +++--- src/mainboard/lenovo/x220/mainboard.c | 4 ++-- src/mainboard/lenovo/x230/mainboard.c | 4 ++-- src/mainboard/lenovo/x60/mainboard.c | 8 +++++--- src/mainboard/lippert/frontrunner-af/mainboard.c | 2 +- src/mainboard/lippert/frontrunner-af/mptable.c | 2 +- src/mainboard/lippert/toucan-af/mainboard.c | 2 +- src/mainboard/lippert/toucan-af/mptable.c | 2 +- src/mainboard/msi/ms7135/get_bus_conf.c | 2 +- src/mainboard/msi/ms7135/mptable.c | 2 +- src/mainboard/msi/ms7260/get_bus_conf.c | 2 +- src/mainboard/msi/ms7260/mainboard.c | 2 +- src/mainboard/msi/ms7260/mptable.c | 2 +- src/mainboard/msi/ms9185/get_bus_conf.c | 2 +- src/mainboard/msi/ms9185/mptable.c | 4 ++-- src/mainboard/msi/ms9282/get_bus_conf.c | 2 +- src/mainboard/msi/ms9282/mainboard.c | 2 +- src/mainboard/msi/ms9282/mptable.c | 2 +- src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 2 +- src/mainboard/msi/ms9652_fam10/mainboard.c | 2 +- src/mainboard/msi/ms9652_fam10/mptable.c | 2 +- src/mainboard/newisys/khepri/mptable.c | 4 ++-- src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 2 +- src/mainboard/nvidia/l1_2pvv/mainboard.c | 2 +- src/mainboard/nvidia/l1_2pvv/mptable.c | 8 ++++---- src/mainboard/packardbell/ms2290/mainboard.c | 2 +- src/mainboard/rca/rm4100/mainboard.c | 4 ++-- src/mainboard/roda/rk886ex/mainboard.c | 4 ++-- src/mainboard/roda/rk9/mainboard.c | 2 +- src/mainboard/samsung/lumpy/mainboard.c | 8 +++----- src/mainboard/samsung/stumpy/mainboard.c | 2 +- src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 2 +- src/mainboard/siemens/sitemp_g1p1/mainboard.c | 21 +++++++++++---------- src/mainboard/siemens/sitemp_g1p1/mptable.c | 2 +- src/mainboard/sunw/ultra40/get_bus_conf.c | 2 +- src/mainboard/sunw/ultra40/mptable.c | 2 +- src/mainboard/supermicro/h8dme/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dme/mptable.c | 2 +- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dmr/mptable.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qgi/mainboard.c | 2 +- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8scm/mainboard.c | 2 +- src/mainboard/supermicro/h8scm/mptable.c | 2 +- src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8scm_fam10/mainboard.c | 6 +++--- src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +- src/mainboard/supermicro/x6dai_g/mptable.c | 2 +- src/mainboard/supermicro/x6dhe_g/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhe_g2/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig/mptable.c | 4 ++-- src/mainboard/supermicro/x6dhr_ig2/mptable.c | 4 ++-- src/mainboard/supermicro/x7db8/mainboard.c | 2 +- src/mainboard/technexion/tim5690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim5690/mainboard.c | 4 ++-- src/mainboard/technexion/tim5690/mptable.c | 2 +- src/mainboard/technexion/tim8690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim8690/mainboard.c | 6 +++--- src/mainboard/technexion/tim8690/mptable.c | 2 +- src/mainboard/thomson/ip1000/mainboard.c | 4 ++-- src/mainboard/tyan/s2735/mptable.c | 2 +- src/mainboard/tyan/s2850/mptable.c | 4 ++-- src/mainboard/tyan/s2875/mptable.c | 4 ++-- src/mainboard/tyan/s2880/mptable.c | 6 +++--- src/mainboard/tyan/s2881/get_bus_conf.c | 2 +- src/mainboard/tyan/s2881/mptable.c | 2 +- src/mainboard/tyan/s2882/mptable.c | 6 +++--- src/mainboard/tyan/s2885/get_bus_conf.c | 2 +- src/mainboard/tyan/s2885/mptable.c | 2 +- src/mainboard/tyan/s2891/get_bus_conf.c | 2 +- src/mainboard/tyan/s2891/mainboard.c | 2 +- src/mainboard/tyan/s2891/mptable.c | 2 +- src/mainboard/tyan/s2892/get_bus_conf.c | 2 +- src/mainboard/tyan/s2892/mainboard.c | 2 +- src/mainboard/tyan/s2892/mptable.c | 2 +- src/mainboard/tyan/s2895/get_bus_conf.c | 2 +- src/mainboard/tyan/s2895/mainboard.c | 2 +- src/mainboard/tyan/s2895/mptable.c | 2 +- src/mainboard/tyan/s2912/get_bus_conf.c | 2 +- src/mainboard/tyan/s2912/mptable.c | 2 +- src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 2 +- src/mainboard/tyan/s2912_fam10/mptable.c | 2 +- src/mainboard/tyan/s4880/mptable.c | 6 +++--- src/mainboard/tyan/s4882/mptable.c | 6 +++--- src/mainboard/tyan/s8226/mainboard.c | 2 +- src/mainboard/tyan/s8226/mptable.c | 2 +- src/mainboard/via/epia-m850/mainboard.c | 2 +- src/mainboard/winent/mb6047/get_bus_conf.c | 2 +- src/mainboard/winent/mb6047/mainboard.c | 2 +- src/mainboard/winent/mb6047/mptable.c | 2 +- 254 files changed, 397 insertions(+), 395 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 80e1d3e..2c5757a 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 9b6450d..686e968 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in A785E-I board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c index f7c55143..6b31272 100644 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c @@ -64,7 +64,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 32c8862..cd4f50e 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -100,7 +100,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -123,7 +123,7 @@ static void get_ide_dma66(void) * enable the dedicated function in bimini board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/amd/dbm690t/get_bus_conf.c +++ b/src/mainboard/amd/dbm690t/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c index 43a8d91..b92426c 100644 --- a/src/mainboard/amd/dbm690t/mainboard.c +++ b/src/mainboard/amd/dbm690t/mainboard.c @@ -119,7 +119,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -180,7 +180,7 @@ static void set_thermal_config(void) * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c index 09d137a..c154fe4 100644 --- a/src/mainboard/amd/dbm690t/mptable.c +++ b/src/mainboard/amd/dbm690t/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c index 00f1a84..83171a0 100644 --- a/src/mainboard/amd/dinar/mainboard.c +++ b/src/mainboard/amd/dinar/mainboard.c @@ -68,7 +68,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in dinar board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev); } diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 4e481f5..e796ffe 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sb700; u32 apicid_rd890; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index dc23007..0c57350 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -74,7 +74,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 7686bd2..65f67cc 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -108,7 +108,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c index f05ce7f..2e5a44f 100644 --- a/src/mainboard/amd/mahogany/get_bus_conf.c +++ b/src/mainboard/amd/mahogany/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c index 0e542ff..e851e8f 100644 --- a/src/mainboard/amd/mahogany/mainboard.c +++ b/src/mainboard/amd/mahogany/mainboard.c @@ -37,7 +37,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -50,7 +50,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -97,7 +97,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c index bd31846..bebf041 100644 --- a/src/mainboard/amd/mahogany/mptable.c +++ b/src/mainboard/amd/mahogany/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index 7d4514a..8f90235 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -37,7 +37,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -50,7 +50,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -70,7 +70,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -98,7 +98,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/amd/mahogany_fam10/mptable.c +++ b/src/mainboard/amd/mahogany_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/olivehill/mainboard.c b/src/mainboard/amd/olivehill/mainboard.c index ac40c84..961a111 100644 --- a/src/mainboard/amd/olivehill/mainboard.c +++ b/src/mainboard/amd/olivehill/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index db4a3ff..d209582 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -182,7 +182,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 6073fd4..1e58d88 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 73660e4..0ca9217 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/parmer/mainboard.c b/src/mainboard/amd/parmer/mainboard.c index 2ba714a..4b192c2 100644 --- a/src/mainboard/amd/parmer/mainboard.c +++ b/src/mainboard/amd/parmer/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in parmer board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 05da01a..7999dd8 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 58ac983..34918a8 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -151,7 +151,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 1227d89..1ae44c4 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -113,7 +113,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/amd/pistachio/get_bus_conf.c +++ b/src/mainboard/amd/pistachio/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 75f92bd..db2cbcf 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -76,7 +76,7 @@ static void set_thermal_config(void) u8 byte, byte2; u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* set adt7475 */ ADT7475_write_byte(0x40, 0x04); @@ -250,7 +250,7 @@ static void set_thermal_config(void) * enable the dedicated function in pistachio board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c index 09d137a..c154fe4 100644 --- a/src/mainboard/amd/pistachio/mptable.c +++ b/src/mainboard/amd/pistachio/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c index 5725c78..2f6af29 100644 --- a/src/mainboard/amd/rumba/mainboard.c +++ b/src/mainboard/amd/rumba/mainboard.c @@ -7,7 +7,7 @@ static void init(struct device *dev) { - device_t nic = NULL; + struct device * nic = NULL; unsigned bus = 0; unsigned devfn = PCI_DEVFN(0xd, 0); int nicirq = 1; diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index f5cd846..f2d7f9e 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); @@ -76,7 +76,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c index b9c88f6..26f61f8 100644 --- a/src/mainboard/amd/serengeti_cheetah/mainboard.c +++ b/src/mainboard/amd/serengeti_cheetah/mainboard.c @@ -5,7 +5,7 @@ #include <arch/acpigen.h> #include "mainboard.h" -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index 866875d..341b367 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -114,7 +114,7 @@ static void *smp_write_config_table(void *v) for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 48d5cc3..02dfb3c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ static u32 get_hcid(u32 i) u32 id = 0; u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; u32 devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); @@ -95,7 +95,7 @@ void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 5335cb8..3b4731b 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -134,7 +134,7 @@ static void *smp_write_config_table(void *v) if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; int jj; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 43d6a78..1be0c0a 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -77,7 +77,7 @@ static void southstation_led_init(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); southstation_led_init(); diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index c2ec4a2..0446e6c 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/thatcher/mainboard.c b/src/mainboard/amd/thatcher/mainboard.c index 834117e..e7b7ecf 100644 --- a/src/mainboard/amd/thatcher/mainboard.c +++ b/src/mainboard/amd/thatcher/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in thatcher board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { msr_t msr; diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 8ddd1b6..e34b899 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -143,7 +143,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 48e4c17..efea2fa 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -102,7 +102,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -127,7 +127,7 @@ static void get_ide_dma66(void) u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -157,7 +157,7 @@ static void set_gpio40_gfx(void) { u8 byte; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -212,7 +212,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -273,7 +273,7 @@ static void set_thermal_config(void) * enable the dedicated function in tilapia board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/amd/tilapia_fam10/mptable.c +++ b/src/mainboard/amd/tilapia_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c index 9b52b89..f5f9c94 100644 --- a/src/mainboard/amd/torpedo/mainboard.c +++ b/src/mainboard/amd/torpedo/mainboard.c @@ -52,7 +52,7 @@ void set_pcie_dereset(void) /************************************************* * enable the dedicated function in torpedo board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev); } diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 477d97a..53038dd 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -186,7 +186,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 8816e8d..ca2e887 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index c2ec4a2..0446e6c 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -105,7 +105,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 99527c1..c9858d8 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -41,12 +41,12 @@ int get_cst_entries(acpi_cstate_t **entries) return 0; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; } diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index 6ee2704..c1a6cef 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -13,7 +13,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -48,7 +48,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) static unsigned max_apicid(void) { unsigned max; - device_t dev; + struct device * dev; max = 0; for(dev = all_devices; dev; dev = dev->next) { if (dev->path.type != DEVICE_PATH_APIC) @@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v) apicid_8131_1 = apicid_base + 1; apicid_8131_2 = apicid_base + 2; { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -127,7 +127,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,1)); @@ -206,7 +206,7 @@ static void *smp_write_config_table(void *v) static void reboot_if_hotswap(void) { /* Hack patch work around for hot swap enable 33mhz problem */ - device_t dev; + struct device * dev; uint32_t data; unsigned long htic; int reset; diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c index f05ce7f..2e5a44f 100644 --- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c +++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 58ad8b2..a8d2913 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -67,7 +67,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -95,7 +95,7 @@ u8 is_dev3_present(void) * enable the dedicated function in mahogany board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c index 790d1da..0d174bc 100644 --- a/src/mainboard/asrock/939a785gmh/mptable.c +++ b/src/mainboard/asrock/939a785gmh/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..1f554f2 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 14fa316..23b5261 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asrock/imb-a180/mainboard.c b/src/mainboard/asrock/imb-a180/mainboard.c index ac40c84..961a111 100644 --- a/src/mainboard/asrock/imb-a180/mainboard.c +++ b/src/mainboard/asrock/imb-a180/mainboard.c @@ -32,7 +32,7 @@ /********************************************** * enable the dedicated function in mainboard. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index d9ca7b7..38db63a 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -183,7 +183,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c index a55401b..22d0123 100644 --- a/src/mainboard/asus/a8n_e/get_bus_conf.c +++ b/src/mainboard/asus/a8n_e/get_bus_conf.c @@ -63,7 +63,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c index a954d92..b6e1059 100644 --- a/src/mainboard/asus/a8n_e/mptable.c +++ b/src/mainboard/asus/a8n_e/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/asus/dsbf/mainboard.c b/src/mainboard/asus/dsbf/mainboard.c index 1d666c9..cf0c044 100644 --- a/src/mainboard/asus/dsbf/mainboard.c +++ b/src/mainboard/asus/dsbf/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_ops.h> #include <arch/io.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/asus/f2a85-m/mainboard.c b/src/mainboard/asus/f2a85-m/mainboard.c index 191eea8..ff4eb20 100644 --- a/src/mainboard/asus/f2a85-m/mainboard.c +++ b/src/mainboard/asus/f2a85-m/mainboard.c @@ -32,7 +32,7 @@ /************************************************* * enable the dedicated function in thatcher board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { msr_t msr; diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index cc81819..e5d7603 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -149,7 +149,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c index cd45213..2898b51 100644 --- a/src/mainboard/asus/k8v-x/mainboard.c +++ b/src/mainboard/asus/k8v-x/mainboard.c @@ -27,7 +27,7 @@ u32 vt8237_ide_80pin_detect(struct device *dev) { - device_t lpc_dev; + struct device * lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c index fd7d304..c9d113d 100644 --- a/src/mainboard/asus/m2n-e/get_bus_conf.c +++ b/src/mainboard/asus/m2n-e/get_bus_conf.c @@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned int apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c index 2c18100..7bf4639 100644 --- a/src/mainboard/asus/m2n-e/mainboard.c +++ b/src/mainboard/asus/m2n-e/mainboard.c @@ -21,7 +21,7 @@ #include <device/device.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c index 333ec49..69a5260 100644 --- a/src/mainboard/asus/m2n-e/mptable.c +++ b/src/mainboard/asus/m2n-e/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) struct mp_config_table *mc; unsigned int sbdn; int i, j, bus_isa; - device_t dev; + struct device * dev; struct resource *res; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c index 21adac0..cbacc88 100644 --- a/src/mainboard/asus/m2v/mainboard.c +++ b/src/mainboard/asus/m2v/mainboard.c @@ -26,7 +26,7 @@ u32 vt8237_ide_80pin_detect(struct device *dev) { - device_t lpc_dev; + struct device * lpc_dev; u16 acpi_io_base; u32 gpio_in; u32 res; diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 1a2e9fc..b32ca0c 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -36,7 +36,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -61,7 +61,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -91,7 +91,7 @@ void set_pcie_reset() u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -118,7 +118,7 @@ u8 is_dev3_present(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/asus/m4a78-em/mptable.c +++ b/src/mainboard/asus/m4a78-em/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index b1154ab..edaecab 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -100,7 +100,7 @@ void set_pcie_reset() u8 is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -129,7 +129,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -190,7 +190,7 @@ static void set_thermal_config(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev); diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/asus/m4a785-m/mptable.c +++ b/src/mainboard/asus/m4a785-m/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index f90c6b8..4c8efff 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 8ee338e..1da327b 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in M5A88-V board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index f90c6b8..4c8efff 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 6ce3469..6ee5923 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -73,7 +73,7 @@ u8 is_dev3_present(void) * enable the dedicated function in EAX-785E board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c index d4b0b2d..ea13cef 100644 --- a/src/mainboard/bachmann/ot200/mainboard.c +++ b/src/mainboard/bachmann/ot200/mainboard.c @@ -46,7 +46,7 @@ static void init(struct device *dev) u32 chksum = 0; char block[20]; msr_t reset; - device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52); + struct device * eeprom_dev = dev_find_slot_on_smbus(1, 0x52); if (eeprom_dev == 0) { printk(BIOS_WARNING, "eeprom not found\n"); diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 5de8952..f95d70a 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -50,7 +50,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c index d7ae6b7..9d415d2 100644 --- a/src/mainboard/broadcom/blast/mptable.c +++ b/src/mainboard/broadcom/blast/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); @@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/dmp/vortex86ex/mainboard.c b/src/mainboard/dmp/vortex86ex/mainboard.c index 2761035..381658a 100644 --- a/src/mainboard/dmp/vortex86ex/mainboard.c +++ b/src/mainboard/dmp/vortex86ex/mainboard.c @@ -25,7 +25,7 @@ #include <device/pci_def.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 83a55e3..815f50e 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <device/device.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Enable qemu/armv7 device...\n"); } diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index a8a61c4..6d1f2b0 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -30,7 +30,7 @@ static const unsigned char qemu_i440fx_irqs[] = { 11, 10, 10, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(struct device * dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index e991b53..622ea54 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -33,7 +33,7 @@ static const unsigned char qemu_q35_irqs[] = { 10, 10, 11, 11, }; -static void qemu_nb_init(device_t dev) +static void qemu_nb_init(struct device * dev) { /* Map memory at 0xc0000 - 0xfffff */ int i; diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 2b33ff0..1dc881a 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -62,7 +62,7 @@ static void pcie_limit_power(void) // machine. It should set the slot numbers and enable power // limitation for the PCIe slots. - device_t dev; + struct device * dev; dev = dev_find_slot(0, PCI_DEVFN(28,0)); if (dev) pci_write_config32(dev, 0x54, 0x0010a0e0); @@ -79,14 +79,14 @@ static void pcie_limit_power(void) } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { ec_enable(); } // mainboard_enable is executed as first thing after // enumerate_buses(). Is there no mainboard_init()? -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->write_acpi_tables = mainboard_write_acpi_tables; diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index 9315cbd..c9c1950 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c index 0af6cf0..9e8c7bf 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index c798415..db5b685 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c index 291d4f7..a668696 100644 --- a/src/mainboard/gigabyte/m57sli/mainboard.c +++ b/src/mainboard/gigabyte/m57sli/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c index 1536823..43459bc 100644 --- a/src/mainboard/gigabyte/m57sli/mptable.c +++ b/src/mainboard/gigabyte/m57sli/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index cd06069..9fe9c7f 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -35,7 +35,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -60,7 +60,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -98,7 +98,7 @@ static void set_gpio40_gfx(void) u8 byte; // u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -134,7 +134,7 @@ static void set_gpio40_gfx(void) * enable the dedicated function in ma785gm board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma785gm/mptable.c +++ b/src/mainboard/gigabyte/ma785gm/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 89b50bb..f591ebb 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -45,7 +45,7 @@ void set_pcie_dereset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ byte = pm_ioread(0x8d); @@ -70,7 +70,7 @@ void set_pcie_reset() { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set 0 to bit1 :disable GPM9 as SLP_S2 output */ /* set 0 to bit2 :disable GPM8 as AZ_RST output */ @@ -98,7 +98,7 @@ void set_pcie_reset() int is_dev3_present(void) { u16 word; - device_t sm_dev; + struct device * sm_dev; /* access the smbus extended register */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -128,7 +128,7 @@ static void set_gpio40_gfx(void) u8 byte; // u16 word; u32 dword; - device_t sm_dev; + struct device * sm_dev; /* disable the GPIO40 as CLKREQ2# function */ byte = pm_ioread(0xd3); byte &= ~(1 << 7); @@ -183,7 +183,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -244,7 +244,7 @@ static void set_thermal_config(void) * enable the dedicated function in ma785gmt board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma785gmt/mptable.c +++ b/src/mainboard/gigabyte/ma785gmt/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 49df0c2..2fd5c52 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -38,7 +38,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -51,7 +51,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -71,7 +71,7 @@ u8 is_dev3_present(void) * enable the dedicated function in board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/gigabyte/ma78gm/mptable.c +++ b/src/mainboard/gigabyte/ma78gm/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index a9afdfb..ad8fa58 100755 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -55,7 +55,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -78,7 +78,7 @@ static void mainboard_enable(device_t dev) void mainboard_final( void *chip_info ); void mainboard_final( void *chip_info ) { - device_t ahci_dev; + struct device * ahci_dev; u32 ABAR; u8 *memptr; diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index b98598a..8301bd5 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/google/bolt/mainboard.c b/src/mainboard/google/bolt/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/bolt/mainboard.c +++ b/src/mainboard/google/bolt/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 655fc2f..c4006c6 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -194,7 +194,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { u32 search_address = 0x0; size_t search_length = -1; @@ -258,7 +258,7 @@ static void mainboard_init(device_t dev) } } -static int butterfly_onboard_smbios_data(device_t dev, int *handle, +static int butterfly_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -278,7 +278,7 @@ static int butterfly_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = butterfly_onboard_smbios_data; diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 0adadb6..fc9a08c 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -258,7 +258,7 @@ static void gpio_init(void) } /* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { int dp_tries; struct s5p_dp_device dp_device = { @@ -322,7 +322,7 @@ static void mainboard_init(device_t dev) // gpio_info(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; diff --git a/src/mainboard/google/falco/mainboard.c b/src/mainboard/google/falco/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/falco/mainboard.c +++ b/src/mainboard/google/falco/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c index ed40f8f..d1a3856 100644 --- a/src/mainboard/google/link/mainboard.c +++ b/src/mainboard/google/link/mainboard.c @@ -149,7 +149,7 @@ static int int15_handler(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ link_ec_init(); @@ -166,7 +166,7 @@ static void mainboard_init(device_t dev) } } -static int link_onboard_smbios_data(device_t dev, int *handle, +static int link_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -204,7 +204,7 @@ static int link_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = link_onboard_smbios_data; diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 6fa8a95..d7df116 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -232,7 +232,7 @@ static void setup_ec_spi(void) spi->rx_frame_header_enable = 1; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { set_clock_sources(); @@ -284,7 +284,7 @@ static void mainboard_init(device_t dev) setup_ec_spi(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/nyan_big/mainboard.c b/src/mainboard/google/nyan_big/mainboard.c index 4a05991..908d610 100644 --- a/src/mainboard/google/nyan_big/mainboard.c +++ b/src/mainboard/google/nyan_big/mainboard.c @@ -232,7 +232,7 @@ static void setup_ec_spi(void) spi->rx_frame_header_enable = 1; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { set_clock_sources(); @@ -281,7 +281,7 @@ static void mainboard_init(device_t dev) setup_ec_spi(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index 5058eca..a1bd459 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { lan_init(); } @@ -52,7 +52,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 547680e..207bcfd 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -48,13 +48,13 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ parrot_ec_init(); } -static int parrot_onboard_smbios_data(device_t dev, int *handle, +static int parrot_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -85,7 +85,7 @@ static int parrot_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = parrot_onboard_smbios_data; diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index 1fb441d..53db9fa 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -405,7 +405,7 @@ static void sdmmc_vdd(void) } /* this happens after cpu_init where exynos resources are set */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* we'll stick with the crummy u-boot struct for now.*/ /* doing this as an auto since the struct has to be writeable */ @@ -462,7 +462,7 @@ static void mainboard_init(device_t dev) setup_usb(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; diff --git a/src/mainboard/google/peppy/mainboard.c b/src/mainboard/google/peppy/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/peppy/mainboard.c +++ b/src/mainboard/google/peppy/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index cd3fc48..b43928d 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -127,12 +127,12 @@ static int int15_handler(void) } #endif -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -161,7 +161,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index 7977ce3..de7f434 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -42,12 +42,12 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -112,7 +112,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index 0ccf90d..7676d56 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -44,12 +44,12 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, +static int mainboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -87,7 +87,7 @@ static int mainboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 0b0182f..4792ea9 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -20,11 +20,11 @@ #include <device/device.h> #include <boot/coreboot_tables.h> -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = &mainboard_init; } diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 9bcbfe4..58d89b8 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -48,7 +48,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { struct device *ethernet_dev = NULL; @@ -70,7 +70,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index acfa023..6a36ef7 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -51,7 +51,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index b9af38b..7e81143 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1)); if (dev) { diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index ba0fc88..59b35aa 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index 6c71bad..6b3032b 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { @@ -90,7 +90,7 @@ static void *smp_write_config_table(void *v) outb(0x0e, 0x4d1); { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; @@ -106,7 +106,7 @@ static void *smp_write_config_table(void *v) // hide XIOAPIC PCI configuration space { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; @@ -151,7 +151,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index 099c41a..6561c94 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c index 86f2cc6..175cfe5 100644 --- a/src/mainboard/hp/dl165_g6_fam10/mptable.c +++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; int i; struct resource *res; for(i=0; i<3; i++) { @@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v) outb(0x0e, 0x4d1); { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; @@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v) // hide XIOAPIC PCI configuration space { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x205, 0); if (dev) { uint32_t dword; @@ -130,7 +130,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c index f858455..3384a9f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c @@ -41,7 +41,7 @@ static void pavilion_cold_boot_init(void) pavilion_m6_1035dx_ec_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index f47b9d9..d12e759 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -144,7 +144,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c index a2a10a1..ba6a09e 100644 --- a/src/mainboard/ibase/mb899/mainboard.c +++ b/src/mainboard/ibase/mb899/mainboard.c @@ -31,7 +31,7 @@ // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c index 6eb6390..50f8031 100644 --- a/src/mainboard/ibm/e325/mptable.c +++ b/src/mainboard/ibm/e325/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -60,7 +60,7 @@ static void *smp_write_config_table(void *v) /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c index f271166..d85e609 100644 --- a/src/mainboard/ibm/e326/mptable.c +++ b/src/mainboard/ibm/e326/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) /* Legacy IOAPIC #2 */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131-1 apic #3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index 43ff9c1..9d67e2b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -53,7 +53,7 @@ u8 is_dev3_present(void) * enable the dedicated function in kino board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c index 11426c2..759ab30 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mptable.c +++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index a6839fc..be142aa 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index feae6ef..d32ca91 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -38,7 +38,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/cougar_canyon2/mainboard.c b/src/mainboard/intel/cougar_canyon2/mainboard.c index 0ea03d3..f0062d5 100644 --- a/src/mainboard/intel/cougar_canyon2/mainboard.c +++ b/src/mainboard/intel/cougar_canyon2/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c index 809feec..78dfb62 100644 --- a/src/mainboard/intel/eagleheights/mptable.c +++ b/src/mainboard/intel/eagleheights/mptable.c @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; int bus_isa, i; uint32_t pin, route; - device_t dev; + struct device * dev; struct resource *res; unsigned long rcba; diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index 347ce8a..1f92309 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c index 21664ce..6dcf7d7 100644 --- a/src/mainboard/intel/jarrell/mptable.c +++ b/src/mainboard/intel/jarrell/mptable.c @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -91,7 +91,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c index 3da1e23..ce9872a 100644 --- a/src/mainboard/intel/minnowmax/mainboard.c +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -25,7 +25,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c index 7559fc2..387931d 100644 --- a/src/mainboard/intel/mohonpeak/mainboard.c +++ b/src/mainboard/intel/mohonpeak/mainboard.c @@ -24,7 +24,7 @@ * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c index 9ad6ea6..2c7eb92 100644 --- a/src/mainboard/intel/truxton/mptable.c +++ b/src/mainboard/intel/truxton/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) u8 bus_pea0 = 0; u8 bus_pea1 = 0; u8 bus_aioc; - device_t dev; + struct device * dev; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index a6839fc..be142aa 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index cc7eda5..65e4bcc 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -19,7 +19,7 @@ static int bus_isa; static void xe7501devkit_register_ioapics(struct mp_config_table *mc) { - device_t dev; + struct device * dev; struct resource *res; // TODO: Gack. This is REALLY ugly. diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c index dfc6636..457c88f 100644 --- a/src/mainboard/iwave/iWRainbowG6/mainboard.c +++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c @@ -22,7 +22,7 @@ #include <console/console.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c index 87de022..da83738 100644 --- a/src/mainboard/iwave/iWRainbowG6/mptable.c +++ b/src/mainboard/iwave/iWRainbowG6/mptable.c @@ -36,7 +36,7 @@ void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index 8868f46..be033f5 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); @@ -76,7 +76,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c index 0202b50..909e5a9 100644 --- a/src/mainboard/iwill/dk8_htx/mainboard.c +++ b/src/mainboard/iwill/dk8_htx/mainboard.c @@ -7,7 +7,7 @@ #include <cpu/amd/amdk8_sysconf.h> #include "mainboard.h" -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c index ff6e582..416cd17 100644 --- a/src/mainboard/iwill/dk8_htx/mptable.c +++ b/src/mainboard/iwill/dk8_htx/mptable.c @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1)); if (dev) { @@ -126,7 +126,7 @@ static void *smp_write_config_table(void *v) for(i=1; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; int ii; - device_t dev; + struct device * dev; struct resource *res; switch(sysconf.hcid[i]) { case 1: diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c index c7bb33d..622b412 100644 --- a/src/mainboard/iwill/dk8s2/mptable.c +++ b/src/mainboard/iwill/dk8s2/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c index c7bb33d..622b412 100644 --- a/src/mainboard/iwill/dk8x/mptable.c +++ b/src/mainboard/iwill/dk8x/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /* IOAPIC handling */ smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index d67e072..92c8d70 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -153,7 +153,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index 4390605..2c9606a 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -116,7 +116,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_E]); /* Use INTE */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0 */ diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 373ebb5..6da52fc 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -39,7 +39,7 @@ u8 is_dev3_present(void); void set_pcie_dereset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -52,7 +52,7 @@ void set_pcie_dereset() void set_pcie_reset() { u16 word; - device_t sm_dev; + struct device * sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -72,7 +72,7 @@ static void get_ide_dma66(void) { u8 byte; /*u32 sm_dev, ide_dev; */ - device_t sm_dev, ide_dev; + struct device * sm_dev, ide_dev; sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -100,7 +100,7 @@ u8 is_dev3_present(void) * enable the dedicated function in this board. * This function called early than rs780_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c index 7cabdf1..0c7130b 100644 --- a/src/mainboard/jetway/pa78vm5/mptable.c +++ b/src/mainboard/jetway/pa78vm5/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index afca796..0ae64b5 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -164,7 +164,7 @@ static void hwm_setup(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 3); hwm_setup(); diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/kontron/kt690/get_bus_conf.c +++ b/src/mainboard/kontron/kt690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c index 717c399..a88a2c8 100644 --- a/src/mainboard/kontron/kt690/mainboard.c +++ b/src/mainboard/kontron/kt690/mainboard.c @@ -119,7 +119,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -180,7 +180,7 @@ static void set_thermal_config(void) * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/kontron/kt690/mptable.c +++ b/src/mainboard/kontron/kt690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index 715ec56..6f6c2d8 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -172,7 +172,7 @@ static int int15_handler(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ @@ -181,7 +181,7 @@ static void mainboard_enable(device_t dev) unsigned disable = 0; if ((get_option(&disable, "ethernet1") == CB_SUCCESS) && disable) { - device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); + struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 2)); if (nic) { printk(BIOS_DEBUG, "DISABLE FIRST NIC!\n"); nic->enabled = 0; @@ -189,7 +189,7 @@ static void mainboard_enable(device_t dev) } disable = 0; if ((get_option(&disable, "ethernet2") == CB_SUCCESS) && disable) { - device_t nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); + struct device * nic = dev_find_slot(0, PCI_DEVFN(0x1c, 3)); if (nic) { printk(BIOS_DEBUG, "DISABLE SECOND NIC!\n"); nic->enabled = 0; diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index 387bbe0..ddd6d22 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -65,7 +65,7 @@ static void mainboard_init(device_t dev) /* mainboard_enable is executed as first thing after enumerate_buses(). */ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index f8c9dae..922b424 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -46,7 +46,7 @@ void mainboard_suspend_resume(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -69,7 +69,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 79b3da8..d960b11 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -61,10 +61,11 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + struct device * dev0; + struct device * idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); @@ -95,7 +96,7 @@ static void mainboard_init(device_t dev) ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 0054064..c79b552 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -45,7 +45,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* This sneaked in here, because X200 SuperIO chip isn't really connected to anything and hence we don't init it. @@ -53,7 +53,7 @@ static void mainboard_init(device_t dev) pc_keyboard_init(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 5b76be2..f61bb9a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -71,7 +71,7 @@ const char *smbios_mainboard_bios_version(void) -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -117,9 +117,9 @@ static void fill_ssdt(void) drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { - device_t dev0; + struct device * dev0; u16 pmbase; dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 00e7991..c86825e 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -49,7 +49,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -72,7 +72,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index a060015..28d7344 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -50,7 +50,7 @@ const char *smbios_mainboard_bios_version(void) return "CBET4000 " COREBOOT_VERSION; } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; @@ -73,7 +73,7 @@ static void mainboard_init(device_t dev) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 1d29c71..9f0cda4 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -56,9 +56,11 @@ int get_cst_entries(acpi_cstate_t **entries) return ARRAY_SIZE(cst_entries); } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { - device_t dev0, idedev, sdhci_dev; + struct device * dev0; + struct device * idedev; + struct device * sdhci_dev; ec_clr_bit(0x03, 2); @@ -115,7 +117,7 @@ static void fill_ssdt(void) drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index ee538c3..983df2c 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -163,7 +163,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index 078601e..6d91730 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 9e44a21..28ac9ba 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -130,7 +130,7 @@ void set_pcie_dereset(void) /********************************************** * Enable the dedicated functions of the board. **********************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); dev->ops->init = init; diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index 078601e..6d91730 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -104,7 +104,7 @@ static void *smp_write_config_table(void *v) /* on board NIC & Slot PCIE. */ /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + struct device * dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; /* PCI_SLOT 0. */ diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c index e364892..cb2bd5d 100644 --- a/src/mainboard/msi/ms7135/get_bus_conf.c +++ b/src/mainboard/msi/ms7135/get_bus_conf.c @@ -55,7 +55,7 @@ void get_bus_conf(void) { unsigned apicid_base; - device_t dev; + struct device *dev; unsigned sbdn; int i; diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c index b43a516..0c7032f 100644 --- a/src/mainboard/msi/ms7135/mptable.c +++ b/src/mainboard/msi/ms7135/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; u32 dword; diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c index 34d3834..97b2b70 100644 --- a/src/mainboard/msi/ms7260/get_bus_conf.c +++ b/src/mainboard/msi/ms7260/get_bus_conf.c @@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned int apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c index 492693a..d4e111f 100644 --- a/src/mainboard/msi/ms7260/mainboard.c +++ b/src/mainboard/msi/ms7260/mainboard.c @@ -23,7 +23,7 @@ #if 0 -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } #endif diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c index ea003a8..a200b70 100644 --- a/src/mainboard/msi/ms7260/mptable.c +++ b/src/mainboard/msi/ms7260/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 3a70d83..86afc47 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c index b30ab73..fc00858 100644 --- a/src/mainboard/msi/ms9185/mptable.c +++ b/src/mainboard/msi/ms9185/mptable.c @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; + struct device * dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); @@ -92,7 +92,7 @@ static void *smp_write_config_table(void *v) /* enable int */ /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/ { - device_t dev; + struct device * dev; dev = dev_find_device(0x1166, 0x0205, 0); if(dev) { uint32_t dword; diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c index 195ddc4..776fabb 100644 --- a/src/mainboard/msi/ms9282/get_bus_conf.c +++ b/src/mainboard/msi/ms9282/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c index c7e459a..54cdc3b 100644 --- a/src/mainboard/msi/ms9282/mainboard.c +++ b/src/mainboard/msi/ms9282/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c index 1764cf3..432e702 100644 --- a/src/mainboard/msi/ms9282/mptable.c +++ b/src/mainboard/msi/ms9282/mptable.c @@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 36ae12c..4ec04f5 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; printk(BIOS_SPEW, "get_bus_conf()\n"); diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c index 96760d6..7fc97f0 100644 --- a/src/mainboard/msi/ms9652_fam10/mainboard.c +++ b/src/mainboard/msi/ms9652_fam10/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c index 09a25f2..1b9b349 100644 --- a/src/mainboard/msi/ms9652_fam10/mptable.c +++ b/src/mainboard/msi/ms9652_fam10/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c index 1d7c79e..ede913f 100644 --- a/src/mainboard/newisys/khepri/mptable.c +++ b/src/mainboard/newisys/khepri/mptable.c @@ -20,7 +20,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* 8111 */ dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; /* 8131 apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x01,1)); diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c index 125b564..b77a355 100644 --- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c +++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c @@ -73,7 +73,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c index 291d4f7..a668696 100644 --- a/src/mainboard/nvidia/l1_2pvv/mainboard.c +++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c @@ -26,7 +26,7 @@ #include <device/pci_ops.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c index e991efd..5cdad5b 100644 --- a/src/mainboard/nvidia/l1_2pvv/mptable.c +++ b/src/mainboard/nvidia/l1_2pvv/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; @@ -117,7 +117,7 @@ static void *smp_write_config_table(void *v) //Slot PCIE for (j = 2; j < 8; j++) { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0)); if (!dev || !dev->enabled) continue; @@ -128,7 +128,7 @@ static void *smp_write_config_table(void *v) //Slot PCI 32 { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); if (dev && dev->enabled) { for (i = 0; i < 4; i++) @@ -148,7 +148,7 @@ static void *smp_write_config_table(void *v) //Slot PCIE for (j = 2; j < 8; j++) { - device_t dev; + struct device * dev; dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x0a + j - 2 , 0)); if (!dev || !dev->enabled) continue; diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index c14e9b7..c5b51e0 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -58,7 +58,7 @@ int get_cst_entries(acpi_cstate_t ** entries) -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { u16 pmbase; diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c index 2e3191b..421c916 100644 --- a/src/mainboard/rca/rm4100/mainboard.c +++ b/src/mainboard/rca/rm4100/mainboard.c @@ -20,12 +20,12 @@ #include <device/device.h> -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { // TODO Switch parport LEDs again } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { // TODO Switch parport LEDs dev->ops->init = mainboard_init; diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 4c7fffa..5421d13 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -63,14 +63,14 @@ static void dump_runtime_registers(void) } #endif -static void mainboard_final(device_t dev) +static void mainboard_final(struct device * dev) { /* Enable Dummy DCC ON# for DVI */ printk(BIOS_DEBUG, "Laptop handling...\n"); outb(inb(0x60f) & ~(1 << 5), 0x60f); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { /* Configure the MultiKey controller */ // m3885_configure_multikey(); diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index acf8023..39ade3f 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -44,7 +44,7 @@ static void ec_setup(void) send_ec_command(0xad); /* Set_Thml_Value */ } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { ec_setup(); /* LCD panel type is SIO GPIO40-43. diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 3bdd4d9..d53bf9e 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -46,9 +46,7 @@ void mainboard_suspend_resume(void) send_ec_command(EC_ACPI_ENABLE); } - - -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { /* Initialize the Embedded Controller */ lumpy_ec_init(); @@ -80,7 +78,7 @@ static int lumpy_smbios_type41_irq(int *handle, unsigned long *current, } -static int lumpy_onboard_smbios_data(device_t dev, int *handle, +static int lumpy_onboard_smbios_data(struct device * dev, int *handle, unsigned long *current) { int len = 0; @@ -101,7 +99,7 @@ static int lumpy_onboard_smbios_data(device_t dev, int *handle, // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; dev->ops->get_smbios_data = lumpy_onboard_smbios_data; diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c index 347ce8a..1f92309 100644 --- a/src/mainboard/samsung/stumpy/mainboard.c +++ b/src/mainboard/samsung/stumpy/mainboard.c @@ -44,7 +44,7 @@ void mainboard_suspend_resume(void) // mainboard_enable is executed as first thing after // enumerate_buses(). -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c +++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c index 77be0af..219527a 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c +++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c @@ -389,7 +389,7 @@ static void pm_init( void ) { u16 word; u8 byte; - device_t sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + struct device * sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); /* set SB600 GPIO 64 to GPIO with pull-up */ byte = pm2_ioread(0x42); @@ -432,7 +432,7 @@ static void set_thermal_config(void) { u8 byte, byte2; u8 cpu_pwm_conf, case_pwm_conf; - device_t sm_dev; + struct device * sm_dev; struct fan_control cpu_fan_control, case_fan_control; const char *name = NULL; @@ -614,8 +614,8 @@ static void patch_mmio_nonposted( void ) resource_t rbase, rend; u32 base, limit; struct resource *resource; - device_t dev; - device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); + struct device * dev; + struct device * k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18,1)); printk(BIOS_DEBUG,"%s ...\n", __func__); @@ -668,7 +668,7 @@ struct { unsigned int plx_present = 0; -static void update_subsystemid( device_t dev ) +static void update_subsystemid(struct device * dev) { int i; @@ -680,7 +680,7 @@ static void update_subsystemid( device_t dev ) } printk(BIOS_INFO, "%s [%x/%x]\n", dev_name(dev), dev->subsystem_vendor, dev->subsystem_device ); for( i=0; slot[i].bus < 255; i++) { - device_t d; + struct device * d; d = dev_find_slot(slot[i].bus,slot[i].devfn); if( d ) { printk(BIOS_DEBUG,"%s subsystem <- %x/%x\n", dev_path(d), dev->subsystem_vendor, dev->subsystem_device); @@ -695,10 +695,11 @@ static void update_subsystemid( device_t dev ) * @param */ -static void detect_hw_variant( device_t dev ) +static void detect_hw_variant(struct device * dev) { - device_t nb_dev =0, dev2 = 0; + struct device * nb_dev = NULL; + struct device * dev2 = NULL; struct southbridge_amd_rs690_config *cfg; u32 lc_state, id = 0; @@ -807,7 +808,7 @@ static void smm_lock( void ) * @param the root device */ -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { #if CONFIG_PCI_OPTION_ROM_RUN_REALMODE INT15_function_extensions int15_func; @@ -833,7 +834,7 @@ static void mainboard_init(device_t dev) * enable the dedicated function in sina board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "%s %s[%x/%x] %s\n", diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index de5151d..194b5ba 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); if (dev) { diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index f57719a..f716158 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; if (get_bus_conf_done == 1) return; //do it only once diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c index 1ba1dcf..6259278 100644 --- a/src/mainboard/sunw/ultra40/mptable.c +++ b/src/mainboard/sunw/ultra40/mptable.c @@ -49,7 +49,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 0279f8f..8b5ec69 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c index 17067ed..d53b498 100644 --- a/src/mainboard/supermicro/h8dme/mptable.c +++ b/src/mainboard/supermicro/h8dme/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 0279f8f..8b5ec69 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c index 11db23f..5a24259 100644 --- a/src/mainboard/supermicro/h8dmr/mptable.c +++ b/src/mainboard/supermicro/h8dmr/mptable.c @@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index a1de06c..71eb756 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -72,7 +72,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c index 4e2d48c..5c88156 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c +++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c index 8f12e22..cdce2f9 100644 --- a/src/mainboard/supermicro/h8qgi/mainboard.c +++ b/src/mainboard/supermicro/h8qgi/mainboard.c @@ -65,7 +65,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in h8qgi board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 50e2b44..7a80f74 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -74,7 +74,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index 4fbb4c8..79f8a5e 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c index 23b1d72..de1dead 100644 --- a/src/mainboard/supermicro/h8scm/mainboard.c +++ b/src/mainboard/supermicro/h8scm/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in h8scm board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 0560180..fc3a446 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -65,7 +65,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c index 18e1e8c..4908dcb 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c +++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c @@ -49,7 +49,7 @@ u8 is_dev3_present(void) ***/ void set_pcie_reset(void) { - device_t pcie_core_dev; + struct device * pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x28282828); @@ -58,7 +58,7 @@ void set_pcie_reset(void) void set_pcie_dereset(void) { - device_t pcie_core_dev; + struct device * pcie_core_dev; pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); set_htiu_enable_bits(pcie_core_dev, 0xA8, 0xFFFFFFFF, 0x6F6F6F6F); @@ -69,7 +69,7 @@ void set_pcie_dereset(void) * enable the dedicated function in h8scm board. * This function called early than sr5650_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c index 84593fc..864cdd1 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mptable.c +++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c @@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c index 0efae77..4185a54 100644 --- a/src/mainboard/supermicro/x6dai_g/mptable.c +++ b/src/mainboard/supermicro/x6dai_g/mptable.c @@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* southbridge */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c index ab73fc7..18fe954 100644 --- a/src/mainboard/supermicro/x6dhe_g/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g/mptable.c @@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; - device_t dev; + struct device * dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c index a2b8c8d..c4d690e 100644 --- a/src/mainboard/supermicro/x6dhe_g2/mptable.c +++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c @@ -21,7 +21,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* esb6300_2 */ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); @@ -65,7 +65,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000); { struct resource *res; - device_t dev; + struct device * dev; /* PXHd apic 4 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c index f9165d6..935ae8c 100644 --- a/src/mainboard/supermicro/x6dhr_ig/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(2, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c index b5ba6b1..56aec2e 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c +++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c @@ -22,7 +22,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* ich5r */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -89,7 +89,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); { struct resource *res; - device_t dev; + struct device * dev; /* pxhd apic 3 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,1)); if (dev) { diff --git a/src/mainboard/supermicro/x7db8/mainboard.c b/src/mainboard/supermicro/x7db8/mainboard.c index 1d666c9..cf0c044 100644 --- a/src/mainboard/supermicro/x7db8/mainboard.c +++ b/src/mainboard/supermicro/x7db8/mainboard.c @@ -27,7 +27,7 @@ #include <device/pci_ops.h> #include <arch/io.h> -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { } diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/technexion/tim5690/get_bus_conf.c +++ b/src/mainboard/technexion/tim5690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c index 3423e51..da4ed9a 100644 --- a/src/mainboard/technexion/tim5690/mainboard.c +++ b/src/mainboard/technexion/tim5690/mainboard.c @@ -117,7 +117,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -222,7 +222,7 @@ static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) * enable the dedicated function in tim5690 board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { u16 gpio_base = IT8712F_SIMPLE_IO_BASE; #if CONFIG_VGA_ROM_RUN diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/technexion/tim5690/mptable.c +++ b/src/mainboard/technexion/tim5690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/technexion/tim8690/get_bus_conf.c +++ b/src/mainboard/technexion/tim8690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c index 6010eb1..14811bb 100644 --- a/src/mainboard/technexion/tim8690/mainboard.c +++ b/src/mainboard/technexion/tim8690/mainboard.c @@ -53,7 +53,7 @@ static void enable_onboard_nic(void) { u8 byte; - device_t sm_dev; + struct device * sm_dev; printk(BIOS_INFO, "enable_onboard_nic.\n"); @@ -79,7 +79,7 @@ static void set_thermal_config(void) { u8 byte; u16 word; - device_t sm_dev; + struct device * sm_dev; /* set ADT 7461 */ ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */ @@ -140,7 +140,7 @@ static void set_thermal_config(void) * enable the dedicated function in tim8690 board. * This function called early than rs690_enable. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c index 8b86b02..840a93a 100644 --- a/src/mainboard/technexion/tim8690/mptable.c +++ b/src/mainboard/technexion/tim8690/mptable.c @@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v) /* I/O APICs: APIC ID Version State Address */ { - device_t dev; + struct device * dev; u32 dword; u8 byte; diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c index 7267696..9bd4f53 100644 --- a/src/mainboard/thomson/ip1000/mainboard.c +++ b/src/mainboard/thomson/ip1000/mainboard.c @@ -84,13 +84,13 @@ static void flash_gpios(void) } } -static void mainboard_init(device_t dev) +static void mainboard_init(struct device * dev) { parport_gpios(); flash_gpios(); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->init = mainboard_init; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c index 9073728..9f65205 100644 --- a/src/mainboard/tyan/s2735/mptable.c +++ b/src/mainboard/tyan/s2735/mptable.c @@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 8, 0x20, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(1, PCI_DEVFN(0x1e,0)); if (dev) { diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c index 371d9a3..3145e32 100644 --- a/src/mainboard/tyan/s2850/mptable.c +++ b/src/mainboard/tyan/s2850/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c index 90299a7..798ea64 100644 --- a/src/mainboard/tyan/s2875/mptable.c +++ b/src/mainboard/tyan/s2875/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c index 32fc639..cbefcdb 100644 --- a/src/mainboard/tyan/s2880/mptable.c +++ b/src/mainboard/tyan/s2880/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index 332e578..b2177a4 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -53,7 +53,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c index 7df5e87..d28a104 100644 --- a/src/mainboard/tyan/s2881/mptable.c +++ b/src/mainboard/tyan/s2881/mptable.c @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index 6c07965..b06b49c 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -11,7 +11,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 0); @@ -118,7 +118,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index 88706c0..dfd62b8 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -56,7 +56,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c index 26081c7..6413230 100644 --- a/src/mainboard/tyan/s2885/mptable.c +++ b/src/mainboard/tyan/s2885/mptable.c @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111 { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); if (dev) { diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index e94c608..5ff3e3b 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -60,7 +60,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/tyan/s2891/mainboard.c +++ b/src/mainboard/tyan/s2891/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index cb49434..f52a07b 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 0ead854..e59cd33 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -58,7 +58,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/tyan/s2892/mainboard.c +++ b/src/mainboard/tyan/s2892/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c index 882ac69..d3dc505 100644 --- a/src/mainboard/tyan/s2892/mptable.c +++ b/src/mainboard/tyan/s2892/mptable.c @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c index 11b1bc2..c6d9a08 100644 --- a/src/mainboard/tyan/s2895/get_bus_conf.c +++ b/src/mainboard/tyan/s2895/get_bus_conf.c @@ -66,7 +66,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c index 604df51..85f5556 100644 --- a/src/mainboard/tyan/s2895/mainboard.c +++ b/src/mainboard/tyan/s2895/mainboard.c @@ -12,7 +12,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c index 20fa92c..3c4242f 100644 --- a/src/mainboard/tyan/s2895/mptable.c +++ b/src/mainboard/tyan/s2895/mptable.c @@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index 7727c4b..fb38d32 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c index 133ce43..8620cd4 100644 --- a/src/mainboard/tyan/s2912/mptable.c +++ b/src/mainboard/tyan/s2912/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 0a3a9d8..6a9e2e9 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c index e15387d..0b7ce31 100644 --- a/src/mainboard/tyan/s2912_fam10/mptable.c +++ b/src/mainboard/tyan/s2912_fam10/mptable.c @@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword; diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c index dcc0fd8..3ec04bb 100644 --- a/src/mainboard/tyan/s4880/mptable.c +++ b/src/mainboard/tyan/s4880/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 2); @@ -120,7 +120,7 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c index 350b55c..3d22fd9 100644 --- a/src/mainboard/tyan/s4882/mptable.c +++ b/src/mainboard/tyan/s4882/mptable.c @@ -10,7 +10,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - device_t dev; + struct device * dev; unsigned reg; dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); @@ -62,7 +62,7 @@ static void *smp_write_config_table(void *v) smp_write_processors(mc); { - device_t dev; + struct device * dev; /* HT chain 0 */ bus_chain_0 = node_link_to_bus(0, 1); @@ -119,7 +119,7 @@ static void *smp_write_config_table(void *v) apicid_8131_2 = apicid_base+2; smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); { - device_t dev; + struct device * dev; struct resource *res; dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { diff --git a/src/mainboard/tyan/s8226/mainboard.c b/src/mainboard/tyan/s8226/mainboard.c index 9e8160a..6f094cb 100644 --- a/src/mainboard/tyan/s8226/mainboard.c +++ b/src/mainboard/tyan/s8226/mainboard.c @@ -67,7 +67,7 @@ void set_pcie_dereset(void *nbconfig) /************************************************* * enable the dedicated function in s8226 board. *************************************************/ -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); } diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 5ec4a35..230cacc 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) int bus_isa; u32 apicid_sp5100; u32 apicid_sr5650; - device_t dev; + struct device * dev; u32 dword; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index dbe682c..146c21b 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -95,7 +95,7 @@ static int vx900_int15_handler(void) } #endif -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { (void)dev; diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c index 5b96b05..1c7e1da 100644 --- a/src/mainboard/winent/mb6047/get_bus_conf.c +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -35,7 +35,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/winent/mb6047/mainboard.c b/src/mainboard/winent/mb6047/mainboard.c index 9a8dd90..5f261c6 100644 --- a/src/mainboard/winent/mb6047/mainboard.c +++ b/src/mainboard/winent/mb6047/mainboard.c @@ -10,7 +10,7 @@ static void mainboard_acpi_fill_ssdt_generator(void) { amd_generate_powernow(0, 0, 0); } -static void mainboard_enable(device_t dev) +static void mainboard_enable(struct device * dev) { dev->ops->acpi_fill_ssdt_generator = mainboard_acpi_fill_ssdt_generator; } diff --git a/src/mainboard/winent/mb6047/mptable.c b/src/mainboard/winent/mb6047/mptable.c index 26e79ca..afbb8b9 100644 --- a/src/mainboard/winent/mb6047/mptable.c +++ b/src/mainboard/winent/mb6047/mptable.c @@ -33,7 +33,7 @@ static void *smp_write_config_table(void *v) /*I/O APICs: APIC ID Version State Address*/ { - device_t dev; + struct device * dev; struct resource *res; uint32_t dword;
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New patch to review for coreboot: 958d2b4 mainboard: TEST BUILD romstage.c
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7280
-gerrit commit 958d2b4f18e003978a6d157774572f0303c2f9c4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 06:57:47 2014 +1100 mainboard: TEST BUILD romstage.c Change-Id: Ibcd6d28493fc3f404462238dde0fe54c61d043d3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/thatcher/romstage.c | 2 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 4 ++-- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/getac/p470/romstage.c | 8 ++++---- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/iei/pm-lx2-800-r10/romstage.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/intel/jarrell/romstage.c | 2 +- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 6 +++--- src/mainboard/kontron/ktqm77/romstage.c | 6 +++--- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 8 ++++---- src/mainboard/roda/rk9/romstage.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 ++-- src/mainboard/supermicro/x6dai_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g/romstage.c | 2 +- src/mainboard/supermicro/x6dhe_g2/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig/romstage.c | 2 +- src/mainboard/supermicro/x6dhr_ig2/romstage.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m/romstage.c | 6 +++--- src/mainboard/via/epia-m700/romstage.c | 8 ++++---- src/mainboard/via/epia-n/romstage.c | 4 ++-- src/mainboard/via/epia/romstage.c | 4 ++-- src/mainboard/via/vt8454c/romstage.c | 2 +- 34 files changed, 53 insertions(+), 53 deletions(-) diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index cc97866..68993e4 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -46,7 +46,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devnfn_t dev; AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); hudson_lpc_port80(); diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index c137b14..b90838d 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 5c78ab1..fa1cfd5 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index caa32ca..11775d7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -67,7 +67,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devnfn_t dev; #if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE) hudson_pci_port80(); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15b8682..c5cdfee 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -88,7 +88,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index d12b77c..cfa3ec9 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -72,7 +72,7 @@ static void sio_setup(void) { u8 byte; u32 dword; - device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ + pci_devnfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ /* Subject decoding */ byte = pci_read_config8(dev, 0x7b); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index adcdfc7..8c6da43 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -107,7 +107,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 30ba468..7dd7a4a 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -91,7 +91,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); @@ -189,7 +189,7 @@ static void m2v_it8712f_gpio_init(void) static void m2v_bus_init(void) { - device_t dev; + pci_devnfn_t dev; printk(BIOS_SPEW, "m2v_bus_init\n"); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 898ad1a..0c9e7cf 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -47,7 +47,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 3dab527..3a756e5 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -105,19 +105,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pci_devnfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pci_devnfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); } -static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pci_devnfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -126,7 +126,7 @@ static void pnp_write_register(device_t dev, int reg, int val) static void early_superio_config(void) { - device_t dev; + pci_devnfn_t dev; dev=PNP_DEV(0x4e, 0x00); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 322907b..5eb3c2b 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -76,7 +76,7 @@ static void ich7_enable_lpc(void) */ static void early_superio_config_w83627ehg(void) { - device_t dev; + pci_devnfn_t dev; dev = DUMMY_DEV; pnp_enter_ext_func_mode(dev); diff --git a/src/mainboard/iei/pm-lx2-800-r10/romstage.c b/src/mainboard/iei/pm-lx2-800-r10/romstage.c index a83bf7e..40f8e3f 100644 --- a/src/mainboard/iei/pm-lx2-800-r10/romstage.c +++ b/src/mainboard/iei/pm-lx2-800-r10/romstage.c @@ -69,7 +69,7 @@ void main(unsigned long bist) console_init(); /* Enable COM3. */ - device_t dev = PNP_DEV(0x2e, 0x0b); + pci_devnfn_t dev = PNP_DEV(0x2e, 0x0b); u16 port = dev >> 8; outb(0x55, port); pnp_set_logical_device(dev); diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index cc956a7..c92b546 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -56,7 +56,7 @@ static inline void reset_system(void) static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devnfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 220b1d7..6d1d2a5 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -47,7 +47,7 @@ static void pch_enable_lpc(void) { - device_t dev = PCH_LPC_DEV; + pci_devnfn_t dev = PCH_LPC_DEV; /* Set COM1/COM2 decode range */ pci_write_config16(dev, LPC_IO_DEC, 0x0010); diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index f1cf4c3..f9f00a8 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -75,7 +75,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index a9c71c3..3a8faee 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 2c12c5d..19ec9d2 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -78,14 +78,14 @@ static void ich7_enable_lpc(void) } /* TODO: superio code should really not be in mainboard */ -static void pnp_enter_func_mode(device_t dev) +static void pnp_enter_func_mode(pci_devnfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_func_mode(device_t dev) +static void pnp_exit_func_mode(pci_devnfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -98,7 +98,7 @@ static void pnp_exit_func_mode(device_t dev) */ static void early_superio_config_w83627thg(void) { - device_t dev; + pci_devnfn_t dev; dev=PNP_DEV(0x2e, W83627THG_SP1); pnp_enter_func_mode(dev); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 401314c..4912328 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -125,14 +125,14 @@ static void rcba_config(void) RCBA32(FD) = reg32; } -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pci_devnfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pci_devnfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -142,7 +142,7 @@ static void superio_gpio_config(void) { int lvds_3v = 0; // 0 (5V) or 1 (3V3) int dis_bl_inv = 1; // backlight inversion: 1 = disabled, 0 = enabled - device_t dev = PNP_DEV(0x2e, 0x9); + pci_devnfn_t dev = PNP_DEV(0x2e, 0x9); pnp_enter_ext_func_mode(dev); pnp_write_config(dev, 0x29, 0x02); /* Pins 119, 120 are GPIO21, 20 */ pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO2+3 */ diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index f11b33e..a888d30 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -98,7 +98,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pci_devnfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0xa0); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 943143a..e2ebde9 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -105,7 +105,7 @@ static void ich7_enable_lpc(void) static void early_superio_config(void) { int timeout = 100000; - device_t dev = PNP_DEV(0x2e, 3); + pci_devnfn_t dev = PNP_DEV(0x2e, 3); pnp_write_config(dev, 0x29, 0x06); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7cc1a1d..d25bf50 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -93,19 +93,19 @@ static void ich7_enable_lpc(void) * the two. Also set up the GPIOs from the beginning. This is the "no schematic * but safe anyways" method. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static inline void pnp_enter_ext_func_mode(pci_devnfn_t dev) { unsigned int port = dev >> 8; outb(0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pci_devnfn_t dev) { unsigned int port = dev >> 8; outb(0xaa, port); } -static void pnp_write_register(device_t dev, int reg, int val) +static void pnp_write_register(pci_devnfn_t dev, int reg, int val) { unsigned int port = dev >> 8; outb(reg, port); @@ -114,7 +114,7 @@ static void pnp_write_register(device_t dev, int reg, int val) static void early_superio_config(void) { - device_t dev; + pci_devnfn_t dev; dev=PNP_DEV(0x2e, 0x00); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index c8b75e0..01692c9 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -88,7 +88,7 @@ static void default_superio_gpio_setup(void) GP1 GP2 GP3 GP4 fd 17 88 14 */ - const device_t sio = PNP_DEV(0x2e, 0); + const pci_devnfn_t sio = PNP_DEV(0x2e, 0); /* Enter super-io's configuration state. */ pnp_enter_conf_state(sio); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 24ecb5d..83bf6d5 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -115,14 +115,14 @@ static const u8 spd_addr[] = { #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) /* TODO: superio code should really not be in mainboard */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pci_devnfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pci_devnfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 0385cad..79ff5de 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -70,7 +70,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing 6300ESB?"); diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 405a2bc..37af097 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -73,7 +73,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing esb6300?"); diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 48945eb..4ad2291 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -73,7 +73,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5r?"); diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 08b0ccd..a059494 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -72,7 +72,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index dfe0da2..b6f2122 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -72,7 +72,7 @@ static void main(unsigned long bist) /* MOVE ME TO A BETTER LOCATION !!! */ /* config LPC decode for flash memory access */ - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); if (dev == PCI_DEV_INVALID) die("Missing ich5?"); diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 20f99cb..d9f6968 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -44,7 +44,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 3f2a0c4..1c6729c 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -25,7 +25,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); @@ -57,7 +57,7 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { - device_t dev = 0; /* no need to look up 0:0.0 */ + pci_devnfn_t dev = 0; /* no need to look up 0:0.0 */ unsigned char shadowreg; /* dev 0 for southbridge */ shadowreg = pci_read_config8(dev, 0x63); @@ -69,7 +69,7 @@ static void enable_shadow_ram(void) #include <cpu/intel/romstage.h> static void main(unsigned long bist) { - device_t dev; + pci_devnfn_t dev; /* Enable VGA; 32MB buffer. */ pci_write_config8(0, 0xe1, 0xdd); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index b00ece1..0333ca0 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -55,7 +55,7 @@ */ static int acpi_is_wakeup_early_via_vx800(void) { - device_t dev; + pci_devnfn_t dev; u16 tmp, result; print_debug("In acpi_is_wakeup_early_via_vx800\n"); @@ -83,7 +83,7 @@ static int acpi_is_wakeup_early_via_vx800(void) /* All content of this function came from the cx700 port of coreboot. */ static void enable_mainboard_devices(void) { - device_t dev; + pci_devnfn_t dev; #if 0 /* * Add and close this switch, since some line cause error, some @@ -378,8 +378,8 @@ void main(unsigned long bist) { u16 boot_mode; u8 rambits, Data8, Data; - device_t device; - /* device_t dev; */ + pci_devnfn_t device; + /* pci_devnfn_t dev; */ /* * Enable multifunction for northbridge. These 4 lines (until diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 2ede8d8..9221875 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -58,7 +58,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devnfn_t dev; u8 reg; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, @@ -105,7 +105,7 @@ static void enable_shadow_ram(void) static void main(unsigned long bist) { unsigned long x; - device_t dev; + pci_devnfn_t dev; /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 1d312d7..0a7d308 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -24,7 +24,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) static void enable_mainboard_devices(void) { - device_t dev; + pci_devnfn_t dev; /* dev 0 for southbridge */ dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0); @@ -60,7 +60,7 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { - device_t dev = 0; + pci_devnfn_t dev = 0; unsigned char shadowreg; shadowreg = pci_read_config8(dev, 0x63); diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index f6d58c8..caa0494 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -39,7 +39,7 @@ static void enable_mainboard_devices(void) { - device_t dev; + pci_devnfn_t dev; dev = pci_locate_device(PCI_ID(0x1106, 0x8324), 0); if (dev == PCI_DEV_INVALID) {
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New patch to review for coreboot: 2ff7cd5 mainboard/dmp/vortex86ec: Unused variable in romstage.c
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7279
-gerrit commit 2ff7cd5ec0339c018b652fac86d8a27e038656f2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 06:55:46 2014 +1100 mainboard/dmp/vortex86ec: Unused variable in romstage.c Change-Id: I9cc549b7862ee535928bd06b5fb4bd38bb67a992 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/dmp/vortex86ex/romstage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index a7b31ca..e7933d5 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -303,7 +303,6 @@ static void enable_l2_cache(void) #include <cpu/intel/romstage.h> static void main(unsigned long bist) { - device_t dev; u32 dmp_id; dmp_id = get_dmp_id();
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New patch to review for coreboot: 96f2781 mainboard: TEST BUILD
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7278
-gerrit commit 96f2781df5fb7af6d62a93dd908b8201d647832e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Oct 31 06:30:43 2014 +1100 mainboard: TEST BUILD Change-Id: I13f2ef26aeea0ebd9f6e2985051ddc2e3ed1e02c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/advansus/a785e-i/get_bus_conf.c | 2 +- src/mainboard/amd/bimini_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/dbm690t/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany/get_bus_conf.c | 2 +- src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 2 +- src/mainboard/amd/pistachio/get_bus_conf.c | 2 +- src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c | 4 ++-- src/mainboard/amd/tilapia_fam10/get_bus_conf.c | 2 +- src/mainboard/asrock/939a785gmh/get_bus_conf.c | 2 +- src/mainboard/asus/a8n_e/get_bus_conf.c | 2 +- src/mainboard/asus/m2n-e/get_bus_conf.c | 2 +- src/mainboard/asus/m4a78-em/get_bus_conf.c | 2 +- src/mainboard/asus/m4a785-m/get_bus_conf.c | 2 +- src/mainboard/asus/m5a88-v/get_bus_conf.c | 2 +- src/mainboard/avalue/eax-785e/get_bus_conf.c | 2 +- src/mainboard/broadcom/blast/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 2 +- src/mainboard/gigabyte/m57sli/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 2 +- src/mainboard/gigabyte/ma78gm/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g1/get_bus_conf.c | 2 +- src/mainboard/hp/dl145_g3/get_bus_conf.c | 2 +- src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 2 +- src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 2 +- src/mainboard/iwill/dk8_htx/get_bus_conf.c | 4 ++-- src/mainboard/jetway/pa78vm5/get_bus_conf.c | 2 +- src/mainboard/kontron/kt690/get_bus_conf.c | 2 +- src/mainboard/msi/ms7135/get_bus_conf.c | 2 +- src/mainboard/msi/ms7260/get_bus_conf.c | 2 +- src/mainboard/msi/ms9185/get_bus_conf.c | 2 +- src/mainboard/msi/ms9282/get_bus_conf.c | 2 +- src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 2 +- src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 2 +- src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 2 +- src/mainboard/sunw/ultra40/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dme/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dmr/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c | 2 +- src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c | 2 +- src/mainboard/technexion/tim5690/get_bus_conf.c | 2 +- src/mainboard/technexion/tim8690/get_bus_conf.c | 2 +- src/mainboard/tyan/s2881/get_bus_conf.c | 2 +- src/mainboard/tyan/s2885/get_bus_conf.c | 2 +- src/mainboard/tyan/s2891/get_bus_conf.c | 2 +- src/mainboard/tyan/s2892/get_bus_conf.c | 2 +- src/mainboard/tyan/s2895/get_bus_conf.c | 2 +- src/mainboard/tyan/s2912/get_bus_conf.c | 2 +- src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 2 +- src/mainboard/winent/mb6047/get_bus_conf.c | 2 +- 52 files changed, 55 insertions(+), 55 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c index 80e1d3e..2c5757a 100644 --- a/src/mainboard/advansus/a785e-i/get_bus_conf.c +++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c index f7c55143..6b31272 100644 --- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c +++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c @@ -64,7 +64,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/amd/dbm690t/get_bus_conf.c +++ b/src/mainboard/amd/dbm690t/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c index f05ce7f..2e5a44f 100644 --- a/src/mainboard/amd/mahogany/get_bus_conf.c +++ b/src/mainboard/amd/mahogany/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c +++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/amd/pistachio/get_bus_conf.c +++ b/src/mainboard/amd/pistachio/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c index f5cd846..f2d7f9e 100644 --- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c @@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); @@ -76,7 +76,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 48d5cc3..02dfb3c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ static u32 get_hcid(u32 i) u32 id = 0; u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; u32 devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); @@ -95,7 +95,7 @@ void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c +++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c index f05ce7f..2e5a44f 100644 --- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c +++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c index a55401b..22d0123 100644 --- a/src/mainboard/asus/a8n_e/get_bus_conf.c +++ b/src/mainboard/asus/a8n_e/get_bus_conf.c @@ -63,7 +63,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c index fd7d304..c9d113d 100644 --- a/src/mainboard/asus/m2n-e/get_bus_conf.c +++ b/src/mainboard/asus/m2n-e/get_bus_conf.c @@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned int apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/asus/m4a78-em/get_bus_conf.c +++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/asus/m4a785-m/get_bus_conf.c +++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index f90c6b8..4c8efff 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c index f90c6b8..4c8efff 100644 --- a/src/mainboard/avalue/eax-785e/get_bus_conf.c +++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c @@ -67,7 +67,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c index 5de8952..f95d70a 100644 --- a/src/mainboard/broadcom/blast/get_bus_conf.c +++ b/src/mainboard/broadcom/blast/get_bus_conf.c @@ -50,7 +50,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c index 9315cbd..c9c1950 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c index c798415..db5b685 100644 --- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c +++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c +++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index acfa023..6a36ef7 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -51,7 +51,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c index ba0fc88..59b35aa 100644 --- a/src/mainboard/hp/dl145_g3/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c index 099c41a..6561c94 100644 --- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c +++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c index 8868f46..be033f5 100644 --- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c +++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c @@ -48,7 +48,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); @@ -76,7 +76,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i, j; struct mb_sysconf_t *m; diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c index 47342fb..414b6e7 100644 --- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c +++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/kontron/kt690/get_bus_conf.c +++ b/src/mainboard/kontron/kt690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c index e364892..cb2bd5d 100644 --- a/src/mainboard/msi/ms7135/get_bus_conf.c +++ b/src/mainboard/msi/ms7135/get_bus_conf.c @@ -55,7 +55,7 @@ void get_bus_conf(void) { unsigned apicid_base; - device_t dev; + struct device *dev; unsigned sbdn; int i; diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c index 34d3834..97b2b70 100644 --- a/src/mainboard/msi/ms7260/get_bus_conf.c +++ b/src/mainboard/msi/ms7260/get_bus_conf.c @@ -69,7 +69,7 @@ static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned int apicid_base, sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c index 3a70d83..86afc47 100644 --- a/src/mainboard/msi/ms9185/get_bus_conf.c +++ b/src/mainboard/msi/ms9185/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; struct mb_sysconf_t *m; diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c index 195ddc4..776fabb 100644 --- a/src/mainboard/msi/ms9282/get_bus_conf.c +++ b/src/mainboard/msi/ms9282/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 36ae12c..4ec04f5 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; printk(BIOS_SPEW, "get_bus_conf()\n"); diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c index 125b564..b77a355 100644 --- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c +++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c @@ -73,7 +73,7 @@ static unsigned get_hcid(unsigned i) unsigned devn = sysconf.hcdn[i] & 0xff; - device_t dev; + struct device *dev; dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c +++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c index f57719a..f716158 100644 --- a/src/mainboard/sunw/ultra40/get_bus_conf.c +++ b/src/mainboard/sunw/ultra40/get_bus_conf.c @@ -67,7 +67,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; if (get_bus_conf_done == 1) return; //do it only once diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c index 0279f8f..8b5ec69 100644 --- a/src/mainboard/supermicro/h8dme/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c index 0279f8f..8b5ec69 100644 --- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index a1de06c..71eb756 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -72,7 +72,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 50e2b44..7a80f74 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -74,7 +74,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c index 0560180..fc3a446 100644 --- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c @@ -65,7 +65,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/technexion/tim5690/get_bus_conf.c +++ b/src/mainboard/technexion/tim5690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c index 084e2b1..c959280 100644 --- a/src/mainboard/technexion/tim8690/get_bus_conf.c +++ b/src/mainboard/technexion/tim8690/get_bus_conf.c @@ -63,7 +63,7 @@ static u32 get_bus_conf_done = 0; void get_bus_conf(void) { u32 apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c index 332e578..b2177a4 100644 --- a/src/mainboard/tyan/s2881/get_bus_conf.c +++ b/src/mainboard/tyan/s2881/get_bus_conf.c @@ -53,7 +53,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c index 88706c0..dfd62b8 100644 --- a/src/mainboard/tyan/s2885/get_bus_conf.c +++ b/src/mainboard/tyan/s2885/get_bus_conf.c @@ -56,7 +56,7 @@ void get_bus_conf(void) unsigned apicid_base; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c index e94c608..5ff3e3b 100644 --- a/src/mainboard/tyan/s2891/get_bus_conf.c +++ b/src/mainboard/tyan/s2891/get_bus_conf.c @@ -60,7 +60,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c index 0ead854..e59cd33 100644 --- a/src/mainboard/tyan/s2892/get_bus_conf.c +++ b/src/mainboard/tyan/s2892/get_bus_conf.c @@ -58,7 +58,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c index 11b1bc2..c6d9a08 100644 --- a/src/mainboard/tyan/s2895/get_bus_conf.c +++ b/src/mainboard/tyan/s2895/get_bus_conf.c @@ -66,7 +66,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1) diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c index 7727c4b..fb38d32 100644 --- a/src/mainboard/tyan/s2912/get_bus_conf.c +++ b/src/mainboard/tyan/s2912/get_bus_conf.c @@ -70,7 +70,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 0a3a9d8..6a9e2e9 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -71,7 +71,7 @@ void get_bus_conf(void) unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; + struct device *dev; int i; if(get_bus_conf_done==1) return; //do it only once diff --git a/src/mainboard/winent/mb6047/get_bus_conf.c b/src/mainboard/winent/mb6047/get_bus_conf.c index 5b96b05..1c7e1da 100644 --- a/src/mainboard/winent/mb6047/get_bus_conf.c +++ b/src/mainboard/winent/mb6047/get_bus_conf.c @@ -35,7 +35,7 @@ void get_bus_conf(void) unsigned apicid_base; unsigned sbdn; - device_t dev; + struct device *dev; int i; if (get_bus_conf_done == 1)
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Patch set updated for coreboot: 07815a0 Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c'
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7196
-gerrit commit 07815a09e2b5e1b49aae98f71f874504207c50ba Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 10:36:02 2014 +1100 Use 'pci_devfn_t' over 'device_t' mixed type in 'reset.c' Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/amdfam10/reset_test.c | 10 +++++----- src/northbridge/amd/amdk8/reset_test.c | 4 ++-- src/southbridge/amd/amd8111/reset.c | 14 ++++++-------- src/southbridge/broadcom/bcm5785/reset.c | 6 ++---- src/southbridge/nvidia/ck804/reset.c | 6 ++---- src/southbridge/nvidia/mcp55/reset.c | 6 ++---- src/southbridge/sis/sis966/reset.c | 6 ++---- 7 files changed, 21 insertions(+), 31 deletions(-) diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 24f5397..de7949e 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -32,7 +32,7 @@ u32 cpu_init_detected(u8 nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev; dev = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(dev, HT_INIT_CONTROL); @@ -67,7 +67,7 @@ u32 other_reset_detected(void) // other warm reset not started by BIOS static void distinguish_cpu_resets(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; @@ -77,7 +77,7 @@ static void distinguish_cpu_resets(u8 nodeid) static u32 warm_reset_detect(u8 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = NODE_PCI(nodeid, 0); htic = pci_io_read_config32(device, HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); @@ -89,7 +89,7 @@ void __attribute__ ((weak)) set_bios_reset(void) u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; @@ -134,7 +134,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b int i; int j; u32 cfg_map_dest; - device_t dev; + pci_devfn_t dev; cfg_map_dest = (1<<7)|(1<<6)|link; diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index 6ef3ec0..8015290 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -10,7 +10,7 @@ static inline int cpu_init_detected(unsigned nodeid) { u32 htic; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); @@ -37,7 +37,7 @@ static inline int cold_reset_detected(void) static inline void distinguish_cpu_resets(unsigned nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect; diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c index c96e898..8824550 100644 --- a/src/southbridge/amd/amd8111/reset.c +++ b/src/southbridge/amd/amd8111/reset.c @@ -10,9 +10,7 @@ #define PCI_ID(VENDOR_ID, DEVICE_ID) \ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF)) -typedef unsigned device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value) { unsigned addr; addr = (dev>>4) | where; @@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value) outb(value, 0xCFC + (addr & 3)); } -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; @@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where) } #define PCI_DEV_INVALID (0xffffffffU) -static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + pci_devfn_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); for(; dev <= last; dev += PCI_DEV(0,0,1)) { @@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) void hard_reset(void) { - device_t dev; + pci_devfn_t dev; unsigned bus; unsigned node = 0; unsigned link = get_sblk(); diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c index 51ba6ec..b34cc86 100644 --- a/src/southbridge/broadcom/bcm5785/reset.c +++ b/src/southbridge/broadcom/bcm5785/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c index a241966..53c0c40 100644 --- a/src/southbridge/nvidia/ck804/reset.c +++ b/src/southbridge/nvidia/ck804/reset.c @@ -26,9 +26,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev >> 4) | where; @@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev >> 4) | where; diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/nvidia/mcp55/reset.c +++ b/src/southbridge/nvidia/mcp55/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where; diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c index 0ec926f..520d836 100644 --- a/src/southbridge/sis/sis966/reset.c +++ b/src/southbridge/sis/sis966/reset.c @@ -29,9 +29,7 @@ (((DEV) & 0x1F) << 15) | \ (((FN) & 0x7) << 12)) -typedef unsigned device_t; - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) +static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value) { unsigned addr; addr = (dev>>4) | where; @@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value) outl(value, 0xCFC); } -static unsigned pci_read_config32(device_t dev, unsigned where) +static unsigned pci_read_config32(pci_devfn_t dev, unsigned where) { unsigned addr; addr = (dev>>4) | where;
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Patch set updated for coreboot: 08a7daa soc: Don't hide pointers behind typedefs
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7277
-gerrit commit 08a7daaa82d01b479251f2afabe1540cac3f6e98 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 28 23:00:45 2014 +1100 soc: Don't hide pointers behind typedefs Change-Id: I05bb3b09cd1059cf43905a310f5c1ba04ed32336 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/baytrail/chip.c | 8 +++---- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/baytrail/ehci.c | 4 ++-- src/soc/intel/baytrail/emmc.c | 2 +- src/soc/intel/baytrail/gfx.c | 14 +++++------ src/soc/intel/baytrail/hda.c | 2 +- src/soc/intel/baytrail/lpe.c | 12 +++++----- src/soc/intel/baytrail/lpss.c | 10 ++++---- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pcie.c | 14 +++++------ src/soc/intel/baytrail/pmutil.c | 8 +++---- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/sata.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- src/soc/intel/baytrail/sd.c | 2 +- src/soc/intel/baytrail/smihandler.c | 2 +- src/soc/intel/baytrail/southcluster.c | 24 +++++++++---------- src/soc/intel/baytrail/spi.c | 6 ++--- src/soc/intel/baytrail/xhci.c | 6 ++--- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/broadwell/me.h | 2 +- src/soc/intel/broadwell/broadwell/pch.h | 2 +- src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++-- src/soc/intel/broadwell/broadwell/xhci.h | 2 +- src/soc/intel/broadwell/chip.c | 8 +++---- src/soc/intel/broadwell/cpu.c | 6 ++--- src/soc/intel/broadwell/ehci.c | 2 +- src/soc/intel/broadwell/lpc.c | 18 +++++++-------- src/soc/intel/broadwell/me.c | 24 +++++++++---------- src/soc/intel/broadwell/pch.c | 6 ++--- src/soc/intel/broadwell/pcie.c | 32 +++++++++++++------------- src/soc/intel/broadwell/romstage/uart.c | 2 +- src/soc/intel/broadwell/sata.c | 2 +- src/soc/intel/broadwell/smbus.c | 8 +++---- src/soc/intel/broadwell/smihandler.c | 2 +- src/soc/intel/broadwell/smmrelocate.c | 6 ++--- src/soc/intel/broadwell/spi.c | 2 +- src/soc/intel/broadwell/systemagent.c | 22 +++++++++--------- src/soc/intel/broadwell/xhci.c | 8 +++---- src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/fsp_baytrail/chip.c | 10 ++++---- src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/northcluster.c | 8 +++---- src/soc/intel/fsp_baytrail/pmutil.c | 4 ++-- src/soc/intel/fsp_baytrail/ramstage.c | 2 +- src/soc/intel/fsp_baytrail/smihandler.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++----------- src/soc/intel/fsp_baytrail/spi.c | 6 ++--- src/soc/nvidia/tegra/dc.h | 2 +- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra124/soc.c | 8 +++---- src/soc/samsung/exynos5250/cpu.c | 10 ++++---- src/soc/samsung/exynos5420/cpu.c | 10 ++++---- 55 files changed, 197 insertions(+), 197 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index a8b5fdc..4a7b536 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -26,16 +26,16 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); +void southcluster_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index ce9eb49..1a478dc 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -26,7 +26,7 @@ #include <baytrail/ramstage.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -40,7 +40,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, @@ -51,7 +51,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -79,7 +79,7 @@ struct chip_operations soc_intel_baytrail_ops = { .init = soc_init, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e8f95ae..a5106dd 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -78,7 +78,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -121,7 +121,7 @@ void baytrail_init_cpus(device_t dev) restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d8..accfed2 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = { REG_SCRIPT_END }; -static void usb2_phy_init(device_t dev) +static void usb2_phy_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { @@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev) reg_script_run(usb2_phy_script); } -static void ehci_init(device_t dev) +static void ehci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ehci_hc_init[] = { diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index f88614b..74bdb4b 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = { REG_SCRIPT_END, }; -static void emmc_init(device_t dev) +static void emmc_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 9d4768f..a47152d 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -38,7 +38,7 @@ * Lock Power Context Base Register to point to a 24KB block * of memory in GSM. Power context save data is stored here. */ -static void gfx_lock_pcbase(device_t dev) +static void gfx_lock_pcbase(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, @@ -263,18 +263,18 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } -static void gfx_pre_vbios_init(device_t dev) +static void gfx_pre_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) +static void gfx_pm_init(struct device *dev) { printk(BIOS_INFO, "GFX: Power Management Init\n"); gfx_run_script(dev, gfx_init_script); @@ -283,13 +283,13 @@ static void gfx_pm_init(device_t dev) gfx_lock_pcbase(dev); } -static void gfx_post_vbios_init(device_t dev) +static void gfx_post_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void gfx_panel_setup(device_t dev) +static void gfx_panel_setup(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { @@ -340,7 +340,7 @@ static void gfx_panel_setup(device_t dev) } } -static void gfx_init(device_t dev) +static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654..5733b95 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = { 0x20671f58, }; -static void hda_init(device_t dev) +static void hda_init(struct device *dev) { struct resource *res; int codec_mask; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42b..b6fb7c2 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -45,7 +45,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) { struct resource *res; @@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index) *field = res->base; } -static void lpe_enable_acpi_mode(device_t dev) +static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev) reg_script_run_on_dev(dev, ops); } -static void setup_codec_clock(device_t dev) +static void setup_codec_clock(struct device *dev) { uint32_t reg; int clk_reg; @@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev) write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } -static void lpe_stash_firmware_info(device_t dev) +static void lpe_stash_firmware_info(struct device *dev) { struct resource *res; struct resource *mmio; @@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev) } } -static void lpe_init(device_t dev) +static void lpe_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -161,7 +161,7 @@ static void lpe_init(device_t dev) lpe_enable_acpi_mode(dev); } -static void lpe_read_resources(device_t dev) +static void lpe_read_resources(struct device *dev) { pci_dev_read_resources(dev); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 3ee648a..c548370 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -33,7 +33,7 @@ #include "chip.h" -static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) { struct reg_script ops[] = { REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, @@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } -static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; @@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) } } -static void i2c_disable_resets(device_t dev) +static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ static const struct reg_script ops[] = { @@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev) } } -static void lpss_init(device_t dev) +static void lpss_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; int iosf_reg, nvs_index; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b119e24..2d4f20b 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 4498f43..e530498 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -34,12 +34,12 @@ static int pll_en_off; static uint32_t strpfusecfg; -static inline int root_port_offset(device_t dev) +static inline int root_port_offset(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn); } -static inline int is_first_port(device_t dev) +static inline int is_first_port(struct device *dev) { return root_port_offset(dev) == PCIE_PORT1_FUNC; } @@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void byt_pcie_init(struct device *dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), @@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = { REG_SCRIPT_END, }; -static void check_port_enabled(device_t dev) +static void check_port_enabled(struct device *dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; @@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev) } } -static void check_device_present(device_t dev) +static void check_device_present(struct device *dev) { /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -172,7 +172,7 @@ static void check_device_present(device_t dev) } } -static void byt_pcie_enable(device_t dev) +static void byt_pcie_enable(struct device *dev) { if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did) { uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee3726..935253c 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -28,9 +28,9 @@ #if defined(__SMM__) -static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline device_t get_pcu_dev(void) +static inline pci_devfn_t get_pcu_dev(void) { return pcu_dev; } @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..10f7ff2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -78,7 +78,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 28a2f8c..3c69985 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -159,7 +159,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { config_t *config = dev->chip_info; u8 reg8; diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..e2bd1dd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -87,7 +87,7 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 97c8628..6068e61 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -34,7 +34,7 @@ #define CAP_OVERRIDE_HIGH 0xa4 # define USE_CAP_OVERRIDES (1 << 31) -static void sd_init(device_t dev) +static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 22b60c4..94e6d81 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 500a13d..d3d284d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -43,12 +43,12 @@ #include "chip.h" static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; @@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -154,7 +154,7 @@ static void sc_rtc_init(void) * or configuration. This is definitely a hack, but it helps the kernel * along. */ -static void com1_configure_resume(device_t dev) +static void com1_configure_resume(struct device *dev) { const uint16_t port = 0x3f8; @@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev) outb(3, port + UART8250_LCR); } -static void sc_init(device_t dev) +static void sc_init(struct device *dev) { int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; @@ -224,7 +224,7 @@ static void sc_init(device_t dev) */ /* Set bit in function disble register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -362,7 +362,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8677b61..112b878 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -290,13 +290,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is stage dependent typed */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..3f3ed91 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = { }; /* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) +static void xhci_reset_port_usb3(struct device *dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ @@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port) } /* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) +static void xhci_route_all(struct device *dev) { static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ @@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev) } } -static void xhci_init(device_t dev) +static void xhci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index f4cac7b..3259308 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package) static int generate_C_state_entries(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; acpi_cstate_t map[3]; int *set; diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h index ddecaf8..f3021ee 100644 --- a/src/soc/intel/broadwell/broadwell/me.h +++ b/src/soc/intel/broadwell/broadwell/me.h @@ -465,7 +465,7 @@ typedef struct { } __attribute__ ((packed)) mbp_plat_time; typedef struct { - u32 device_type : 2; + u32 struct device *ype : 2; u32 reserved : 30; } __attribute__ ((packed)) mbp_nfc_data; diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index e677215..c58b695 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -47,6 +47,6 @@ int pch_is_wpt(void); int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_log_state(void); -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h index 685de14..d66e8cc 100644 --- a/src/soc/intel/broadwell/broadwell/ramstage.h +++ b/src/soc/intel/broadwell/broadwell/ramstage.h @@ -24,8 +24,8 @@ #include <chip.h> void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(device_t dev); -void broadwell_pch_enable_dev(device_t dev); +void broadwell_init_cpus(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h index 3f4fb4e..a5536fc 100644 --- a/src/soc/intel/broadwell/broadwell/xhci.h +++ b/src/soc/intel/broadwell/broadwell/xhci.h @@ -55,7 +55,7 @@ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ #ifdef __SMM__ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ); #endif #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 94f7893..e2ab17c 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -24,7 +24,7 @@ #include <broadwell/ramstage.h> #include <chip.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -36,7 +36,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_ops_mmconf, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = &cpu_bus_noop, @@ -45,7 +45,7 @@ static struct device_operations cpu_bus_ops = { .init = &broadwell_init_cpus, }; -static void broadwell_enable(device_t dev) +static void broadwell_enable(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -67,7 +67,7 @@ struct chip_operations soc_intel_broadwell_ops = { .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 58f81fc..416fe3c 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -444,7 +444,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; msr_t msr; @@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void cpu_core_init(device_t cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void broadwell_init_cpus(device_t dev) +void broadwell_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; int num_threads; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index a59d3c8..30f4acd 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -28,7 +28,7 @@ #include <broadwell/ehci.h> #include <broadwell/pch.h> -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { u8 access_cntl; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 4b21326..270316c 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -89,9 +89,9 @@ static void pch_enable_ioapic(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); @@ -126,7 +126,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u16 reg16; const char *state; @@ -325,7 +325,7 @@ static void pch_pm_init(struct device *dev) RCBA32_OR(0x3a6c, 0x00000001); } -static void pch_cg_init(device_t dev) +static void pch_cg_init(struct device *dev) { u32 reg32; u16 reg16; @@ -420,7 +420,7 @@ static void lpc_init(struct device *dev) pch_set_acpi_mode(); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -482,7 +482,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -495,7 +495,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -508,7 +508,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -533,7 +533,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 15bcc34..19bc754 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,11 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); /* MMIO base address for MEI interface */ static u32 mei_base_address; -void intel_me_mbp_clear(device_t dev); +void intel_me_mbp_clear(struct device *dev); #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -440,7 +440,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc, * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +static void intel_me_mbp_give_up(struct device *dev) { struct mei_csr csr; @@ -456,7 +456,7 @@ static void intel_me_mbp_give_up(device_t dev) * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +void intel_me_mbp_clear(struct device *dev) { int count; struct me_hfs2 hfs2; @@ -568,7 +568,7 @@ static int mkhi_end_of_post(void) void intel_me_finalize(void) { - device_t dev = PCH_DEV_ME; + struct device *dev = PCH_DEV_ME; struct me_hfs hfs; u32 reg32; @@ -629,7 +629,7 @@ static int me_icc_set_clock_enables(u32 mask) } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -699,7 +699,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -729,7 +729,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -776,7 +776,7 @@ static int intel_me_extend_valid(device_t dev) } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { config_t *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -829,7 +829,7 @@ static void intel_me_init(device_t dev) */ } -static void intel_me_enable(device_t dev) +static void intel_me_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ @@ -882,7 +882,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 82390a4..e681620 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id) #ifndef __PRE_RAM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ @@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev) } } -void broadwell_pch_enable_dev(device_t dev) +void broadwell_pch_enable_dev(struct device *dev) { u32 reg32; diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index a407f3c..08e4863 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -32,8 +32,8 @@ #include <broadwell/rcba.h> #include <chip.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or); +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or); /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -52,23 +52,23 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - device_t ports[NUM_ROOT_PORTS]; + struct device *ports[NUM_ROOT_PORTS]; }; static struct root_port_config rpc; -static inline int root_port_is_first(device_t dev) +static inline int root_port_is_first(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == 0; } -static inline int root_port_is_last(device_t dev) +static inline int root_port_is_last(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); } /* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(device_t dev) +static inline int root_port_number(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) + 1; } @@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void) } } -static void root_port_init_config(device_t dev) +static void root_port_init_config(struct device *dev) { int rp; @@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_device_set_func(int index, int pci_func) { - device_t dev; + struct device *dev; unsigned new_devfn; dev = rpc.ports[index]; @@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void) int enabled_ports = 0; for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; int rp; dev = rpc.ports[i]; @@ -244,7 +244,7 @@ static void root_port_commit_config(void) pcie_enable_clock_gating(); for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; u32 reg32; dev = rpc.ports[i]; @@ -297,7 +297,7 @@ static void root_port_commit_config(void) RCBA32(RPFN) = rpc.new_rpfn; } -static void root_port_mark_disable(device_t dev) +static void root_port_mark_disable(struct device *dev) { /* Mark device as disabled. */ dev->enabled = 0; @@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev) rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); } -static void root_port_check_disable(device_t dev) +static void root_port_check_disable(struct device *dev) { int rp; @@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or) { u32 reg32; @@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); } -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { /* Add this device to the root port config structure. */ root_port_init_config(dev); @@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev) root_port_commit_config(); } -static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 8214a8a..2517fef 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -52,7 +52,7 @@ void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; + struct device *dev; /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e8d1fbe..24a8ebe 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -221,7 +221,7 @@ static void sata_init(struct device *dev) * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index a1dbdfe..c214510 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -31,7 +31,7 @@ #include <broadwell/ramstage.h> #include <broadwell/smbus.h> -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; u16 reg16; @@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev) outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_BASE_ADDRESS; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 6acd07c..49cf774 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index bd1fc26..9ba6a00 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; int num_cpus; msr_t msr; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 353323a..6095cf7 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -286,7 +286,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev = PCH_DEV_LPC; + struct device *dev = PCH_DEV_LPC; ich9_spi_regs *ich9_spi; pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 787a62b..c1110ab 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -37,7 +37,7 @@ #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -184,7 +184,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev) chromeos_reserve_ram_oops(dev, index++); } -static void systemagent_read_resources(device_t dev) +static void systemagent_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) +static void systemagent_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 89e1139..9530422 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -27,7 +27,7 @@ #include <broadwell/xhci.h> #ifdef __SMM__ -static u32 usb_xhci_mem_base(device_t dev) +static u32 usb_xhci_mem_base(struct device *dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(struct device *dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(struct device *dev, int all) { u32 status, port_disabled; int timeout, port; @@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ) { u16 reg16; u32 reg32; diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h index d3a2377..d991d34 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -57,7 +57,7 @@ void rangeley_early_initialization(void); int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(device_t dev); +void soc_enable(struct device *dev); /* debugging functions */ void print_pci_devices(void); diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h index 095f09c..c1114df 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h @@ -25,10 +25,10 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void southcluster_enable_dev(struct device *dev); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 839e8dc..e8f8ef4 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -25,12 +25,12 @@ #include <drivers/intel/fsp/fsp_util.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -50,7 +50,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, @@ -60,7 +60,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = NULL, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", dev_name(dev), dev->path.type); @@ -100,7 +100,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { .final = &finalize_chip, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 6f1e9c4..5c6375e 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev) } } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..010063e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void) static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 bmbound, bsmmrrl; int index = 0; @@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void nc_enable(device_t dev) +static void nc_enable(struct device *dev) { print_fsp_info(); } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index aee3726..6a62a34 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..55abb4d 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -76,7 +76,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index 2225964..50b6ef4 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902..307b006 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -51,12 +51,12 @@ typedef struct soc_intel_fsp_baytrail_config config_t; static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { #ifndef CONFIG_VIRTUAL_ROM_SIZE #error CONFIG_VIRTUAL_ROM_SIZE must be set. @@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -255,7 +255,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void sc_pirq_init(device_t dev) +static void sc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; u8 io_index = 0; @@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -409,7 +409,7 @@ static void sc_init(struct device *dev) */ /* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -505,7 +505,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -517,7 +517,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -534,7 +534,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -611,7 +611,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4feb502..295e203 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -288,13 +288,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is type-dependent on stage */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 48ffbda..895fd89 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -567,7 +567,7 @@ struct disp_ctl_win { u32 out_h; /* Height of output window in pixels */ }; -void display_startup(device_t dev); +void display_startup(struct device *dev); void dp_bringup(u32 winb_addr); unsigned int fb_base_mb(void); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 00dfbb6..9cc0cf0 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -234,7 +234,7 @@ uint32_t fb_base_mb(void) /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ -void display_startup(device_t dev) +void display_startup(struct device *dev) { u32 val; int i; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 11a52c4..eb8002b 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -29,7 +29,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(device_t dev) +static void soc_enable(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -39,13 +39,13 @@ static void soc_enable(device_t dev) mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); } -static void soc_init(device_t dev) +static void soc_init(struct device *dev) { display_startup(dev); printk(BIOS_INFO, "CPU: Tegra124\n"); } -static void soc_noop(device_t dev) +static void soc_noop(struct device *dev) { } @@ -57,7 +57,7 @@ static struct device_operations soc_ops = { .scan_bus = 0, }; -static void enable_tegra124_dev(device_t dev) +static void enable_tegra124_dev(struct device *dev) { dev->ops = &soc_ops; } diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index b8b88d7..c4561f6 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -59,7 +59,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5250_config *conf = dev->chip_info; @@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -123,13 +123,13 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -141,7 +141,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5250_dev(device_t dev) +static void enable_exynos5250_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 506b676..b646f82 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -73,7 +73,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5420_config *conf = dev->chip_info; @@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index) } } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -154,13 +154,13 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / 1000000); } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -172,7 +172,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5420_dev(device_t dev) +static void enable_exynos5420_dev(struct device *dev) { dev->ops = &cpu_ops; }
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Patch set updated for coreboot: 2c6c84b soc: Don't hide pointers behind typedefs
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7277
-gerrit commit 2c6c84bbddc1d20d2dfb28a4f920211a379f11e4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 28 23:00:45 2014 +1100 soc: Don't hide pointers behind typedefs Change-Id: I05bb3b09cd1059cf43905a310f5c1ba04ed32336 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/baytrail/chip.c | 8 +++---- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/baytrail/ehci.c | 4 ++-- src/soc/intel/baytrail/emmc.c | 2 +- src/soc/intel/baytrail/gfx.c | 14 +++++------ src/soc/intel/baytrail/hda.c | 2 +- src/soc/intel/baytrail/lpe.c | 12 +++++----- src/soc/intel/baytrail/lpss.c | 10 ++++---- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pcie.c | 14 +++++------ src/soc/intel/baytrail/pmutil.c | 8 +++---- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/sata.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- src/soc/intel/baytrail/sd.c | 2 +- src/soc/intel/baytrail/smihandler.c | 2 +- src/soc/intel/baytrail/southcluster.c | 24 +++++++++---------- src/soc/intel/baytrail/spi.c | 2 +- src/soc/intel/baytrail/xhci.c | 6 ++--- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/broadwell/me.h | 2 +- src/soc/intel/broadwell/broadwell/pch.h | 2 +- src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++-- src/soc/intel/broadwell/broadwell/xhci.h | 2 +- src/soc/intel/broadwell/chip.c | 8 +++---- src/soc/intel/broadwell/cpu.c | 6 ++--- src/soc/intel/broadwell/ehci.c | 2 +- src/soc/intel/broadwell/lpc.c | 18 +++++++-------- src/soc/intel/broadwell/me.c | 24 +++++++++---------- src/soc/intel/broadwell/pch.c | 6 ++--- src/soc/intel/broadwell/pcie.c | 32 +++++++++++++------------- src/soc/intel/broadwell/romstage/uart.c | 2 +- src/soc/intel/broadwell/sata.c | 2 +- src/soc/intel/broadwell/smbus.c | 8 +++---- src/soc/intel/broadwell/smihandler.c | 2 +- src/soc/intel/broadwell/smmrelocate.c | 6 ++--- src/soc/intel/broadwell/spi.c | 2 +- src/soc/intel/broadwell/systemagent.c | 22 +++++++++--------- src/soc/intel/broadwell/xhci.c | 8 +++---- src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/fsp_baytrail/chip.c | 10 ++++---- src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/northcluster.c | 8 +++---- src/soc/intel/fsp_baytrail/pmutil.c | 4 ++-- src/soc/intel/fsp_baytrail/ramstage.c | 2 +- src/soc/intel/fsp_baytrail/smihandler.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++----------- src/soc/intel/fsp_baytrail/spi.c | 6 ++--- src/soc/nvidia/tegra/dc.h | 2 +- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra124/soc.c | 8 +++---- src/soc/samsung/exynos5250/cpu.c | 10 ++++---- src/soc/samsung/exynos5420/cpu.c | 10 ++++---- 55 files changed, 195 insertions(+), 195 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index a8b5fdc..4a7b536 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -26,16 +26,16 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); +void southcluster_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index ce9eb49..1a478dc 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -26,7 +26,7 @@ #include <baytrail/ramstage.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -40,7 +40,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, @@ -51,7 +51,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -79,7 +79,7 @@ struct chip_operations soc_intel_baytrail_ops = { .init = soc_init, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e8f95ae..a5106dd 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -78,7 +78,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -121,7 +121,7 @@ void baytrail_init_cpus(device_t dev) restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d8..accfed2 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = { REG_SCRIPT_END }; -static void usb2_phy_init(device_t dev) +static void usb2_phy_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { @@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev) reg_script_run(usb2_phy_script); } -static void ehci_init(device_t dev) +static void ehci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ehci_hc_init[] = { diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index f88614b..74bdb4b 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = { REG_SCRIPT_END, }; -static void emmc_init(device_t dev) +static void emmc_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 9d4768f..a47152d 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -38,7 +38,7 @@ * Lock Power Context Base Register to point to a 24KB block * of memory in GSM. Power context save data is stored here. */ -static void gfx_lock_pcbase(device_t dev) +static void gfx_lock_pcbase(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, @@ -263,18 +263,18 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } -static void gfx_pre_vbios_init(device_t dev) +static void gfx_pre_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) +static void gfx_pm_init(struct device *dev) { printk(BIOS_INFO, "GFX: Power Management Init\n"); gfx_run_script(dev, gfx_init_script); @@ -283,13 +283,13 @@ static void gfx_pm_init(device_t dev) gfx_lock_pcbase(dev); } -static void gfx_post_vbios_init(device_t dev) +static void gfx_post_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void gfx_panel_setup(device_t dev) +static void gfx_panel_setup(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { @@ -340,7 +340,7 @@ static void gfx_panel_setup(device_t dev) } } -static void gfx_init(device_t dev) +static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654..5733b95 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = { 0x20671f58, }; -static void hda_init(device_t dev) +static void hda_init(struct device *dev) { struct resource *res; int codec_mask; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42b..b6fb7c2 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -45,7 +45,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) { struct resource *res; @@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index) *field = res->base; } -static void lpe_enable_acpi_mode(device_t dev) +static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev) reg_script_run_on_dev(dev, ops); } -static void setup_codec_clock(device_t dev) +static void setup_codec_clock(struct device *dev) { uint32_t reg; int clk_reg; @@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev) write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } -static void lpe_stash_firmware_info(device_t dev) +static void lpe_stash_firmware_info(struct device *dev) { struct resource *res; struct resource *mmio; @@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev) } } -static void lpe_init(device_t dev) +static void lpe_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -161,7 +161,7 @@ static void lpe_init(device_t dev) lpe_enable_acpi_mode(dev); } -static void lpe_read_resources(device_t dev) +static void lpe_read_resources(struct device *dev) { pci_dev_read_resources(dev); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 3ee648a..c548370 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -33,7 +33,7 @@ #include "chip.h" -static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) { struct reg_script ops[] = { REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, @@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } -static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; @@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) } } -static void i2c_disable_resets(device_t dev) +static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ static const struct reg_script ops[] = { @@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev) } } -static void lpss_init(device_t dev) +static void lpss_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; int iosf_reg, nvs_index; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b119e24..2d4f20b 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 4498f43..e530498 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -34,12 +34,12 @@ static int pll_en_off; static uint32_t strpfusecfg; -static inline int root_port_offset(device_t dev) +static inline int root_port_offset(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn); } -static inline int is_first_port(device_t dev) +static inline int is_first_port(struct device *dev) { return root_port_offset(dev) == PCIE_PORT1_FUNC; } @@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void byt_pcie_init(struct device *dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), @@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = { REG_SCRIPT_END, }; -static void check_port_enabled(device_t dev) +static void check_port_enabled(struct device *dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; @@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev) } } -static void check_device_present(device_t dev) +static void check_device_present(struct device *dev) { /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -172,7 +172,7 @@ static void check_device_present(device_t dev) } } -static void byt_pcie_enable(device_t dev) +static void byt_pcie_enable(struct device *dev) { if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did) { uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee3726..935253c 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -28,9 +28,9 @@ #if defined(__SMM__) -static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline device_t get_pcu_dev(void) +static inline pci_devfn_t get_pcu_dev(void) { return pcu_dev; } @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..10f7ff2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -78,7 +78,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 28a2f8c..3c69985 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -159,7 +159,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { config_t *config = dev->chip_info; u8 reg8; diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..e2bd1dd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -87,7 +87,7 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 97c8628..6068e61 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -34,7 +34,7 @@ #define CAP_OVERRIDE_HIGH 0xa4 # define USE_CAP_OVERRIDES (1 << 31) -static void sd_init(device_t dev) +static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 22b60c4..94e6d81 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 500a13d..d3d284d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -43,12 +43,12 @@ #include "chip.h" static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; @@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -154,7 +154,7 @@ static void sc_rtc_init(void) * or configuration. This is definitely a hack, but it helps the kernel * along. */ -static void com1_configure_resume(device_t dev) +static void com1_configure_resume(struct device *dev) { const uint16_t port = 0x3f8; @@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev) outb(3, port + UART8250_LCR); } -static void sc_init(device_t dev) +static void sc_init(struct device *dev) { int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; @@ -224,7 +224,7 @@ static void sc_init(device_t dev) */ /* Set bit in function disble register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -362,7 +362,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8677b61..4de3d91 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -290,7 +290,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; + struct device *dev; uint32_t sbase; #ifdef __SMM__ diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..3f3ed91 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = { }; /* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) +static void xhci_reset_port_usb3(struct device *dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ @@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port) } /* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) +static void xhci_route_all(struct device *dev) { static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ @@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev) } } -static void xhci_init(device_t dev) +static void xhci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index f4cac7b..3259308 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package) static int generate_C_state_entries(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; acpi_cstate_t map[3]; int *set; diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h index ddecaf8..f3021ee 100644 --- a/src/soc/intel/broadwell/broadwell/me.h +++ b/src/soc/intel/broadwell/broadwell/me.h @@ -465,7 +465,7 @@ typedef struct { } __attribute__ ((packed)) mbp_plat_time; typedef struct { - u32 device_type : 2; + u32 struct device *ype : 2; u32 reserved : 30; } __attribute__ ((packed)) mbp_nfc_data; diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index e677215..c58b695 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -47,6 +47,6 @@ int pch_is_wpt(void); int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_log_state(void); -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h index 685de14..d66e8cc 100644 --- a/src/soc/intel/broadwell/broadwell/ramstage.h +++ b/src/soc/intel/broadwell/broadwell/ramstage.h @@ -24,8 +24,8 @@ #include <chip.h> void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(device_t dev); -void broadwell_pch_enable_dev(device_t dev); +void broadwell_init_cpus(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h index 3f4fb4e..a5536fc 100644 --- a/src/soc/intel/broadwell/broadwell/xhci.h +++ b/src/soc/intel/broadwell/broadwell/xhci.h @@ -55,7 +55,7 @@ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ #ifdef __SMM__ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ); #endif #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 94f7893..e2ab17c 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -24,7 +24,7 @@ #include <broadwell/ramstage.h> #include <chip.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -36,7 +36,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_ops_mmconf, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = &cpu_bus_noop, @@ -45,7 +45,7 @@ static struct device_operations cpu_bus_ops = { .init = &broadwell_init_cpus, }; -static void broadwell_enable(device_t dev) +static void broadwell_enable(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -67,7 +67,7 @@ struct chip_operations soc_intel_broadwell_ops = { .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 58f81fc..416fe3c 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -444,7 +444,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; msr_t msr; @@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void cpu_core_init(device_t cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void broadwell_init_cpus(device_t dev) +void broadwell_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; int num_threads; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index a59d3c8..30f4acd 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -28,7 +28,7 @@ #include <broadwell/ehci.h> #include <broadwell/pch.h> -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { u8 access_cntl; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 4b21326..270316c 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -89,9 +89,9 @@ static void pch_enable_ioapic(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); @@ -126,7 +126,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u16 reg16; const char *state; @@ -325,7 +325,7 @@ static void pch_pm_init(struct device *dev) RCBA32_OR(0x3a6c, 0x00000001); } -static void pch_cg_init(device_t dev) +static void pch_cg_init(struct device *dev) { u32 reg32; u16 reg16; @@ -420,7 +420,7 @@ static void lpc_init(struct device *dev) pch_set_acpi_mode(); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -482,7 +482,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -495,7 +495,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -508,7 +508,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -533,7 +533,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 15bcc34..19bc754 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,11 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); /* MMIO base address for MEI interface */ static u32 mei_base_address; -void intel_me_mbp_clear(device_t dev); +void intel_me_mbp_clear(struct device *dev); #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -440,7 +440,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc, * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +static void intel_me_mbp_give_up(struct device *dev) { struct mei_csr csr; @@ -456,7 +456,7 @@ static void intel_me_mbp_give_up(device_t dev) * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +void intel_me_mbp_clear(struct device *dev) { int count; struct me_hfs2 hfs2; @@ -568,7 +568,7 @@ static int mkhi_end_of_post(void) void intel_me_finalize(void) { - device_t dev = PCH_DEV_ME; + struct device *dev = PCH_DEV_ME; struct me_hfs hfs; u32 reg32; @@ -629,7 +629,7 @@ static int me_icc_set_clock_enables(u32 mask) } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -699,7 +699,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -729,7 +729,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -776,7 +776,7 @@ static int intel_me_extend_valid(device_t dev) } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { config_t *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -829,7 +829,7 @@ static void intel_me_init(device_t dev) */ } -static void intel_me_enable(device_t dev) +static void intel_me_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ @@ -882,7 +882,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 82390a4..e681620 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id) #ifndef __PRE_RAM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ @@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev) } } -void broadwell_pch_enable_dev(device_t dev) +void broadwell_pch_enable_dev(struct device *dev) { u32 reg32; diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index a407f3c..08e4863 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -32,8 +32,8 @@ #include <broadwell/rcba.h> #include <chip.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or); +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or); /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -52,23 +52,23 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - device_t ports[NUM_ROOT_PORTS]; + struct device *ports[NUM_ROOT_PORTS]; }; static struct root_port_config rpc; -static inline int root_port_is_first(device_t dev) +static inline int root_port_is_first(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == 0; } -static inline int root_port_is_last(device_t dev) +static inline int root_port_is_last(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); } /* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(device_t dev) +static inline int root_port_number(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) + 1; } @@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void) } } -static void root_port_init_config(device_t dev) +static void root_port_init_config(struct device *dev) { int rp; @@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_device_set_func(int index, int pci_func) { - device_t dev; + struct device *dev; unsigned new_devfn; dev = rpc.ports[index]; @@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void) int enabled_ports = 0; for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; int rp; dev = rpc.ports[i]; @@ -244,7 +244,7 @@ static void root_port_commit_config(void) pcie_enable_clock_gating(); for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; u32 reg32; dev = rpc.ports[i]; @@ -297,7 +297,7 @@ static void root_port_commit_config(void) RCBA32(RPFN) = rpc.new_rpfn; } -static void root_port_mark_disable(device_t dev) +static void root_port_mark_disable(struct device *dev) { /* Mark device as disabled. */ dev->enabled = 0; @@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev) rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); } -static void root_port_check_disable(device_t dev) +static void root_port_check_disable(struct device *dev) { int rp; @@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or) { u32 reg32; @@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); } -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { /* Add this device to the root port config structure. */ root_port_init_config(dev); @@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev) root_port_commit_config(); } -static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 8214a8a..2517fef 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -52,7 +52,7 @@ void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; + struct device *dev; /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e8d1fbe..24a8ebe 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -221,7 +221,7 @@ static void sata_init(struct device *dev) * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index a1dbdfe..c214510 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -31,7 +31,7 @@ #include <broadwell/ramstage.h> #include <broadwell/smbus.h> -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; u16 reg16; @@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev) outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_BASE_ADDRESS; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 6acd07c..49cf774 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index bd1fc26..9ba6a00 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; int num_cpus; msr_t msr; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 353323a..6095cf7 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -286,7 +286,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev = PCH_DEV_LPC; + struct device *dev = PCH_DEV_LPC; ich9_spi_regs *ich9_spi; pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 787a62b..c1110ab 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -37,7 +37,7 @@ #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -184,7 +184,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev) chromeos_reserve_ram_oops(dev, index++); } -static void systemagent_read_resources(device_t dev) +static void systemagent_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) +static void systemagent_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 89e1139..9530422 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -27,7 +27,7 @@ #include <broadwell/xhci.h> #ifdef __SMM__ -static u32 usb_xhci_mem_base(device_t dev) +static u32 usb_xhci_mem_base(struct device *dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(struct device *dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(struct device *dev, int all) { u32 status, port_disabled; int timeout, port; @@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ) { u16 reg16; u32 reg32; diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h index d3a2377..d991d34 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -57,7 +57,7 @@ void rangeley_early_initialization(void); int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(device_t dev); +void soc_enable(struct device *dev); /* debugging functions */ void print_pci_devices(void); diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h index 095f09c..c1114df 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h @@ -25,10 +25,10 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void southcluster_enable_dev(struct device *dev); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 839e8dc..e8f8ef4 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -25,12 +25,12 @@ #include <drivers/intel/fsp/fsp_util.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -50,7 +50,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, @@ -60,7 +60,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = NULL, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", dev_name(dev), dev->path.type); @@ -100,7 +100,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { .final = &finalize_chip, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 6f1e9c4..5c6375e 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev) } } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..010063e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void) static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 bmbound, bsmmrrl; int index = 0; @@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void nc_enable(device_t dev) +static void nc_enable(struct device *dev) { print_fsp_info(); } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index aee3726..6a62a34 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..55abb4d 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -76,7 +76,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index 2225964..50b6ef4 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902..307b006 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -51,12 +51,12 @@ typedef struct soc_intel_fsp_baytrail_config config_t; static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { #ifndef CONFIG_VIRTUAL_ROM_SIZE #error CONFIG_VIRTUAL_ROM_SIZE must be set. @@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -255,7 +255,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void sc_pirq_init(device_t dev) +static void sc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; u8 io_index = 0; @@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -409,7 +409,7 @@ static void sc_init(struct device *dev) */ /* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -505,7 +505,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -517,7 +517,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -534,7 +534,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -611,7 +611,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4feb502..295e203 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -288,13 +288,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is type-dependent on stage */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 48ffbda..895fd89 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -567,7 +567,7 @@ struct disp_ctl_win { u32 out_h; /* Height of output window in pixels */ }; -void display_startup(device_t dev); +void display_startup(struct device *dev); void dp_bringup(u32 winb_addr); unsigned int fb_base_mb(void); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 00dfbb6..9cc0cf0 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -234,7 +234,7 @@ uint32_t fb_base_mb(void) /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ -void display_startup(device_t dev) +void display_startup(struct device *dev) { u32 val; int i; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 11a52c4..eb8002b 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -29,7 +29,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(device_t dev) +static void soc_enable(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -39,13 +39,13 @@ static void soc_enable(device_t dev) mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); } -static void soc_init(device_t dev) +static void soc_init(struct device *dev) { display_startup(dev); printk(BIOS_INFO, "CPU: Tegra124\n"); } -static void soc_noop(device_t dev) +static void soc_noop(struct device *dev) { } @@ -57,7 +57,7 @@ static struct device_operations soc_ops = { .scan_bus = 0, }; -static void enable_tegra124_dev(device_t dev) +static void enable_tegra124_dev(struct device *dev) { dev->ops = &soc_ops; } diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index b8b88d7..c4561f6 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -59,7 +59,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5250_config *conf = dev->chip_info; @@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -123,13 +123,13 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -141,7 +141,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5250_dev(device_t dev) +static void enable_exynos5250_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 506b676..b646f82 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -73,7 +73,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5420_config *conf = dev->chip_info; @@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index) } } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -154,13 +154,13 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / 1000000); } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -172,7 +172,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5420_dev(device_t dev) +static void enable_exynos5420_dev(struct device *dev) { dev->ops = &cpu_ops; }
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Patch set updated for coreboot: e56a233 TEST
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7198
-gerrit commit e56a233980e97ca2075c11ec534d3ab1ffee04f8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Oct 26 23:33:22 2014 +1100 TEST Change-Id: I6f29b198569eb4834328d36ca8f69d6550ded4cf Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/agesa/00730F01/model_16_init.c | 2 +- src/cpu/amd/agesa/amd_late_init.c | 2 +- src/cpu/amd/agesa/family10/model_10_init.c | 2 +- src/cpu/amd/agesa/family12/model_12_init.c | 2 +- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15/model_15_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/dualcore/amd_sibling.c | 6 +++--- src/cpu/amd/geode_gx1/geode_gx1_init.c | 2 +- src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +- src/cpu/amd/geode_lx/geode_lx_init.c | 2 +- src/cpu/amd/model_10xxx/fidvid.c | 28 ++++++++++++++-------------- src/cpu/amd/model_10xxx/init_cpus.c | 2 +- src/cpu/amd/model_10xxx/model_10xxx_init.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/cpu/amd/model_fxx/model_fxx_init.c | 10 ++++++---- src/cpu/amd/quadcore/amd_sibling.c | 6 +++--- src/cpu/amd/sc520/sc520.c | 14 +++++++------- 19 files changed, 47 insertions(+), 45 deletions(-) diff --git a/src/cpu/amd/agesa/00730F01/model_16_init.c b/src/cpu/amd/agesa/00730F01/model_16_init.c index 8053fd1..78cfc06 100644 --- a/src/cpu/amd/agesa/00730F01/model_16_init.c +++ b/src/cpu/amd/agesa/00730F01/model_16_init.c @@ -37,7 +37,7 @@ #include <cpu/amd/agesa/s3_resume.h> #endif -static void model_16_init(device_t dev) +static void model_16_init(struct device *dev) { printk(BIOS_DEBUG, "Model 16 Init.\n"); diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index cab03a3..97f5425 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -42,7 +42,7 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdinitlate); #if (NORTHBRIDGE_00700F00) || (NORTHBRIDGE_00730F01) - device_t dev; + struct device *dev; u32 value; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 6fbfd1a..d00a105 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -34,7 +34,7 @@ #define MCI_STATUS 0x401 -static void model_10_init(device_t dev) +static void model_10_init(struct device *dev) { printk(BIOS_DEBUG, "Model 10 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 635bd81..a2061e7 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -35,7 +35,7 @@ #define MCI_STATUS 0x401 -static void model_12_init(device_t dev) +static void model_12_init(struct device *dev) { printk(BIOS_DEBUG, "Model 12 Init - a no-op.\n"); diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 60a88c7..ca250b9 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -36,7 +36,7 @@ #define MCI_STATUS 0x401 -static void model_14_init(device_t dev) +static void model_14_init(struct device *dev) { u32 i; msr_t msr; diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index a755e1c..c7fbd75 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -31,7 +31,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> -static void model_15_init(device_t dev) +static void model_15_init(struct device *dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 64c78af..b888cf2 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -35,7 +35,7 @@ #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -static void model_15_init(device_t dev) +static void model_15_init(struct device *dev) { printk(BIOS_DEBUG, "Model 15 Init.\n"); diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index ef31f96..07b92f5 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -34,7 +34,7 @@ #include <arch/acpi.h> #include <cpu/amd/agesa/s3_resume.h> -static void model_16_init(device_t dev) +static void model_16_init(struct device *dev) { printk(BIOS_DEBUG, "Model 16 Init.\n"); diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c index d9942de..e2ad3a1 100644 --- a/src/cpu/amd/dualcore/amd_sibling.c +++ b/src/cpu/amd/dualcore/amd_sibling.c @@ -19,7 +19,7 @@ static int disable_siblings = !CONFIG_LOGICAL_CPUS; static int get_max_siblings(int nodes) { - device_t dev; + struct device *dev; int nodeid; int siblings=0; @@ -38,7 +38,7 @@ static int get_max_siblings(int nodes) static void enable_apic_ext_id(int nodes) { - device_t dev; + struct device *dev; int nodeid; //enable APIC_EXIT_ID all the nodes @@ -54,7 +54,7 @@ static void enable_apic_ext_id(int nodes) unsigned get_apicid_base(unsigned ioapic_num) { - device_t dev; + struct device *dev; int nodes; unsigned apicid_base; int siblings; diff --git a/src/cpu/amd/geode_gx1/geode_gx1_init.c b/src/cpu/amd/geode_gx1/geode_gx1_init.c index 8fbf507..4f08a1c 100644 --- a/src/cpu/amd/geode_gx1/geode_gx1_init.c +++ b/src/cpu/amd/geode_gx1/geode_gx1_init.c @@ -72,7 +72,7 @@ unsigned long addr; } #endif -static void geode_gx1_init(device_t dev) +static void geode_gx1_init(struct device *dev) { #if 0 gx1_cpu_setup(); diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c index b8f56db..43ac808 100644 --- a/src/cpu/amd/geode_gx2/geode_gx2_init.c +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -15,7 +15,7 @@ static void vsm_end_post_smi(void) ); } -static void geode_gx2_init(device_t dev) +static void geode_gx2_init(struct device *dev) { printk(BIOS_DEBUG, "geode_gx2_init\n"); diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c index cd931a4..1024c00 100644 --- a/src/cpu/amd/geode_lx/geode_lx_init.c +++ b/src/cpu/amd/geode_lx/geode_lx_init.c @@ -37,7 +37,7 @@ static void vsm_end_post_smi(void) ".byte 0x0f, 0x38\n" "pop %ax\n"); } -static void geode_lx_init(device_t dev) +static void geode_lx_init(struct device *dev) { printk(BIOS_DEBUG, "geode_lx_init\n"); diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index 4297c90..c0be3d0 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -134,7 +134,7 @@ static void enable_fid_change(u8 fid) { u32 dword; u32 nodes; - device_t dev; + struct device *dev; int i; nodes = get_nodes(); @@ -151,7 +151,7 @@ static void enable_fid_change(u8 fid) } } -static void applyBoostFIDOffset( device_t dev ) { +static void applyBoostFIDOffset( struct device *dev ) { // BKDG 2.4.2.8 // revision E only, but E is apparently not supported yet, therefore untested if ((cpuid_edx(0x80000007) & CPB_MASK) @@ -168,7 +168,7 @@ static void applyBoostFIDOffset( device_t dev ) { } } -static void enableNbPState1( device_t dev ) { +static void enableNbPState1( struct device *dev ) { u32 cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); @@ -188,7 +188,7 @@ static void enableNbPState1( device_t dev ) { } } -static u8 setPStateMaxVal( device_t dev ) { +static u8 setPStateMaxVal( struct device *dev ) { u8 i,maxpstate=0; for (i = 0; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PS_REG_BASE + i); @@ -208,7 +208,7 @@ static u8 setPStateMaxVal( device_t dev ) { return maxpstate; } -static void dualPlaneOnly( device_t dev ) { +static void dualPlaneOnly( struct device *dev ) { // BKDG 2.4.2.7 u32 cpuRev = mctGetLogicalCPUID(0xFF); @@ -252,7 +252,7 @@ static int vidTo100uV(u8 vid) return voltage; } -static void setVSRamp(device_t dev) { +static void setVSRamp(struct device *dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] * If this field accepts 8 values between 10 and 500 us why * does page 324 say "BIOS should set this field to 001b." @@ -267,7 +267,7 @@ static void setVSRamp(device_t dev) { pci_write_config32(dev, 0xd8, dword); } -static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) +static void recalculateVsSlamTimeSettingOnCorePre(struct device *dev) { u8 pviModeFlag; u8 highVoltageVid, lowVoltageVid, bValue; @@ -443,7 +443,7 @@ static u32 power_up_down(int node, u8 procPkg) { } static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { - device_t dev = NODE_PCI(node, 3); + struct device *dev = NODE_PCI(node, 3); /* Program fields in Clock Power/Control register0 (F3xD4) */ @@ -467,7 +467,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) { } -static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { +static void config_power_ctrl_misc_reg(struct device *dev,u32 cpuRev, u8 procPkg) { /* check PVI/SVI */ u32 dword = pci_read_config32(dev, 0xA0); @@ -500,7 +500,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) { pci_write_config32(dev, 0xA0, dword); } -static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { +static void config_nb_syn_ptr_adj(struct device *dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ @@ -522,7 +522,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { pci_write_config32(dev, 0xdc, dword); } -static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { +static void config_acpi_pwr_state_ctrl_regs(struct device *dev, u32 cpuRev, u8 procPkg) { /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ u32 dword; u32 c1= 1; @@ -582,7 +582,7 @@ static void prep_fid_change(void) { u32 dword; u32 nodes; - device_t dev; + struct device *dev; int i; /* This needs to be run before any Pstate changes are requested */ @@ -785,7 +785,7 @@ static u32 needs_NB_COF_VID_update(void) static u32 init_fidvid_core(u32 nodeid, u32 coreid) { - device_t dev; + struct device *dev; u32 vid_max; u32 fid_max = 0; u8 nb_cof_vid_update = needs_NB_COF_VID_update(); @@ -946,7 +946,7 @@ static void finalPstateChange(void) static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; - device_t dev; + struct device *dev; u32 reg1fc; u32 dtemp; u32 nbvid; diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 10c0c8a..f6d2bd7 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -362,7 +362,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + struct device *device; device = NODE_PCI(nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_ColdR_Detect; diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c6cf64a..214b416 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -38,7 +38,7 @@ #define MCI_STATUS 0x401 -static void model_10xxx_init(device_t dev) +static void model_10xxx_init(struct device *dev) { u8 i; msr_t msr; diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 12d3a95..0dacc8d 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -310,7 +310,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + struct device *device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_INIT_Detect; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index 260e83e..24e86dc 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -51,7 +51,7 @@ int is_e0_later_in_bsp(int nodeid) return !is_cpu_pre_e0(); } // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 2)); if (!dev) return 0; @@ -73,7 +73,7 @@ int is_e0_later_in_bsp(int nodeid) int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + struct device *dev; dev = dev_find_slot(0, PCI_DEVFN(0x18 + nodeid, 3)); dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; @@ -228,7 +228,9 @@ static void init_ecc_memory(unsigned node_id) unsigned long basek; struct mtrr_state mtrr_state; - device_t f1_dev, f2_dev, f3_dev; + struct device *f1_dev; + struct device *f2_dev; + struct device *f3_dev; int enable_scrubbing; uint32_t dcl; @@ -456,7 +458,7 @@ static inline void k8_errata(void) } -static void model_fxx_init(device_t dev) +static void model_fxx_init(struct device *dev) { unsigned long i; msr_t msr; diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c index d653a85..419af78 100644 --- a/src/cpu/amd/quadcore/amd_sibling.c +++ b/src/cpu/amd/quadcore/amd_sibling.c @@ -30,7 +30,7 @@ #include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/amdfam10_sysconf.h> -extern device_t get_node_pci(u32 nodeid, u32 fn); +extern struct device *get_node_pci(u32 nodeid, u32 fn); #if 0 static int first_time = 1; @@ -40,7 +40,7 @@ static int first_time = 1; static u32 get_max_siblings(u32 nodes) { - device_t dev; + struct device *dev; u32 nodeid; u32 siblings=0; @@ -60,7 +60,7 @@ static u32 get_max_siblings(u32 nodes) static void enable_apic_ext_id(u32 nodes) { - device_t dev; + struct device *dev; u32 nodeid; //enable APIC_EXIT_ID all the nodes diff --git a/src/cpu/amd/sc520/sc520.c b/src/cpu/amd/sc520/sc520.c index 808c33c..ac3ba4e 100644 --- a/src/cpu/amd/sc520/sc520.c +++ b/src/cpu/amd/sc520/sc520.c @@ -18,7 +18,7 @@ * set up basic things ... * PAR should NOT go here, as it might change with the mainboard. */ -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { unsigned long *l = (unsigned long *) 0xfffef088; int i; @@ -49,7 +49,7 @@ static void sc520_enable_resources(struct device *dev) { } -static void sc520_read_resources(device_t dev) +static void sc520_read_resources(struct device *dev) { struct resource* res; @@ -83,9 +83,9 @@ static const struct pci_driver cpu_driver __pci_driver = { .device = 0x3000 }; -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { - device_t mc_dev; + struct device *mc_dev; uint32_t pci_tolm; printk(BIOS_SPEW, "%s\n", __func__); pci_tolm = find_pci_tolm(dev->link_list); @@ -130,7 +130,7 @@ static void pci_domain_set_resources(device_t dev) } #if 0 -void sc520_enable_resources(device_t dev) { +void sc520_enable_resources(struct device *dev) { printk(BIOS_SPEW, "%s\n", __func__); printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n"); @@ -165,12 +165,12 @@ static struct device_operations pci_domain_ops = { }; #if 0 -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { printk(BIOS_SPEW, "cpu_bus_init\n"); } -static void cpu_bus_noop(device_t dev) +static void cpu_bus_noop(struct device *dev) { }
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New patch to review for coreboot: 987d9bc soc: Don't hide pointers behind typedefs
by Edward O'Callaghan
30 Oct '14
30 Oct '14
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/7277
-gerrit commit 987d9bcebd241398a677e435585e1175487a2c78 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Oct 28 23:00:45 2014 +1100 soc: Don't hide pointers behind typedefs Change-Id: I05bb3b09cd1059cf43905a310f5c1ba04ed32336 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/soc/intel/baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/baytrail/chip.c | 8 +++---- src/soc/intel/baytrail/cpu.c | 4 ++-- src/soc/intel/baytrail/ehci.c | 4 ++-- src/soc/intel/baytrail/emmc.c | 2 +- src/soc/intel/baytrail/gfx.c | 14 +++++------ src/soc/intel/baytrail/hda.c | 2 +- src/soc/intel/baytrail/lpe.c | 12 +++++----- src/soc/intel/baytrail/lpss.c | 10 ++++---- src/soc/intel/baytrail/northcluster.c | 2 +- src/soc/intel/baytrail/pcie.c | 14 +++++------ src/soc/intel/baytrail/pmutil.c | 8 +++---- src/soc/intel/baytrail/ramstage.c | 2 +- src/soc/intel/baytrail/sata.c | 2 +- src/soc/intel/baytrail/scc.c | 2 +- src/soc/intel/baytrail/sd.c | 2 +- src/soc/intel/baytrail/smihandler.c | 2 +- src/soc/intel/baytrail/southcluster.c | 24 +++++++++---------- src/soc/intel/baytrail/spi.c | 2 +- src/soc/intel/baytrail/xhci.c | 6 ++--- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/broadwell/me.h | 2 +- src/soc/intel/broadwell/broadwell/pch.h | 2 +- src/soc/intel/broadwell/broadwell/ramstage.h | 4 ++-- src/soc/intel/broadwell/broadwell/xhci.h | 2 +- src/soc/intel/broadwell/chip.c | 8 +++---- src/soc/intel/broadwell/cpu.c | 6 ++--- src/soc/intel/broadwell/ehci.c | 2 +- src/soc/intel/broadwell/lpc.c | 18 +++++++-------- src/soc/intel/broadwell/me.c | 24 +++++++++---------- src/soc/intel/broadwell/pch.c | 6 ++--- src/soc/intel/broadwell/pcie.c | 32 +++++++++++++------------- src/soc/intel/broadwell/romstage/uart.c | 2 +- src/soc/intel/broadwell/sata.c | 2 +- src/soc/intel/broadwell/smbus.c | 8 +++---- src/soc/intel/broadwell/smihandler.c | 2 +- src/soc/intel/broadwell/smmrelocate.c | 6 ++--- src/soc/intel/broadwell/spi.c | 2 +- src/soc/intel/broadwell/systemagent.c | 22 +++++++++--------- src/soc/intel/broadwell/xhci.c | 8 +++---- src/soc/intel/fsp_baytrail/baytrail/baytrail.h | 2 +- src/soc/intel/fsp_baytrail/baytrail/ramstage.h | 6 ++--- src/soc/intel/fsp_baytrail/chip.c | 10 ++++---- src/soc/intel/fsp_baytrail/cpu.c | 4 ++-- src/soc/intel/fsp_baytrail/northcluster.c | 8 +++---- src/soc/intel/fsp_baytrail/pmutil.c | 4 ++-- src/soc/intel/fsp_baytrail/ramstage.c | 2 +- src/soc/intel/fsp_baytrail/smihandler.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 26 ++++++++++----------- src/soc/intel/fsp_baytrail/spi.c | 6 ++--- src/soc/nvidia/tegra/dc.h | 2 +- src/soc/nvidia/tegra124/display.c | 2 +- src/soc/nvidia/tegra124/soc.c | 8 +++---- src/soc/samsung/exynos5250/cpu.c | 10 ++++---- src/soc/samsung/exynos5420/cpu.c | 10 ++++---- 55 files changed, 195 insertions(+), 195 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index a8b5fdc..4a7b536 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -26,16 +26,16 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); +void southcluster_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index ce9eb49..1a478dc 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -26,7 +26,7 @@ #include <baytrail/ramstage.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -40,7 +40,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, @@ -51,7 +51,7 @@ static struct device_operations cpu_bus_ops = { }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -79,7 +79,7 @@ struct chip_operations soc_intel_baytrail_ops = { .init = soc_init, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index e8f95ae..a5106dd 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -78,7 +78,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -121,7 +121,7 @@ void baytrail_init_cpus(device_t dev) restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index 5d1a4d8..accfed2 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -91,7 +91,7 @@ static const struct reg_script ehci_hc_reset[] = { REG_SCRIPT_END }; -static void usb2_phy_init(device_t dev) +static void usb2_phy_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { @@ -123,7 +123,7 @@ static void usb2_phy_init(device_t dev) reg_script_run(usb2_phy_script); } -static void ehci_init(device_t dev) +static void ehci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ehci_hc_init[] = { diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index f88614b..74bdb4b 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -49,7 +49,7 @@ static const struct reg_script emmc_ops[] = { REG_SCRIPT_END, }; -static void emmc_init(device_t dev) +static void emmc_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 9d4768f..a47152d 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -38,7 +38,7 @@ * Lock Power Context Base Register to point to a 24KB block * of memory in GSM. Power context save data is stored here. */ -static void gfx_lock_pcbase(device_t dev) +static void gfx_lock_pcbase(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, @@ -263,18 +263,18 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(struct device *dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } -static void gfx_pre_vbios_init(device_t dev) +static void gfx_pre_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) +static void gfx_pm_init(struct device *dev) { printk(BIOS_INFO, "GFX: Power Management Init\n"); gfx_run_script(dev, gfx_init_script); @@ -283,13 +283,13 @@ static void gfx_pm_init(device_t dev) gfx_lock_pcbase(dev); } -static void gfx_post_vbios_init(device_t dev) +static void gfx_post_vbios_init(struct device *dev) { printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void gfx_panel_setup(device_t dev) +static void gfx_panel_setup(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { @@ -340,7 +340,7 @@ static void gfx_panel_setup(device_t dev) } } -static void gfx_init(device_t dev) +static void gfx_init(struct device *dev) { /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index c5de654..5733b95 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -78,7 +78,7 @@ static const uint32_t hdmi_codec_verb_table[] = { 0x20671f58, }; -static void hda_init(device_t dev) +static void hda_init(struct device *dev) { struct resource *res; int codec_mask; diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index 581f42b..b6fb7c2 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -45,7 +45,7 @@ #define FIRMWARE_REG_BASE_C0 0x144000 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) -static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +static void assign_device_nvs(struct device *dev, u32 *field, unsigned index) { struct resource *res; @@ -54,7 +54,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index) *field = res->base; } -static void lpe_enable_acpi_mode(device_t dev) +static void lpe_enable_acpi_mode(struct device *dev) { static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -87,7 +87,7 @@ static void lpe_enable_acpi_mode(device_t dev) reg_script_run_on_dev(dev, ops); } -static void setup_codec_clock(device_t dev) +static void setup_codec_clock(struct device *dev) { uint32_t reg; int clk_reg; @@ -125,7 +125,7 @@ static void setup_codec_clock(device_t dev) write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); } -static void lpe_stash_firmware_info(device_t dev) +static void lpe_stash_firmware_info(struct device *dev) { struct resource *res; struct resource *mmio; @@ -149,7 +149,7 @@ static void lpe_stash_firmware_info(device_t dev) } } -static void lpe_init(device_t dev) +static void lpe_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -161,7 +161,7 @@ static void lpe_init(device_t dev) lpe_enable_acpi_mode(dev); } -static void lpe_read_resources(device_t dev) +static void lpe_read_resources(struct device *dev) { pci_dev_read_resources(dev); diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index 3ee648a..c548370 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -33,7 +33,7 @@ #include "chip.h" -static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ @@ -70,7 +70,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg) { struct reg_script ops[] = { REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, @@ -82,7 +82,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run_on_dev(dev, ops); } -static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; @@ -123,7 +123,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) } } -static void i2c_disable_resets(device_t dev) +static void i2c_disable_resets(struct device *dev) { /* Release the I2C devices from reset. */ static const struct reg_script ops[] = { @@ -150,7 +150,7 @@ static void i2c_disable_resets(device_t dev) } } -static void lpss_init(device_t dev) +static void lpss_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; int iosf_reg, nvs_index; diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index b119e24..2d4f20b 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -71,7 +71,7 @@ uint32_t nc_read_top_of_low_memory(void) return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { unsigned long mmconf; unsigned long bmbound; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 4498f43..e530498 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -34,12 +34,12 @@ static int pll_en_off; static uint32_t strpfusecfg; -static inline int root_port_offset(device_t dev) +static inline int root_port_offset(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn); } -static inline int is_first_port(device_t dev) +static inline int is_first_port(struct device *dev) { return root_port_offset(dev) == PCIE_PORT1_FUNC; } @@ -88,7 +88,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void byt_pcie_init(struct device *dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), @@ -129,7 +129,7 @@ static const struct reg_script no_dev_behind_port[] = { REG_SCRIPT_END, }; -static void check_port_enabled(device_t dev) +static void check_port_enabled(struct device *dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; @@ -155,7 +155,7 @@ static void check_port_enabled(device_t dev) } } -static void check_device_present(device_t dev) +static void check_device_present(struct device *dev) { /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -172,7 +172,7 @@ static void check_device_present(device_t dev) } } -static void byt_pcie_enable(device_t dev) +static void byt_pcie_enable(struct device *dev) { if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -194,7 +194,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +static void pcie_root_set_subsystem(struct device *dev, unsigned vid, unsigned did) { uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index aee3726..935253c 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -28,9 +28,9 @@ #if defined(__SMM__) -static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); +static const pci_devfn_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); -static inline device_t get_pcu_dev(void) +static inline pci_devfn_t get_pcu_dev(void) { return pcu_dev; } @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 9622930..10f7ff2 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -78,7 +78,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c index 28a2f8c..3c69985 100644 --- a/src/soc/intel/baytrail/sata.c +++ b/src/soc/intel/baytrail/sata.c @@ -159,7 +159,7 @@ static void sata_init(struct device *dev) pci_write_config32(dev, 0x98, reg32); } -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { config_t *config = dev->chip_info; u8 reg8; diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 7efb66d..e2bd1dd 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -87,7 +87,7 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 97c8628..6068e61 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -34,7 +34,7 @@ #define CAP_OVERRIDE_HIGH 0xa4 # define USE_CAP_OVERRIDES (1 << 31) -static void sd_init(device_t dev) +static void sd_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 22b60c4..4dca798 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 500a13d..d3d284d 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -43,12 +43,12 @@ #include "chip.h" static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -83,7 +83,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -96,7 +96,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; @@ -113,7 +113,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -154,7 +154,7 @@ static void sc_rtc_init(void) * or configuration. This is definitely a hack, but it helps the kernel * along. */ -static void com1_configure_resume(device_t dev) +static void com1_configure_resume(struct device *dev) { const uint16_t port = 0x3f8; @@ -182,7 +182,7 @@ static void com1_configure_resume(device_t dev) outb(3, port + UART8250_LCR); } -static void sc_init(device_t dev) +static void sc_init(struct device *dev) { int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; @@ -224,7 +224,7 @@ static void sc_init(device_t dev) */ /* Set bit in function disble register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -333,7 +333,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -345,7 +345,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -362,7 +362,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -478,7 +478,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 8677b61..4de3d91 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -290,7 +290,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; + struct device *dev; uint32_t sbase; #ifdef __SMM__ diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 8d076c2..3f3ed91 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -148,7 +148,7 @@ const struct reg_script xhci_clock_gating_script[] = { }; /* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) +static void xhci_reset_port_usb3(struct device *dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ @@ -167,7 +167,7 @@ static void xhci_reset_port_usb3(device_t dev, int port) } /* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) +static void xhci_route_all(struct device *dev) { static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ @@ -196,7 +196,7 @@ static void xhci_route_all(device_t dev) } } -static void xhci_init(device_t dev) +static void xhci_init(struct device *dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index f4cac7b..3259308 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -394,7 +394,7 @@ static int generate_T_state_entries(int core, int cores_per_package) static int generate_C_state_entries(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *config = dev->chip_info; acpi_cstate_t map[3]; int *set; diff --git a/src/soc/intel/broadwell/broadwell/me.h b/src/soc/intel/broadwell/broadwell/me.h index ddecaf8..f3021ee 100644 --- a/src/soc/intel/broadwell/broadwell/me.h +++ b/src/soc/intel/broadwell/broadwell/me.h @@ -465,7 +465,7 @@ typedef struct { } __attribute__ ((packed)) mbp_plat_time; typedef struct { - u32 device_type : 2; + u32 struct device *ype : 2; u32 reserved : 30; } __attribute__ ((packed)) mbp_nfc_data; diff --git a/src/soc/intel/broadwell/broadwell/pch.h b/src/soc/intel/broadwell/broadwell/pch.h index e677215..c58b695 100644 --- a/src/soc/intel/broadwell/broadwell/pch.h +++ b/src/soc/intel/broadwell/broadwell/pch.h @@ -47,6 +47,6 @@ int pch_is_wpt(void); int pch_is_wpt_ulx(void); u32 pch_read_soft_strap(int id); void pch_log_state(void); -void pch_disable_devfn(device_t dev); +void pch_disable_devfn(struct device *dev); #endif diff --git a/src/soc/intel/broadwell/broadwell/ramstage.h b/src/soc/intel/broadwell/broadwell/ramstage.h index 685de14..d66e8cc 100644 --- a/src/soc/intel/broadwell/broadwell/ramstage.h +++ b/src/soc/intel/broadwell/broadwell/ramstage.h @@ -24,8 +24,8 @@ #include <chip.h> void broadwell_init_pre_device(void *chip_info); -void broadwell_init_cpus(device_t dev); -void broadwell_pch_enable_dev(device_t dev); +void broadwell_init_cpus(struct device *dev); +void broadwell_pch_enable_dev(struct device *dev); #if CONFIG_HAVE_REFCODE_BLOB void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/broadwell/xhci.h b/src/soc/intel/broadwell/broadwell/xhci.h index 3f4fb4e..a5536fc 100644 --- a/src/soc/intel/broadwell/broadwell/xhci.h +++ b/src/soc/intel/broadwell/broadwell/xhci.h @@ -55,7 +55,7 @@ #define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ #ifdef __SMM__ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ); #endif #endif diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index 94f7893..e2ab17c 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -24,7 +24,7 @@ #include <broadwell/ramstage.h> #include <chip.h> -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } @@ -36,7 +36,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = &pci_ops_mmconf, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = &cpu_bus_noop, @@ -45,7 +45,7 @@ static struct device_operations cpu_bus_ops = { .init = &broadwell_init_cpus, }; -static void broadwell_enable(device_t dev) +static void broadwell_enable(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { @@ -67,7 +67,7 @@ struct chip_operations soc_intel_broadwell_ops = { .init = &broadwell_init_pre_device, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 58f81fc..416fe3c 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -444,7 +444,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; msr_t msr; @@ -587,7 +587,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus) } /* All CPUs including BSP will run the following function. */ -static void cpu_core_init(device_t cpu) +static void cpu_core_init(struct device *cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -671,7 +671,7 @@ static const struct cpu_driver driver __cpu_driver = { .id_table = cpu_table, }; -void broadwell_init_cpus(device_t dev) +void broadwell_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; int num_threads; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index a59d3c8..30f4acd 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -28,7 +28,7 @@ #include <broadwell/ehci.h> #include <broadwell/pch.h> -static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { u8 access_cntl; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 4b21326..270316c 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -89,9 +89,9 @@ static void pch_enable_ioapic(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void pch_pirq_init(device_t dev) +static void pch_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; config_t *config = dev->chip_info; pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); @@ -126,7 +126,7 @@ static void pch_pirq_init(device_t dev) } } -static void pch_power_options(device_t dev) +static void pch_power_options(struct device *dev) { u16 reg16; const char *state; @@ -325,7 +325,7 @@ static void pch_pm_init(struct device *dev) RCBA32_OR(0x3a6c, 0x00000001); } -static void pch_cg_init(device_t dev) +static void pch_cg_init(struct device *dev) { u32 reg32; u16 reg16; @@ -420,7 +420,7 @@ static void lpc_init(struct device *dev) pch_set_acpi_mode(); } -static void pch_lpc_add_mmio_resources(device_t dev) +static void pch_lpc_add_mmio_resources(struct device *dev) { u32 reg; struct resource *res; @@ -482,7 +482,7 @@ static inline int pch_io_range_in_default(u16 base, u16 size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) +static void pch_lpc_add_io_resource(struct device *dev, u16 base, u16 size, int index) { struct resource *res; @@ -495,7 +495,7 @@ static void pch_lpc_add_io_resource(device_t dev, u16 base, u16 size, int index) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) +static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value, int index) { /* * Check if the register is enabled. If so and the base exceeds the @@ -508,7 +508,7 @@ static void pch_lpc_add_gen_io_resources(device_t dev, int reg_value, int index) } } -static void pch_lpc_add_io_resources(device_t dev) +static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; config_t *config = dev->chip_info; @@ -533,7 +533,7 @@ static void pch_lpc_add_io_resources(device_t dev) pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC); } -static void pch_lpc_read_resources(device_t dev) +static void pch_lpc_read_resources(struct device *dev) { global_nvs_t *gnvs; diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 15bcc34..19bc754 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -58,11 +58,11 @@ static const char *me_bios_path_values[] = { [ME_DISABLE_BIOS_PATH] = "Disable", [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev); /* MMIO base address for MEI interface */ static u32 mei_base_address; -void intel_me_mbp_clear(device_t dev); +void intel_me_mbp_clear(struct device *dev); #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -117,7 +117,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) mei_dump(ptr, dword, offset, "WRITE"); } -static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset) +static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -440,7 +440,7 @@ static inline int mei_sendrecv_icc(struct icc_header *icc, * mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read * state machine on the BIOS end doesn't match the ME's state machine. */ -static void intel_me_mbp_give_up(device_t dev) +static void intel_me_mbp_give_up(struct device *dev) { struct mei_csr csr; @@ -456,7 +456,7 @@ static void intel_me_mbp_give_up(device_t dev) * mbp clear routine. This will wait for the ME to indicate that * the MBP has been read and cleared. */ -void intel_me_mbp_clear(device_t dev) +void intel_me_mbp_clear(struct device *dev) { int count; struct me_hfs2 hfs2; @@ -568,7 +568,7 @@ static int mkhi_end_of_post(void) void intel_me_finalize(void) { - device_t dev = PCH_DEV_ME; + struct device *dev = PCH_DEV_ME; struct me_hfs hfs; u32 reg32; @@ -629,7 +629,7 @@ static int me_icc_set_clock_enables(u32 mask) } /* Determine the path that we should take based on ME status */ -static me_bios_path intel_me_path(device_t dev) +static me_bios_path intel_me_path(struct device *dev) { me_bios_path path = ME_DISABLE_BIOS_PATH; struct me_hfs hfs; @@ -699,7 +699,7 @@ static me_bios_path intel_me_path(device_t dev) } /* Prepare ME for MEI messages */ -static int intel_mei_setup(device_t dev) +static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -729,7 +729,7 @@ static int intel_mei_setup(device_t dev) } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(device_t dev) +static int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -776,7 +776,7 @@ static int intel_me_extend_valid(device_t dev) } /* Check whether ME is present and do basic init */ -static void intel_me_init(device_t dev) +static void intel_me_init(struct device *dev) { config_t *config = dev->chip_info; me_bios_path path = intel_me_path(dev); @@ -829,7 +829,7 @@ static void intel_me_init(device_t dev) */ } -static void intel_me_enable(device_t dev) +static void intel_me_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ @@ -882,7 +882,7 @@ struct mbp_payload { * mbp seems to be following its own flow, let's retrieve it in a dedicated * function. */ -static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) +static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) { mbp_header mbp_hdr; u32 me2host_pending; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 82390a4..e681620 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -81,7 +81,7 @@ u32 pch_read_soft_strap(int id) #ifndef __PRE_RAM__ /* Put device in D3Hot Power State */ -static void pch_enable_d3hot(device_t dev) +static void pch_enable_d3hot(struct device *dev) { u32 reg32 = pci_read_config32(dev, PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; @@ -89,7 +89,7 @@ static void pch_enable_d3hot(device_t dev) } /* Set bit in Function Disble register to hide this device */ -void pch_disable_devfn(device_t dev) +void pch_disable_devfn(struct device *dev) { switch (dev->path.pci.devfn) { case PCH_DEVFN_ADSP: /* Audio DSP */ @@ -179,7 +179,7 @@ void pch_disable_devfn(device_t dev) } } -void broadwell_pch_enable_dev(device_t dev) +void broadwell_pch_enable_dev(struct device *dev) { u32 reg32; diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index a407f3c..08e4863 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -32,8 +32,8 @@ #include <broadwell/rcba.h> #include <chip.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or); +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or); /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -52,23 +52,23 @@ struct root_port_config { int coalesce; int gbe_port; int num_ports; - device_t ports[NUM_ROOT_PORTS]; + struct device *ports[NUM_ROOT_PORTS]; }; static struct root_port_config rpc; -static inline int root_port_is_first(device_t dev) +static inline int root_port_is_first(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == 0; } -static inline int root_port_is_last(device_t dev) +static inline int root_port_is_last(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1); } /* Root ports are numbered 1..N in the documentation. */ -static inline int root_port_number(device_t dev) +static inline int root_port_number(struct device *dev) { return PCI_FUNC(dev->path.pci.devfn) + 1; } @@ -98,7 +98,7 @@ static void root_port_config_update_gbe_port(void) } } -static void root_port_init_config(device_t dev) +static void root_port_init_config(struct device *dev) { int rp; @@ -149,7 +149,7 @@ static void root_port_init_config(device_t dev) /* Update devicetree with new Root Port function number assignment */ static void pch_pcie_device_set_func(int index, int pci_func) { - device_t dev; + struct device *dev; unsigned new_devfn; dev = rpc.ports[index]; @@ -178,7 +178,7 @@ static void pcie_enable_clock_gating(void) int enabled_ports = 0; for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; int rp; dev = rpc.ports[i]; @@ -244,7 +244,7 @@ static void root_port_commit_config(void) pcie_enable_clock_gating(); for (i = 0; i < rpc.num_ports; i++) { - device_t dev; + struct device *dev; u32 reg32; dev = rpc.ports[i]; @@ -297,7 +297,7 @@ static void root_port_commit_config(void) RCBA32(RPFN) = rpc.new_rpfn; } -static void root_port_mark_disable(device_t dev) +static void root_port_mark_disable(struct device *dev) { /* Mark device as disabled. */ dev->enabled = 0; @@ -305,7 +305,7 @@ static void root_port_mark_disable(device_t dev) rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); } -static void root_port_check_disable(device_t dev) +static void root_port_check_disable(struct device *dev) { int rp; @@ -376,7 +376,7 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) +static void pcie_update_cfg8(struct device *dev, int reg, u8 mask, u8 or) { u8 reg8; @@ -386,7 +386,7 @@ static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) +static void pcie_update_cfg(struct device *dev, int reg, u32 mask, u32 or) { u32 reg32; @@ -574,7 +574,7 @@ static void pch_pcie_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); } -static void pch_pcie_enable(device_t dev) +static void pch_pcie_enable(struct device *dev) { /* Add this device to the root port config structure. */ root_port_init_config(dev); @@ -594,7 +594,7 @@ static void pch_pcie_enable(device_t dev) root_port_commit_config(); } -static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pcie_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { /* NOTE: This is not the default position! */ if (!vendor || !device) diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index 8214a8a..2517fef 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -52,7 +52,7 @@ void pch_uart_init(void) { /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ u32 gpiodf = 0x131f; - device_t dev; + struct device *dev; /* Put UART in byte access mode for 16550 compatibility */ switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index e8d1fbe..24a8ebe 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -221,7 +221,7 @@ static void sata_init(struct device *dev) * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ -static void sata_enable(device_t dev) +static void sata_enable(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index a1dbdfe..c214510 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -31,7 +31,7 @@ #include <broadwell/ramstage.h> #include <broadwell/smbus.h> -static void pch_smbus_init(device_t dev) +static void pch_smbus_init(struct device *dev) { struct resource *res; u16 reg16; @@ -47,7 +47,7 @@ static void pch_smbus_init(device_t dev) outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); } -static int lsmbus_read_byte(device_t dev, u8 address) +static int lsmbus_read_byte(struct device *dev, u8 address) { u16 device; struct resource *res; @@ -60,7 +60,7 @@ static int lsmbus_read_byte(device_t dev, u8 address) return do_smbus_read_byte(res->base, device, address); } -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) +static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) { u16 device; struct resource *res; @@ -77,7 +77,7 @@ static struct smbus_bus_operations lops_smbus_bus = { .write_byte = lsmbus_write_byte, }; -static void smbus_read_resources(device_t dev) +static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_BASE_ADDRESS; diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 6acd07c..49cf774 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -83,7 +83,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + struct device *dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index bd1fc26..9ba6a00 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -196,7 +196,7 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) } } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -206,7 +206,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -static void fill_in_relocation_params(device_t dev, +static void fill_in_relocation_params(struct device *dev, struct smm_relocation_params *params) { u32 tseg_size; @@ -351,7 +351,7 @@ static int install_permanent_handler(int num_cpus, static int cpu_smm_setup(void) { - device_t dev = SA_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; int num_cpus; msr_t msr; diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 353323a..6095cf7 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -286,7 +286,7 @@ void spi_init(void) uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; - device_t dev = PCH_DEV_LPC; + struct device *dev = PCH_DEV_LPC; ich9_spi_regs *ich9_spi; pci_read_config_dword(dev, 0xf0, &rcba); diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 787a62b..c1110ab 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -37,7 +37,7 @@ #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; @@ -70,7 +70,7 @@ static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) return 0; } -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) +static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -89,7 +89,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) /* There are special BARs that actually are programmed in the MCHBAR. These * Intel special features, but they do consume resources that need to be * accounted for. */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { u32 bar; @@ -109,7 +109,7 @@ static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(device_t dev, unsigned int index, + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; @@ -127,7 +127,7 @@ struct fixed_mmio_descriptor mc_fixed_resources[] = { * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. */ -static void mc_add_fixed_mmio_resources(device_t dev) +static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -184,7 +184,7 @@ struct map_entry { const char *description; }; -static void read_map_entry(device_t dev, struct map_entry *entry, +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; @@ -253,7 +253,7 @@ static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -static void mc_read_map_entries(device_t dev, uint64_t *values) +static void mc_read_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -261,7 +261,7 @@ static void mc_read_map_entries(device_t dev, uint64_t *values) } } -static void mc_report_map_entries(device_t dev, uint64_t *values) +static void mc_report_map_entries(struct device *dev, uint64_t *values) { int i; for (i = 0; i < NUM_MAP_ENTRIES; i++) { @@ -272,7 +272,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values) printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { unsigned long base_k, size_k; unsigned long touud_k; @@ -376,7 +376,7 @@ static void mc_add_dram_resources(device_t dev) chromeos_reserve_ram_oops(dev, index++); } -static void systemagent_read_resources(device_t dev) +static void systemagent_read_resources(struct device *dev) { /* Read standard PCI resources. */ pci_dev_read_resources(dev); @@ -412,7 +412,7 @@ static void systemagent_init(struct device *dev) set_power_limits(28); } -static void systemagent_enable(device_t dev) +static void systemagent_enable(struct device *dev) { #if CONFIG_HAVE_ACPI_RESUME struct romstage_handoff *handoff; diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 89e1139..9530422 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -27,7 +27,7 @@ #include <broadwell/xhci.h> #ifdef __SMM__ -static u32 usb_xhci_mem_base(device_t dev) +static u32 usb_xhci_mem_base(struct device *dev) { u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); @@ -38,7 +38,7 @@ static u32 usb_xhci_mem_base(device_t dev) return mem_base & ~0xf; } -static int usb_xhci_port_count_usb3(device_t dev) +static int usb_xhci_port_count_usb3(struct device *dev) { /* PCH-LP has 4 SS ports */ return 4; @@ -71,7 +71,7 @@ static void usb_xhci_reset_port_usb3(u32 mem_base, int port) * b) Poll for warm reset complete * c) Write 1 to port change status bits */ -static void usb_xhci_reset_usb3(device_t dev, int all) +static void usb_xhci_reset_usb3(struct device *dev, int all) { u32 status, port_disabled; int timeout, port; @@ -142,7 +142,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all) } /* Handler for XHCI controller on entry to S3/S4/S5 */ -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) +void usb_xhci_sleep_prepare(struct device *dev, u8 slp_typ) { u16 reg16; u32 reg32; diff --git a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h index d3a2377..d991d34 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/baytrail.h +++ b/src/soc/intel/fsp_baytrail/baytrail/baytrail.h @@ -57,7 +57,7 @@ void rangeley_early_initialization(void); int soc_silicon_revision(void); int soc_silicon_type(void); int soc_silicon_supported(int type, int rev); -void soc_enable(device_t dev); +void soc_enable(struct device *dev); /* debugging functions */ void print_pci_devices(void); diff --git a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h index 095f09c..c1114df 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/ramstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/ramstage.h @@ -25,10 +25,10 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); -void baytrail_init_cpus(device_t dev); +void baytrail_init_cpus(struct device *dev); void set_max_freq(void); -void southcluster_enable_dev(device_t dev); -void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); +void southcluster_enable_dev(struct device *dev); +void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 839e8dc..e8f8ef4 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -25,12 +25,12 @@ #include <drivers/intel/fsp/fsp_util.h> #include "chip.h" -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { assign_resources(dev->link_list); } -static void finalize_dev (device_t dev) +static void finalize_dev (struct device *dev) { /* * Notify FSP for PostPciEnumeration. @@ -50,7 +50,7 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_noop(device_t dev) { } +static void cpu_bus_noop(struct device *dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, @@ -60,7 +60,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = NULL, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", dev_name(dev), dev->path.type); @@ -100,7 +100,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = { .final = &finalize_chip, }; -static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index 6f1e9c4..5c6375e 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -68,7 +68,7 @@ const struct reg_script core_msr_script[] = { REG_SCRIPT_END }; -void baytrail_init_cpus(device_t dev) +void baytrail_init_cpus(struct device *dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); @@ -91,7 +91,7 @@ void baytrail_init_cpus(device_t dev) } } -static void baytrail_core_init(device_t cpu) +static void baytrail_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 838e554..010063e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -92,7 +92,7 @@ uint32_t nc_read_top_of_low_memory(void) static int get_pcie_bar(u32 *base, u32 *len) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -141,7 +141,7 @@ static int add_fixed_resources(struct device *dev, int index) return index; } -static void mc_add_dram_resources(device_t dev) +static void mc_add_dram_resources(struct device *dev) { u32 bmbound, bsmmrrl; int index = 0; @@ -189,7 +189,7 @@ static void mc_add_dram_resources(device_t dev) index = add_fixed_resources(dev, index); } -static void nc_read_resources(device_t dev) +static void nc_read_resources(struct device *dev) { /* Call the normal read_resources */ pci_dev_read_resources(dev); @@ -199,7 +199,7 @@ static void nc_read_resources(device_t dev) mc_add_dram_resources(dev); } -static void nc_enable(device_t dev) +static void nc_enable(struct device *dev) { print_fsp_info(); } diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c index aee3726..6a62a34 100644 --- a/src/soc/intel/fsp_baytrail/pmutil.c +++ b/src/soc/intel/fsp_baytrail/pmutil.c @@ -39,8 +39,8 @@ static inline device_t get_pcu_dev(void) #include <device/device.h> #include <device/pci.h> -static device_t pcu_dev; -static device_t get_pcu_dev(void) +static struct device *pcu_dev; +static struct device *get_pcu_dev(void) { if (pcu_dev == NULL) pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 814b16e..55abb4d 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -76,7 +76,7 @@ static const char *stepping_str[] = { static void fill_in_pattrs(void) { - device_t dev; + struct device *dev; msr_t msr; struct pattrs *attrs = (struct pattrs *)pattrs_get(); diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index 2225964..50b6ef4 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -71,7 +71,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { u32 reg32; - device_t dev = PCI_DEV(bus, slot, func); + pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902..307b006 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -51,12 +51,12 @@ typedef struct soc_intel_fsp_baytrail_config config_t; static inline void -add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { mmio_resource(dev, i, addr >> 10, size >> 10); } -static void sc_add_mmio_resources(device_t dev) +static void sc_add_mmio_resources(struct device *dev) { #ifndef CONFIG_VIRTUAL_ROM_SIZE #error CONFIG_VIRTUAL_ROM_SIZE must be set. @@ -171,8 +171,8 @@ static void sc_enable_serial_irqs(struct device *dev) */ static void write_pci_config_irqs(void) { - device_t irq_dev; - device_t targ_dev; + struct device *irq_dev; + struct device *targ_dev; uint8_t int_line = 0; uint8_t original_int_pin = 0; uint8_t new_int_pin = 0; @@ -255,7 +255,7 @@ static void write_pci_config_irqs(void) printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -static void sc_pirq_init(device_t dev) +static void sc_pirq_init(struct device *dev) { int i, j; int pirq; @@ -318,7 +318,7 @@ static inline int io_range_in_default(int base, int size) * Note: this function assumes there is no overlap with the default LPC device's * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. */ -static void sc_add_io_resource(device_t dev, int base, int size, int index) +static void sc_add_io_resource(struct device *dev, int base, int size, int index) { struct resource *res; @@ -332,7 +332,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) IORESOURCE_FIXED; } -static void sc_add_io_resources(device_t dev) +static void sc_add_io_resources(struct device *dev) { struct resource *res; u8 io_index = 0; @@ -354,7 +354,7 @@ static void sc_add_io_resources(device_t dev) sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } -static void sc_read_resources(device_t dev) +static void sc_read_resources(struct device *dev) { /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -409,7 +409,7 @@ static void sc_init(struct device *dev) */ /* Set bit in function disable register to hide this device. */ -static void sc_disable_devfn(device_t dev) +static void sc_disable_devfn(struct device *dev) { const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; @@ -505,7 +505,7 @@ static void sc_disable_devfn(device_t dev) } } -static inline void set_d3hot_bits(device_t dev, int offset) +static inline void set_d3hot_bits(struct device *dev, int offset) { uint32_t reg8; printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); @@ -517,7 +517,7 @@ static inline void set_d3hot_bits(device_t dev, int offset) /* Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of * the audio paths work for LPE audio. */ -static void hda_work_around(device_t dev) +static void hda_work_around(struct device *dev) { unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; @@ -534,7 +534,7 @@ static void hda_work_around(device_t dev) pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); } -static int place_device_in_d3hot(device_t dev) +static int place_device_in_d3hot(struct device *dev) { unsigned offset; @@ -611,7 +611,7 @@ static int place_device_in_d3hot(device_t dev) } /* Common PCI device function disable. */ -void southcluster_enable_dev(device_t dev) +void southcluster_enable_dev(struct device *dev) { uint32_t reg32; diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 4feb502..295e203 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -288,13 +288,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) static ich9_spi_regs *spi_regs(void) { - device_t dev; uint32_t sbase; +/* N.B. dev is type-dependent on stage */ #ifdef __SMM__ - dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + pci_devfn_t dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); #else - dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 48ffbda..895fd89 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -567,7 +567,7 @@ struct disp_ctl_win { u32 out_h; /* Height of output window in pixels */ }; -void display_startup(device_t dev); +void display_startup(struct device *dev); void dp_bringup(u32 winb_addr); unsigned int fb_base_mb(void); diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 00dfbb6..9cc0cf0 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -234,7 +234,7 @@ uint32_t fb_base_mb(void) /* this is really aimed at the lcd panel. That said, there are two display * devices on this part and we may someday want to extend it for other boards. */ -void display_startup(device_t dev) +void display_startup(struct device *dev) { u32 val; int i; diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c index 11a52c4..eb8002b 100644 --- a/src/soc/nvidia/tegra124/soc.c +++ b/src/soc/nvidia/tegra124/soc.c @@ -29,7 +29,7 @@ * Will break if we get 2. Sigh. * We assume it's all multiples of MiB for MMUs sake. */ -static void soc_enable(device_t dev) +static void soc_enable(struct device *dev) { u32 lcdbase = fb_base_mb(); unsigned long fb_size = FB_SIZE_MB; @@ -39,13 +39,13 @@ static void soc_enable(device_t dev) mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); } -static void soc_init(device_t dev) +static void soc_init(struct device *dev) { display_startup(dev); printk(BIOS_INFO, "CPU: Tegra124\n"); } -static void soc_noop(device_t dev) +static void soc_noop(struct device *dev) { } @@ -57,7 +57,7 @@ static struct device_operations soc_ops = { .scan_bus = 0, }; -static void enable_tegra124_dev(device_t dev) +static void enable_tegra124_dev(struct device *dev) { dev->ops = &soc_ops; } diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index b8b88d7..c4561f6 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -59,7 +59,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5250_config *conf = dev->chip_info; @@ -110,7 +110,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -123,13 +123,13 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / (1024*1024)); } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -141,7 +141,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5250_dev(device_t dev) +static void enable_exynos5250_dev(struct device *dev) { dev->ops = &cpu_ops; } diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 506b676..b646f82 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -73,7 +73,7 @@ static void set_cpu_id(void) * involving lots of machine and callbacks, is hard to debug and * verify. */ -static void exynos_displayport_init(device_t dev, u32 lcdbase, +static void exynos_displayport_init(struct device *dev, u32 lcdbase, unsigned long fb_size) { struct soc_samsung_exynos5420_config *conf = dev->chip_info; @@ -133,7 +133,7 @@ static void tps65090_thru_ec_fet_disable(int index) } } -static void cpu_enable(device_t dev) +static void cpu_enable(struct device *dev) { unsigned long fb_size = FB_SIZE_KB * KiB; u32 lcdbase = get_fb_base_kb() * KiB; @@ -154,13 +154,13 @@ static void cpu_enable(device_t dev) set_cpu_id(); } -static void cpu_init(device_t dev) +static void cpu_init(struct device *dev) { printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", cpu_id, get_arm_clk() / 1000000); } -static void cpu_noop(device_t dev) +static void cpu_noop(struct device *dev) { } @@ -172,7 +172,7 @@ static struct device_operations cpu_ops = { .scan_bus = 0, }; -static void enable_exynos5420_dev(device_t dev) +static void enable_exynos5420_dev(struct device *dev) { dev->ops = &cpu_ops; }
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