Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4881
-gerrit
commit 33bf5faf7a285392c8e6e03bbf60c87deb56111c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 10 12:47:47 2013 -0500
baytrail: allow downstream use of SSE instructions
If a payload is compiled to use SSE instructions it will
fault with an undefined opcode because SSE instructions weren't
enabled. Therefore enable SSE instructions at runtime.
BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted with SSE enabled payload. No exceptions seen.
Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172642
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
---
src/soc/intel/baytrail/ramstage.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 10c030f..229e367 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -20,6 +20,7 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
+#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci_def.h>
@@ -109,6 +110,9 @@ void baytrail_init_pre_device(void)
fill_in_pattrs();
+ /* Allow for SSE instructions to be executed. */
+ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
+
/* Get GPIO initial states from mainboard */
config = mainboard_get_gpios();
setup_soc_gpios(config);
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4879
-gerrit
commit b08ce0a024de50a965c149c1cfb4ba37abba1fd0
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 10 20:58:57 2013 -0500
vboot: provide empty vboot_verify_firmware()
In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being
selected allow for calling vboot_verify_firmware()
with an empty implementation. This allows for one not to
clutter the source with ifdefs.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded
call to vboot_verify_firmware().
Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172711
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/vendorcode/google/chromeos/chromeos.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index f51215e..5493801 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -46,12 +46,14 @@ int recovery_mode_enabled(void);
/* functions implemented in vboot.c */
void init_chromeos(int bootmode);
-#if CONFIG_VBOOT_VERIFY_FIRMWARE
struct romstage_handoff;
+#if CONFIG_VBOOT_VERIFY_FIRMWARE
void vboot_verify_firmware(struct romstage_handoff *handoff);
void *vboot_get_payload(size_t *len);
/* Returns 0 on success < 0 on error. */
int vboot_get_handoff_info(void **addr, uint32_t *size);
+#else
+static inline void vboot_verify_firmware(struct romstage_handoff *h) {}
#endif
#endif
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4878
-gerrit
commit 92096b4e589165b1c791c79a26d104fc1b6e327c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 10 20:54:57 2013 -0500
baytrail: add reset support
Bay Trail has the following types of resets it supports:
- Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
- Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
- Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
- Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
- Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to
0xcf9 but with ETR[20] set.
While these are documented this support currently provides support
for 2nd soft reset as well as cold and warm reset.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted.
Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172710
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/soc/intel/baytrail/Kconfig | 1 +
src/soc/intel/baytrail/Makefile.inc | 2 ++
src/soc/intel/baytrail/baytrail/pmc.h | 12 +++++++++
src/soc/intel/baytrail/baytrail/reset.h | 36 +++++++++++++++++++++++++
src/soc/intel/baytrail/reset.c | 47 +++++++++++++++++++++++++++++++++
5 files changed, 98 insertions(+)
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 1a7851a..2431802 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_MICROCODE_IN_CBFS
select DYNAMIC_CBMEM
select HAVE_SMI_HANDLER
+ select HAVE_HARD_RESET
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 4707d2b..2cae746 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -20,6 +20,8 @@ romstage-y += iosf.c
ramstage-y += northcluster.c
ramstage-y += ramstage.c
ramstage-y += gpio.c
+romstage-y += reset.c
+ramstage-y += reset.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h
index 2cf1f00..b85800a 100644
--- a/src/soc/intel/baytrail/baytrail/pmc.h
+++ b/src/soc/intel/baytrail/baytrail/pmc.h
@@ -26,6 +26,12 @@
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define GEN_PMCONF1 0x20
# define UART_EN (1 << 24)
+#define ETR 0x48
+# define CF9LOCK (1 << 31)
+# define LTR_DEF (1 << 22)
+# define IGNORE_HPET (1 << 21)
+# define CF9GR (1 << 20)
+# define CWORWRE (1 << 18)
/* IO Mapped registers behind ACPI_BASE_ADDRESS */
#define TCO_RLD 0x60
@@ -37,4 +43,10 @@
# define TCO_TMR_HALT (1 << 11)
#define TCO_TMR 0x70
+/* I/O ports */
+#define RST_CNT 0xcf9
+# define FULL_RST (1 << 3)
+# define RST_CPU (1 << 2)
+# define SYS_RST (1 << 1)
+
#endif /* _BAYTRAIL_PMC_H_ */
diff --git a/src/soc/intel/baytrail/baytrail/reset.h b/src/soc/intel/baytrail/baytrail/reset.h
new file mode 100644
index 0000000..dbf0fd2
--- /dev/null
+++ b/src/soc/intel/baytrail/baytrail/reset.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BAYTRAIL_RESET_H_
+#define _BAYTRAIL_RESET_H_
+#include <reset.h>
+
+/* Bay Trail has the following types of resets:
+ * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92
+ * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9
+ * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9
+ * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9
+ * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but
+ * with ETR[20] set.
+ */
+
+void cold_reset(void);
+void warm_reset(void);
+
+#endif /* _BAYTRAIL_RESET_H_ */
diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c
new file mode 100644
index 0000000..a421ec9
--- /dev/null
+++ b/src/soc/intel/baytrail/reset.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <baytrail/pmc.h>
+#include <baytrail/reset.h>
+
+void cold_reset(void)
+{
+ /* S0->S5->S0 trip. */
+ outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT);
+}
+
+void warm_reset(void)
+{
+ /* PMC_PLTRST# asserted. */
+ outb(RST_CPU | SYS_RST, RST_CNT);
+}
+
+void soft_reset(void)
+{
+ /* Sends INIT# to CPU */
+ outb(RST_CPU, RST_CNT);
+}
+
+void hard_reset(void)
+{
+ /* Don't power cycle on hard_reset(). It's not really clear what the
+ * semantics should be for the meaning of hard_reset(). */
+ warm_reset();
+}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4876
-gerrit
commit a944e4210bee5eb793953ec891951ab5b9ff9b59
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 10 20:37:04 2013 -0500
coreboot: config to cache ramstage outside CBMEM
Haswell was the original chipset to store the cache
in another area besides CBMEM. However, it was specific
to the implementation. Instead, provide a generic way
to obtain the location of the ramstage cache. This option
is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Kconfig option.
BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with baytrail support. Also built for
falco successfully.
CQ-DEPEND=CL:172643
CQ-DEPEND=CL:*146397
CQ-DEPEND=CL:*146398
CQ-DEPEND=CL:*146435
CQ-DEPEND=CL:*146445
Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172602
Reviewed-by: Stefan Reinauer <reinauer(a)google.com>
---
src/Kconfig | 8 +++
src/cpu/intel/haswell/haswell.h | 16 -----
src/cpu/intel/haswell/romstage.c | 66 +++---------------
src/include/ramstage_cache.h | 49 +++++++++++++
src/lib/Makefile.inc | 2 +
src/lib/cbfs.c | 47 -------------
src/lib/ramstage_cache.c | 144 +++++++++++++++++++++++++++++++++++++++
7 files changed, 213 insertions(+), 119 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index c6696af..7492e22 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -431,6 +431,14 @@ config RELOCATABLE_RAMSTAGE
wake. When selecting this option the romstage is responsible for
determing a stack location to use for loading the ramstage.
+config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+ depends on RELOCATABLE_RAMSTAGE
+ bool "Cache the relocated ramstage outside of cbmem."
+ default n
+ help
+ The relocated ramstage is saved in an area specified by the
+ by the board and/or chipset.
+
config HAVE_ACPI_TABLES
bool
help
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index dcd5dc7..190abc6 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -215,22 +215,6 @@ void release_aps_for_smm_relocation(int do_parallel_relocation);
extern int ht_disabled;
#endif
-/* This structure is saved along with the relocated ramstage program in SMM
- * space. It is used to protect the integrity of the ramstage program on S3
- * resume by saving a copy of the relocated ramstage in SMM space with the
- * assumption that the SMM region cannot be altered from the OS. The magic
- * value just serves as a quick sanity check. */
-
-#define RAMSTAGE_CACHE_MAGIC 0xf3c3a02a
-
-struct ramstage_cache {
- uint32_t magic;
- uint32_t entry_point;
- uint32_t load_address;
- uint32_t size;
- char program[0];
-} __attribute__((packed));
-
/* CPU identification */
int haswell_family_model(void);
int haswell_stepping(void);
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 40a396d..53c5987 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -33,6 +33,7 @@
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cbfs.h>
+#include <ramstage_cache.h>
#include <romstage_handoff.h>
#include <reset.h>
#if CONFIG_CHROMEOS
@@ -318,67 +319,20 @@ void romstage_after_car(void)
#if CONFIG_RELOCATABLE_RAMSTAGE
-void cache_loaded_ramstage(struct romstage_handoff *handoff,
- const struct cbmem_entry *ramstage,
- void *entry_point)
-{
- struct ramstage_cache *cache;
- uint32_t total_size;
- uint32_t ramstage_size;
- void *ramstage_base;
-
- ramstage_size = cbmem_entry_size(ramstage);
- ramstage_base = cbmem_entry_start(ramstage);
+#include <ramstage_cache.h>
+struct ramstage_cache *ramstage_cache_location(long *size)
+{
/* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
* The top of ram is defined to be the TSEG base address. */
- cache = (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET);
- total_size = sizeof(*cache) + ramstage_size;
- if (total_size > RESERVED_SMM_SIZE) {
- printk(BIOS_DEBUG, "0x%08x > RESERVED_SMM_SIZE (0x%08x)\n",
- total_size, RESERVED_SMM_SIZE);
- /* Nuke whatever may be there now just in case. */
- cache->magic = ~RAMSTAGE_CACHE_MAGIC;
- return;
- }
-
- cache->magic = RAMSTAGE_CACHE_MAGIC;
- cache->entry_point = (uint32_t)entry_point;
- cache->load_address = (uint32_t)ramstage_base;
- cache->size = ramstage_size;
-
- printk(BIOS_DEBUG, "Saving ramstage to SMM space cache.\n");
-
- /* Copy over the program. */
- memcpy(&cache->program[0], ramstage_base, ramstage_size);
-
- if (handoff == NULL)
- return;
-
- handoff->ramstage_entry_point = (uint32_t)entry_point;
+ *size = RESERVED_SMM_SIZE;
+ return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET);
}
-void *load_cached_ramstage(struct romstage_handoff *handoff,
- const struct cbmem_entry *ramstage)
+void ramstage_cache_invalid(struct ramstage_cache *cache)
{
- struct ramstage_cache *cache;
-
- /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
- * The top of ram is defined to be the TSEG base address. */
- cache = (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET);
-
- if (cache->magic != RAMSTAGE_CACHE_MAGIC) {
- printk(BIOS_DEBUG, "Invalid ramstage cache found.\n");
- #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
- reset_system();
- #endif
- return NULL;
- }
-
- printk(BIOS_DEBUG, "Loading ramstage from SMM space cache.\n");
-
- memcpy((void *)cache->load_address, &cache->program[0], cache->size);
-
- return (void *)cache->entry_point;
+#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
+ reset_system();
+#endif
}
#endif
diff --git a/src/include/ramstage_cache.h b/src/include/ramstage_cache.h
new file mode 100644
index 0000000..5b0597a
--- /dev/null
+++ b/src/include/ramstage_cache.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _RAMSTAGE_CACHE_
+#define _RAMSTAGE_CACHE_
+
+#if !defined(__PRE_RAM__)
+#error "ramstage_cache only used in romstage for loading ramstage."
+#endif
+
+/* This structure is saved along with the relocated ramstage program when
+ * CONFIG_RELOCATED_RAMSTAGE is employed. For x86, it can used to protect
+ * the integrity of the ramstage program on S3 resume by saving a copy of
+ * the relocated ramstage in SMM space with the assumption that the SMM region
+ * cannot be altered from the OS. The magic value just serves as a quick sanity
+ * check. */
+
+#define RAMSTAGE_CACHE_MAGIC 0xf3c3a02a
+
+struct ramstage_cache {
+ uint32_t magic;
+ uint32_t entry_point;
+ uint32_t load_address;
+ uint32_t size;
+ char program[0];
+} __attribute__((packed));
+
+/* Chipset/Board function for obtaining cache location and size. */
+struct ramstage_cache *ramstage_cache_location(long *size);
+/* Chipset/Board function called when cache is invalid on resume. */
+void ramstage_cache_invalid(struct ramstage_cache *cache);
+
+#endif /* _RAMSTAGE_CACHE_ */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 37c7dea..18b30ef 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -119,6 +119,8 @@ romstage-y += hexdump.c
ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c
+
ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
smm-y += memset.c
endif
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index e38f856..396fe33 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -127,53 +127,6 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor,
#include <rmodule.h>
#include <romstage_handoff.h>
-/* When CONFIG_RELOCATABLE_RAMSTAGE is enabled and this file is being compiled
- * for the romstage, the rmodule loader is used. */
-void __attribute__((weak))
-cache_loaded_ramstage(struct romstage_handoff *handoff,
- const struct cbmem_entry *ramstage, void *entry_point)
-{
- uint32_t ramstage_size;
- const struct cbmem_entry *entry;
-
- if (handoff == NULL)
- return;
-
- ramstage_size = cbmem_entry_size(ramstage);
- /* cbmem_entry_add() does a find() before add(). */
- entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE_CACHE, ramstage_size);
-
- if (entry == NULL)
- return;
-
- /* Keep track of the entry point in the handoff structure. */
- handoff->ramstage_entry_point = (uint32_t)entry_point;
-
- memcpy(cbmem_entry_start(entry), cbmem_entry_start(ramstage),
- ramstage_size);
-}
-
-void * __attribute__((weak))
-load_cached_ramstage(struct romstage_handoff *handoff,
- const struct cbmem_entry *ramstage)
-{
- const struct cbmem_entry *entry_cache;
-
- if (handoff == NULL)
- return NULL;
-
- entry_cache = cbmem_entry_find(CBMEM_ID_RAMSTAGE_CACHE);
-
- if (entry_cache == NULL)
- return NULL;
-
- /* Load the cached ramstage copy into the to-be-run region. */
- memcpy(cbmem_entry_start(ramstage), cbmem_entry_start(entry_cache),
- cbmem_entry_size(ramstage));
-
- return (void *)handoff->ramstage_entry_point;
-}
-
static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name,
struct romstage_handoff *handoff)
{
diff --git a/src/lib/ramstage_cache.c b/src/lib/ramstage_cache.c
new file mode 100644
index 0000000..a1a4804
--- /dev/null
+++ b/src/lib/ramstage_cache.c
@@ -0,0 +1,144 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stddef.h>
+#include <string.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <ramstage_cache.h>
+#include <romstage_handoff.h>
+
+#if CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
+
+void cache_loaded_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage,
+ void *entry_point)
+{
+ struct ramstage_cache *cache;
+ uint32_t total_size;
+ uint32_t ramstage_size;
+ void *ramstage_base;
+ long cache_size = 0;
+
+ ramstage_size = cbmem_entry_size(ramstage);
+ ramstage_base = cbmem_entry_start(ramstage);
+
+ cache = ramstage_cache_location(&cache_size);
+
+ if (cache == NULL) {
+ printk(BIOS_DEBUG, "No ramstage cache location provided.\n");
+ return;
+ }
+
+ total_size = sizeof(*cache) + ramstage_size;
+ if (total_size > cache_size) {
+ printk(BIOS_DEBUG, "cache size too small: 0x%08x > 0x%08lx\n",
+ total_size, cache_size);
+ /* Nuke whatever may be there now just in case. */
+ cache->magic = ~RAMSTAGE_CACHE_MAGIC;
+ return;
+ }
+
+ cache->magic = RAMSTAGE_CACHE_MAGIC;
+ cache->entry_point = (uint32_t)entry_point;
+ cache->load_address = (uint32_t)ramstage_base;
+ cache->size = ramstage_size;
+
+ printk(BIOS_DEBUG, "Saving ramstage to %p.\n", cache);
+
+ /* Copy over the program. */
+ memcpy(&cache->program[0], ramstage_base, ramstage_size);
+
+ if (handoff == NULL)
+ return;
+
+ handoff->ramstage_entry_point = (uint32_t)entry_point;
+}
+
+void *load_cached_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage)
+{
+ struct ramstage_cache *cache;
+ long size = 0;
+
+ cache = ramstage_cache_location(&size);
+
+ if (cache == NULL || cache->magic != RAMSTAGE_CACHE_MAGIC) {
+ printk(BIOS_DEBUG, "Invalid ramstage cache found.\n");
+ ramstage_cache_invalid(cache);
+ return NULL;
+ }
+
+ printk(BIOS_DEBUG, "Loading ramstage from %p.\n", cache);
+
+ memcpy((void *)cache->load_address, &cache->program[0], cache->size);
+
+ return (void *)cache->entry_point;
+}
+
+#else
+
+/* Cache relocated ramstage in CBMEM. */
+
+void __attribute__((weak))
+cache_loaded_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage, void *entry_point)
+{
+ uint32_t ramstage_size;
+ const struct cbmem_entry *entry;
+
+ if (handoff == NULL)
+ return;
+
+ ramstage_size = cbmem_entry_size(ramstage);
+ /* cbmem_entry_add() does a find() before add(). */
+ entry = cbmem_entry_add(CBMEM_ID_RAMSTAGE_CACHE, ramstage_size);
+
+ if (entry == NULL)
+ return;
+
+ /* Keep track of the entry point in the handoff structure. */
+ handoff->ramstage_entry_point = (uint32_t)entry_point;
+
+ memcpy(cbmem_entry_start(entry), cbmem_entry_start(ramstage),
+ ramstage_size);
+}
+
+void * __attribute__((weak))
+load_cached_ramstage(struct romstage_handoff *handoff,
+ const struct cbmem_entry *ramstage)
+{
+ const struct cbmem_entry *entry_cache;
+
+ if (handoff == NULL)
+ return NULL;
+
+ entry_cache = cbmem_entry_find(CBMEM_ID_RAMSTAGE_CACHE);
+
+ if (entry_cache == NULL)
+ return NULL;
+
+ /* Load the cached ramstage copy into the to-be-run region. */
+ memcpy(cbmem_entry_start(ramstage), cbmem_entry_start(entry_cache),
+ cbmem_entry_size(ramstage));
+
+ return (void *)handoff->ramstage_entry_point;
+}
+
+#endif
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4871
-gerrit
commit 9c79a1793db760d4b3dc4fcaf59e4ccc9ce522a2
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Oct 8 16:54:18 2013 -0500
baytrail: move early init to before mainboard
It's helpful to have a lot of the early init happen
before the handoff to mainboard. One example of this
need is having the BARs programmed so that the mainboard
can read board-specific gpios.
BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built. Booted and saw console outout in bayleybay
mainboard.
Signed-off-by; Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I030d7b4f9061ad7501049e8e204ea12255061fbe
Reviewed-on: https://chromium-review.googlesource.com/172290
Tested-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Commit-Queue: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/baytrail/romstage/romstage.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 0035019..4228615 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -107,17 +107,6 @@ void * asmlinkage romstage_main(unsigned long bist,
/* Save romstage begin */
mark_ts(&rp, timestamp_get());
- /* Call into mainboard. */
- mainboard_romstage_entry(&rp);
-
- return setup_stack_and_mttrs();
-}
-
-/* Entry from the mainboard. */
-void romstage_common(struct romstage_params *params)
-{
- struct romstage_handoff *handoff;
-
program_base_addresses();
tco_disable();
@@ -132,6 +121,17 @@ void romstage_common(struct romstage_params *params)
gfx_init();
+ /* Call into mainboard. */
+ mainboard_romstage_entry(&rp);
+
+ return setup_stack_and_mttrs();
+}
+
+/* Entry from the mainboard. */
+void romstage_common(struct romstage_params *params)
+{
+ struct romstage_handoff *handoff;
+
mark_ts(params, timestamp_get());
/* Initialize RAM */