Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4850
-gerrit
commit 6c32a2c2125ac1129abf6929274c98f01b605f70
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Sep 24 12:36:14 2013 -0500
baytrail: initialize graphics before MRC
The graphics device needs to have its resource contraints
initialized before running the reference code. Right now just
use a 256MiB aperture, 32MiB of stolen memory data, and 2MiB
GTT memory.
BUG=chrome-os-partner:22869
BRANCH=None
TEST=Built and booted. Noted amount of stolen memory matches
configuration as well as BAR size within the graphics
device.
Change-Id: I328bf858f288363187cf705d6340947393b5ff10
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170427
---
src/soc/intel/baytrail/baytrail/gfx.h | 48 +++++++++++++++++++++++++++
src/soc/intel/baytrail/baytrail/romstage.h | 1 +
src/soc/intel/baytrail/romstage/Makefile.inc | 1 +
src/soc/intel/baytrail/romstage/gfx.c | 49 ++++++++++++++++++++++++++++
src/soc/intel/baytrail/romstage/romstage.c | 2 ++
5 files changed, 101 insertions(+)
diff --git a/src/soc/intel/baytrail/baytrail/gfx.h b/src/soc/intel/baytrail/baytrail/gfx.h
new file mode 100644
index 0000000..655615d
--- /dev/null
+++ b/src/soc/intel/baytrail/baytrail/gfx.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _BAYTRAIL_GFX_H_
+#define _BAYTRAIL_GFX_H_
+
+/*
+ * PCI config registers.
+ */
+
+#define GGC 0x50
+# define GGC_VGA_DISABLE (1 << 1)
+# define GGC_GTT_SIZE_MASK (3 << 8)
+# define GGC_GTT_SIZE_0MB (0 << 8)
+# define GGC_GTT_SIZE_1MB (1 << 8)
+# define GGC_GTT_SIZE_2MB (2 << 8)
+# define GGC_GSM_SIZE_MASK (0x1f << 3)
+# define GGC_GSM_SIZE_0MB (0 << 3)
+# define GGC_GSM_SIZE_32MB (1 << 3)
+# define GGC_GSM_SIZE_64MB (2 << 3)
+# define GGC_GSM_SIZE_128MB (4 << 3)
+
+#define GSM_BASE 0x5c
+#define GTT_BASE 0x70
+
+#define MSAC 0x62
+#define APERTURE_SIZE_MASK (3 << 1)
+#define APERTURE_SIZE_128MB (0 << 1)
+#define APERTURE_SIZE_256MB (1 << 1)
+#define APERTURE_SIZE_512MB (3 << 1)
+
+#endif /* _BAYTRAIL_GFX_H_ */
diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h
index b0755e5..6c622e1 100644
--- a/src/soc/intel/baytrail/baytrail/romstage.h
+++ b/src/soc/intel/baytrail/baytrail/romstage.h
@@ -36,6 +36,7 @@ void romstage_common(const struct romstage_params *params);
void * asmlinkage romstage_main(unsigned long bist);
void asmlinkage romstage_after_car(void);
void raminit(struct mrc_params *mp, int prev_sleep_state);
+void gfx_init(void);
#if CONFIG_ENABLE_BUILTIN_COM1
void byt_config_com1_and_enable(void);
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc
index 18e4608..912298d 100644
--- a/src/soc/intel/baytrail/romstage/Makefile.inc
+++ b/src/soc/intel/baytrail/romstage/Makefile.inc
@@ -1,4 +1,5 @@
cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc
romstage-y += romstage.c
romstage-y += raminit.c
+romstage-y += gfx.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com1.c
diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c
new file mode 100644
index 0000000..3b47ccf
--- /dev/null
+++ b/src/soc/intel/baytrail/romstage/gfx.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <baytrail/gfx.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/romstage.h>
+
+void gfx_init(void)
+{
+ uint32_t ggc;
+ uint8_t msac;
+ const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC);
+
+ /* The GFX device needs to set the aperture, gtt stolen size, and
+ * graphics stolen memory stolen size before running MRC. For now
+ * just hard code the defaults. Options can be added to the device
+ * tree if needed. */
+
+ ggc = pci_read_config32(gfx_dev, GGC);
+ msac = pci_read_config8(gfx_dev, MSAC);
+
+ ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK);
+ ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_32MB;
+ /* Enable VGA decoding as well. */
+ ggc &= ~(GGC_VGA_DISABLE);
+
+ msac &= ~(APERTURE_SIZE_MASK);
+ msac |= APERTURE_SIZE_256MB;
+
+ pci_write_config32(gfx_dev, GGC, ggc);
+ pci_write_config8(gfx_dev, MSAC, msac);
+}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index d353899..e4e6fde 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -89,6 +89,8 @@ void romstage_common(const struct romstage_params *params)
console_init();
+ gfx_init();
+
/* Initialize RAM */
raminit(params->mrc_params, 5);
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4846
-gerrit
commit 79f1fafc293f312a6412d15f78f9a7fa4b4b941b
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 27 16:39:17 2014 -0600
x86/mtrr: don't assume size of ROM cached during CAR mode
Romstage and ramstage can use 2 different values for the
amount of ROM to cache just under 4GiB in the address
space. Don't assume a cpu's romstage caching policy
for the ROM.
Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/include/cpu/x86/mtrr.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index bbcde8a..9414687 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -134,10 +134,6 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type);
#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
-#if ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) * 1UL > CACHE_ROM_BASE * 1UL)
-# error "CAR region (WB) and flash (WP) regions overlap."
-#endif
-
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
#endif
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4844
-gerrit
commit 0b7aa722e85aee19c612103c51a7bbcc73012091
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 27 15:08:27 2014 -0600
chromeos: include stddef to fix compilation error
As some of the standard definitions were shuffled around
chromeos started failing to build. Correct this.
Change-Id: I9927441ccb2d646e8b3395e6e9f8e8166de74ab0
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/vendorcode/google/chromeos/chromeos.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index ae715dc..f51215e 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -20,6 +20,7 @@
#ifndef __CHROMEOS_H__
#define __CHROMEOS_H__
+#include <stddef.h>
#include <stdint.h>
/* functions implemented per mainboard: */
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4843
-gerrit
commit 11e496b6c605e8b292f1b8179500551ba2db84a2
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 27 15:07:26 2014 -0600
x86: include header to define types in use
The tsc header is using u32 w/o including the file
with defines it.
Change-Id: I9fcad882d25e93b4c0032b32abd2432b0169a068
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/include/cpu/x86/tsc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 66451ad..7323599 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -1,6 +1,8 @@
#ifndef CPU_X86_TSC_H
#define CPU_X86_TSC_H
+#include <stdint.h>
+
#if CONFIG_TSC_SYNC_MFENCE
#define TSC_SYNC "mfence\n"
#elif CONFIG_TSC_SYNC_LFENCE