Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4898
-gerrit
commit d7d218bf31f0ef05b62d1dc120ad0528f7c9552b
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 10:21:43 2013 -0500
baytrail: add support to run reference code blob
The reference code blog is needed to bootstrap
certain pieces of hardware in bay trail. Provide
the ability to run reference code by loading
the reference code as an rmodule.
Note that support for vboot verification and S3
resume is omitted from this commit.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted with refcode loading.
Change-Id: I30334db441a57f4d87b4de6fca0a9a48e1c05c05
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174426
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/Makefile.inc | 1 +
src/soc/intel/baytrail/baytrail/efi_wrapper.h | 50 ++++++++++++++++++++++
src/soc/intel/baytrail/baytrail/ramstage.h | 5 +++
src/soc/intel/baytrail/ramstage.c | 3 ++
src/soc/intel/baytrail/refcode.c | 60 +++++++++++++++++++++++++++
5 files changed, 119 insertions(+)
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index f913f0c..455f015 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -31,6 +31,7 @@ smm-y += pmutil.c
smm-y += smihandler.c
ramstage-y += smm.c
ramstage-y += southcluster.c
+ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/baytrail/efi_wrapper.h b/src/soc/intel/baytrail/baytrail/efi_wrapper.h
new file mode 100644
index 0000000..6682f95
--- /dev/null
+++ b/src/soc/intel/baytrail/baytrail/efi_wrapper.h
@@ -0,0 +1,50 @@
+/*
+ * PEI EFI entry point
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Google Inc. nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __EFI_WRAPPER_H__
+#define __EFI_WRAPPER_H__
+
+#define EFI_WRAPPER_VER 1
+
+/* Provide generic x86 calling conventions. */
+#define ABI_X86 __attribute((regparm(0)))
+
+/* Errors returned by the EFI wrapper. */
+enum efi_wrapper_error {
+ INVALID_VER = -1,
+};
+
+struct efi_wrapper_params {
+ /* Mainboard Inputs */
+ int version;
+
+ void ABI_X86 (*console_out)(unsigned char byte);
+} __attribute__((packed));
+
+typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *);
+#endif
diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h
index 790b8c6..eaa8f6b 100644
--- a/src/soc/intel/baytrail/baytrail/ramstage.h
+++ b/src/soc/intel/baytrail/baytrail/ramstage.h
@@ -27,6 +27,11 @@
void baytrail_init_pre_device(void);
void baytrail_init_cpus(device_t dev);
void set_max_freq(void);
+#if CONFIG_HAVE_REFCODE_BLOB
+void baytrail_run_reference_code(void);
+#else
+static inline void baytrail_run_reference_code(void) {}
+#endif
extern struct pci_operations soc_pci_ops;
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 229e367..896ecfe 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -113,6 +113,9 @@ void baytrail_init_pre_device(void)
/* Allow for SSE instructions to be executed. */
write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT);
+ /* Run reference code. */
+ baytrail_run_reference_code();
+
/* Get GPIO initial states from mainboard */
config = mainboard_get_gpios();
setup_soc_gpios(config);
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
new file mode 100644
index 0000000..59e3c4c
--- /dev/null
+++ b/src/soc/intel/baytrail/refcode.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <rmodule.h>
+
+#include <baytrail/ramstage.h>
+#include <baytrail/efi_wrapper.h>
+
+static void ABI_X86 send_to_console(unsigned char b)
+{
+ console_tx_byte(b);
+}
+
+void baytrail_run_reference_code(void)
+{
+ int ret;
+ efi_wrapper_entry_t entry;
+ struct efi_wrapper_params wrp = {
+ .version = EFI_WRAPPER_VER,
+ .console_out = send_to_console,
+ };
+ struct rmod_stage_load refcode = {
+ .cbmem_id = CBMEM_ID_REFCODE,
+ .name = "fallback/refcode",
+ };
+
+ if (rmodule_stage_load_from_cbfs(&refcode) || refcode.entry == NULL) {
+ printk(BIOS_DEBUG, "Error loading reference code.\n");
+ return;
+ }
+
+ entry = refcode.entry;
+
+ /* Call into reference code. */
+ ret = entry(&wrp);
+
+ if (ret != 0) {
+ printk(BIOS_DEBUG, "Reference code returned %d\n", ret);
+ return;
+ }
+}
+
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4895
-gerrit
commit 064ec204eba3e476a1d258b7c990199c894cd0fb
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 08:55:51 2013 -0500
x86: add HAVE_REFCODE_BLOB option
In order to incorporate external blobs into
CBFS besides MRC have a notion of a reference code
blob. By selecting HAVE_REFCODE_BLOB and providing
the file name the refcode blob will be added to
cbfs as a stage file.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Using this option and other patches able to build,
boot, and run blob code.
Change-Id: I472604d77f4cb48f286b5a76b25d8b5bfb0c7780
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174423
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/Kconfig | 17 +++++++++++++++++
src/arch/x86/Makefile.inc | 3 +++
2 files changed, 20 insertions(+)
diff --git a/src/Kconfig b/src/Kconfig
index 7492e22..31a41ab 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -439,6 +439,23 @@ config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
The relocated ramstage is saved in an area specified by the
by the board and/or chipset.
+config HAVE_REFCODE_BLOB
+ depends on ARCH_X86
+ bool "An external reference code blob should be put into cbfs."
+ default n
+ help
+ The reference code blob will be placed into cbfs.
+
+if HAVE_REFCODE_BLOB
+
+config REFCODE_BLOB_FILE
+ string "Path and filename to reference code blob."
+ default "refcode.elf"
+ help
+ The path and filename to the file to be added to cbfs.
+
+endif # HAVE_REFCODE_BLOB
+
config HAVE_ACPI_TABLES
bool
help
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 2ade820..80e731f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -136,6 +136,9 @@ endif
ifeq ($(CONFIG_VBOOT_VERIFY_FIRMWARE),y)
$(CBFSTOOL) $@.tmp add-stage -f $(VBOOT_STUB_ELF) -n $(CONFIG_CBFS_PREFIX)/vboot -c $(CBFS_COMPRESS_FLAG)
endif
+ifeq ($(CONFIG_HAVE_REFCODE_BLOB),y)
+ $(CBFSTOOL) $@.tmp add-stage -f $(CONFIG_REFCODE_BLOB_FILE) -n $(CONFIG_CBFS_PREFIX)/refcode -c $(CBFS_COMPRESS_FLAG)
+endif
ifeq ($(CONFIG_PXE_ROM),y)
$(CBFSTOOL) $@.tmp add -f $(CONFIG_PXE_ROM_FILE) -n pci$(CONFIG_PXE_ROM_ID).rom -t raw
endif
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4893
-gerrit
commit d788781bd3dc6580570672051fc06d6818ba6c0e
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 00:05:31 2013 -0500
baytrail: add south cluster fixed resources
The PCU (platform controller unit) contains the
resources and IP blocks that used to reside in the
south bridge. Bay Trail has since renamed it south
cluster. There are quite a few fixed MMIO and I/O
resources. If these aren't added the resource allocator
will freely assign these addresses which causes conflicts
and other subtle bugs.
BUG=chrome-os-partner:23544
BUG=chrome-os-partner:23545
BRANCH=None
TEST=Built and booted through depthcharge. Verified
resource allocation not weird. And no more depthcharge
crashes.
Change-Id: I697fbda4538c03fded293bcb63a5823b1ed150ec
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174421
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/Makefile.inc | 1 +
src/soc/intel/baytrail/southcluster.c | 130 ++++++++++++++++++++++++++++++++++
2 files changed, 131 insertions(+)
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 9711549..f913f0c 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -30,6 +30,7 @@ ramstage-y += pmutil.c
smm-y += pmutil.c
smm-y += smihandler.c
ramstage-y += smm.c
+ramstage-y += southcluster.c
# Remove as ramstage gets fleshed out
ramstage-y += placeholders.c
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
new file mode 100644
index 0000000..32b8799
--- /dev/null
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -0,0 +1,130 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <romstage_handoff.h>
+
+#include <baytrail/iomap.h>
+#include <baytrail/lpc.h>
+#include <baytrail/nvs.h>
+#include <baytrail/pci_devs.h>
+#include <baytrail/ramstage.h>
+
+static inline void
+add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
+{
+ mmio_resource(dev, i, addr >> 10, size >> 10);
+}
+
+static void sc_add_mmio_resources(device_t dev)
+{
+ add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, 1024);
+ add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, 16 * 1024);
+ add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, 1024);
+ add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, 1024);
+ add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, 1024 * 1024);
+ add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, 2048);
+ add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, 1024);
+}
+
+/* Default IO range claimed by the LPC device. The upper bound is exclusive. */
+#define LPC_DEFAULT_IO_RANGE_LOWER 0
+#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
+
+static inline int io_range_in_default(int base, int size)
+{
+ /* Does it start above the range? */
+ if (base >= LPC_DEFAULT_IO_RANGE_UPPER)
+ return 0;
+
+ /* Is it entirely contained? */
+ if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
+ (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
+ return 1;
+
+ /* This will return not in range for partial overlaps. */
+ return 0;
+}
+
+/*
+ * Note: this function assumes there is no overlap with the default LPC device's
+ * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
+ */
+static void sc_add_io_resource(device_t dev, int base, int size, int index)
+{
+ struct resource *res;
+
+ if (io_range_in_default(base, size))
+ return;
+
+ res = new_resource(dev, index);
+ res->base = base;
+ res->size = size;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void sc_add_io_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Add the default claimed IO range for the LPC device. */
+ res = new_resource(dev, 0);
+ res->base = LPC_DEFAULT_IO_RANGE_LOWER;
+ res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
+ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ /* GPIO */
+ sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE);
+
+ /* ACPI */
+ sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE);
+}
+
+static void sc_read_resources(device_t dev)
+{
+ /* Get the normal PCI resources of this device. */
+ pci_dev_read_resources(dev);
+
+ /* Add non-standard MMIO resources. */
+ sc_add_mmio_resources(dev);
+
+ /* Add IO resources. */
+ sc_add_io_resources(dev);
+}
+
+static struct device_operations device_ops = {
+ .read_resources = sc_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .enable = NULL,
+ .scan_bus = NULL,
+ .ops_pci = &soc_pci_ops,
+};
+
+static const struct pci_driver southcluster __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = LPC_DEVID,
+};