coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 94b0c3d amd/cimx: fix sb(8|9)00 NULL type redefine
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5088 -gerrit commit 94b0c3dd50d85a841cb168e919c2fc358a8c32a7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 22:20:01 2014 -0600 amd/cimx: fix sb(8|9)00 NULL type redefine It is inappropriate for chipset code to be redefining types -- especially NULL to a non-pointer type. Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 6 +----- src/southbridge/amd/cimx/sb900/SbPlatform.h | 6 +----- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index fa7d196..ea3f719 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -24,11 +24,7 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -//#include "cbtypes.h" -#ifdef NULL - #undef NULL -#endif -#define NULL 0 +#include <stddef.h> typedef unsigned long long PLACEHOLDER; diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 5e41978..176ad87 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -24,11 +24,7 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -//#include "cbtypes.h" -#ifdef NULL - #undef NULL -#endif -#define NULL 0 +#include <stddef.h> typedef unsigned long long PLACEHOLDER;

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Patch set updated for coreboot: 60a69e2 coreboot: infrastructure for different ramstage loaders
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5087 -gerrit commit 60a69e2d0db80f259ff62d54f74aa29fc95e6ad5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 17:19:46 2014 -0600 coreboot: infrastructure for different ramstage loaders WARNING: Not compile tested. proof of concept. There are 2 methods currently avaiable in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/lib/cbfs_and_run.c | 21 +----- src/cpu/intel/haswell/romstage.c | 2 - src/include/cbfs.h | 22 +++++- src/include/cbmem.h | 5 ++ src/include/ramstage_loader.h | 34 +++++++++ src/include/romstage_handoff.h | 10 ++- src/lib/Makefile.inc | 1 + src/lib/cbfs.c | 53 -------------- src/lib/loaders/Makefile.inc | 21 ++++++ src/lib/loaders/cbfs_ramstage_loader.c | 67 +++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 100 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/chromeos.h | 4 -- src/vendorcode/google/chromeos/vboot_loader.c | 86 ++++++++++------------ 13 files changed, 296 insertions(+), 130 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 3d56e19..ca8d61b 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -17,27 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <cbfs.h> #include <arch/stages.h> -#include <timestamp.h> - -static void cbfs_and_run_core(const char *filename) -{ - u8 *dst; - - timestamp_add_now(TS_START_COPYRAM); - print_debug("Loading image.\n"); - dst = cbfs_load_stage(CBFS_DEFAULT_MEDIA, filename); - if ((void *)dst == (void *) -1) - die("FATAL: Essential component is missing.\n"); - - timestamp_add_now(TS_END_COPYRAM); - print_debug("Jumping to image.\n"); - stage_exit(dst); -} +#include <ramstage_loader.h> void asmlinkage copy_and_run(void) { - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram"); + run_ramstage(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 60a1c3a..9e27668 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -309,8 +309,6 @@ void romstage_after_car(void) prepare_for_resume(handoff); - vboot_verify_firmware(handoff); - /* Load the ramstage. */ copy_and_run(); } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index c05566d..9ce862b 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -83,6 +83,10 @@ void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); +#if defined(__PRE_RAM__) +struct romstage_handoff; +struct cbmem_entry; + #if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) /* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined * to be weak so that board and chipset code may override them. Their job is to @@ -90,9 +94,6 @@ int init_default_cbfs_media(struct cbfs_media *media); * relocated ramstage is saved using the cbmem infrastructure. These * functions are only valid during romstage. */ -struct romstage_handoff; -struct cbmem_entry; - /* The implementer of cache_loaded_ramstage() may use the romstage_handoff * structure to store information, but note that the handoff variable can be * NULL. The ramstage cbmem_entry represents the region occupied by the loaded @@ -105,7 +106,22 @@ cache_loaded_ramstage(struct romstage_handoff *handoff, void * __attribute__((weak)) load_cached_ramstage(struct romstage_handoff *handoff, const struct cbmem_entry *ramstage); +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static inline void cache_loaded_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage, void *entry_point) +{ +} + +static inline void * +load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage) +{ + return NULL; +} + #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ +#endif /* defined(__PRE_RAM__) */ #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9e68ba9..0b6031e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -66,6 +66,7 @@ #define CBMEM_ID_HOB_POINTER 0x484f4221 #ifndef __ASSEMBLER__ +#include <stddef.h> #include <stdint.h> struct cbmem_entry; @@ -150,6 +151,10 @@ void cbmem_late_set_table(uint64_t base, uint64_t size); void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); +static inline const struct cbmem_entry *cbmem_entry_find(u32 id) +{ + return NULL; +} #endif /* CONFIG_DYNAMIC_CBMEM */ /* Common API between cbmem and dynamic cbmem. */ diff --git a/src/include/ramstage_loader.h b/src/include/ramstage_loader.h new file mode 100644 index 0000000..67003d4 --- /dev/null +++ b/src/include/ramstage_loader.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 20l4 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef RAMSTAGE_LOADER_H +#define RAMSTAGE_LOADER_H + +#include <stdint.h> +struct cbmem_entry; + +/* Run ramstage from romstage. */ +void run_ramstage(void); + +struct ramstage_loader_ops { + const char *name; + void *(*load)(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry); +}; + +#endif /* RAMSTAGE_LOADER_H */ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 699838a..307babd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -41,6 +41,7 @@ struct romstage_handoff { }; #if defined(__PRE_RAM__) +#if CONFIG_EARLY_CBMEM_INIT /* The romstage_handoff_find_or_add() function provides the necessary logic * for initializing the romstage_handoff structure in cbmem. Different components * of the romstage may be responsible for setting up different fields. Therefore @@ -63,7 +64,14 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) return handoff; } -#endif +#else /* CONFIG_EARLY_CBMEM_INIT */ +static inline struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + return NULL; +} +#endif /* CONFIG_EARLY_CBMEM_INIT */ + +#endif /* defined(__PRE_RAM__) */ #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 18b30ef..55a946f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -16,6 +16,7 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-y += loaders bootblock-y += cbfs.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..f2a2587 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -123,58 +123,6 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -#if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) - -#include <rmodule.h> -#include <romstage_handoff.h> -static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, - struct romstage_handoff *handoff) -{ - struct rmod_stage_load rmod_ram = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = name, - }; - - if (rmodule_stage_load_from_cbfs(&rmod_ram)) { - printk(BIOS_DEBUG, "Could not load ramstage.\n"); - return (void *) -1; - } - - cache_loaded_ramstage(handoff, rmod_ram.cbmem_entry, rmod_ram.entry); - - return rmod_ram.entry; -} - -void * cbfs_load_stage(struct cbfs_media *media, const char *name) -{ - struct romstage_handoff *handoff; - const struct cbmem_entry *ramstage; - void *entry; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) { - LOG("Couldn't find or allocate romstage handoff.\n"); - return load_stage_from_cbfs(media, name, handoff); - } else if (!handoff->s3_resume) - return load_stage_from_cbfs(media, name, handoff); - - ramstage = cbmem_entry_find(CBMEM_ID_RAMSTAGE); - - if (ramstage == NULL) - return load_stage_from_cbfs(media, name, handoff); - - /* S3 resume path. Load a cached copy of the loaded ramstage. If - * return value is NULL load from cbfs. */ - entry = load_cached_ramstage(handoff, ramstage); - if (entry == NULL) - return load_stage_from_cbfs(media, name, handoff); - - return entry; -} - -#else - void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) @@ -211,7 +159,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ #if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc new file mode 100644 index 0000000..eceaa00 --- /dev/null +++ b/src/lib/loaders/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += cbfs_ramstage_loader.c +romstage-y += load_and_run_ramstage.c diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c new file mode 100644 index 0000000..6e5fe8e --- /dev/null +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <cbfs.h> +#include <arch/stages.h> +#include <ramstage_loader.h> +#include <timestamp.h> + +#if CONFIG_RELOCATABLE_RAMSTAGE +#include <rmodule.h> + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **entry) +{ + struct rmod_stage_load rmod_ram = { + .cbmem_id = cbmem_id, + .name = name, + }; + + if (rmodule_stage_load_from_cbfs(&rmod_ram)) { + printk(BIOS_DEBUG, "Could not load ramstage.\n"); + return NULL; + } + + *cbmem_entry = rmod_ram.cbmem_entry; + + return rmod_ram.entry; +} + +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name); + + if ((void *)entry == (void *) -1) + entry = NULL; + + return entry; +} + +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ + +const struct ramstage_loader_ops cbfs_ramstage_loader = { + .name = "CBFS", + .load = cbfs_load_ramstage, +}; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c new file mode 100644 index 0000000..a4c400a --- /dev/null +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 20l4 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <cbmem.h> +#include <ramstage_loader.h> +#include <romstage_handoff.h> +#include <timestamp.h> + +extern const struct ramstage_loader_ops cbfs_ramstage_loader; +extern const struct ramstage_loader_ops vboot_ramstage_loader; + +static const struct ramstage_loader_ops *loaders[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_ramstage_loader, +#endif + &cbfs_ramstage_loader, +}; + +static const char *ramstage_name = CONFIG_CBFS_PREFIX "/coreboot_ram"; +static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; + +static void +load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) +{ + const struct cbmem_entry *cbmem_entry; + void *entry_point; + + timestamp_add_now(TS_START_COPYRAM); + entry_point = ops->load(ramstage_id, ramstage_name, &cbmem_entry); + + if (entry_point == NULL) + return; + + cache_loaded_ramstage(handoff, cbmem_entry, entry_point); + + timestamp_add_now(TS_END_COPYRAM); + + stage_exit(entry_point); +} + +static void run_ramstage_from_resume(struct romstage_handoff *handoff) +{ + void *entry; + const struct cbmem_entry *cbmem_entry; + + if (handoff != NULL && handoff->s3_resume) { + cbmem_entry = cbmem_entry_find(ramstage_id); + + /* No place to load ramstage. */ + if (cbmem_entry == NULL) + return; + + /* Load the cached ramstage to runtime location. */ + entry = load_cached_ramstage(handoff, cbmem_entry); + + if (entry != NULL) { + print_debug("Jumping to image.\n"); + stage_exit(entry); + } + } +} + +void run_ramstage(void) +{ + struct romstage_handoff *handoff; + const struct ramstage_loader_ops *ops; + int i; + + handoff = romstage_handoff_find_or_add(); + + run_ramstage_from_resume(handoff); + + for (i = 0; i < ARRAY_SIZE(loaders); i++) { + ops = loaders[i]; + printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); + load_ramstage(ops, handoff); + } + + die("Ramstage was not loaded!\n"); +} diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 5493801..0359c91 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,14 +46,10 @@ int recovery_mode_enabled(void); /* functions implemented in vboot.c */ void init_chromeos(int bootmode); -struct romstage_handoff; #if CONFIG_VBOOT_VERIFY_FIRMWARE -void vboot_verify_firmware(struct romstage_handoff *handoff); void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); -#else -static inline void vboot_verify_firmware(struct romstage_handoff *h) {} #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index cc7c25d..2094657 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -141,27 +141,52 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) vboot_run_stub(&context); } -static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, - struct romstage_handoff *handoff) +static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **entry) { + struct vboot_handoff *vboot_handoff; struct cbfs_stage *stage; const struct firmware_component *fwc; struct rmod_stage_load rmod_load = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = CONFIG_CBFS_PREFIX "/coreboot_ram", + .cbmem_id = cbmem_id, + .name = name, }; + timestamp_add_now(TS_START_VBOOT); + + vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, + sizeof(*vboot_handoff)); + + if (vboot_handoff == NULL) { + printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); + return NULL; + } + + memset(vboot_handoff, 0, sizeof(*vboot_handoff)); + + vboot_invoke_wrapper(vboot_handoff); + + timestamp_add_now(TS_END_VBOOT); + + /* Take RO firmware path since no RW area was selected. */ + if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && + vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { + printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", + vboot_handoff->selected_firmware); + return NULL; + } + if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) { printk(BIOS_ERR, "Invalid ramstage index: %d\n", CONFIG_VBOOT_RAMSTAGE_INDEX); - return; + return NULL; } /* Check for invalid address. */ fwc = &vboot_handoff->components[CONFIG_VBOOT_RAMSTAGE_INDEX]; if (fwc->address == 0) { printk(BIOS_DEBUG, "RW ramstage image address invalid.\n"); - return; + return NULL; } printk(BIOS_DEBUG, "RW ramstage image at 0x%08x, 0x%08x bytes.\n", @@ -169,53 +194,18 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, stage = (void *)fwc->address; - timestamp_add_now(TS_START_COPYRAM); - if (rmodule_stage_load(&rmod_load, stage)) { vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; printk(BIOS_DEBUG, "Could not load ramstage region.\n"); - return; + return NULL; } - cache_loaded_ramstage(handoff, rmod_load.cbmem_entry, rmod_load.entry); - - timestamp_add_now(TS_END_COPYRAM); + *cbmem_entry = rmod_load.cbmem_entry; - stage_exit(rmod_load.entry); + return rmod_load.entry; } -void vboot_verify_firmware(struct romstage_handoff *handoff) -{ - struct vboot_handoff *vboot_handoff; - - /* Don't go down verified boot path on S3 resume. */ - if (handoff != NULL && handoff->s3_resume) - return; - - timestamp_add_now(TS_START_VBOOT); - - vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, - sizeof(*vboot_handoff)); - - if (vboot_handoff == NULL) { - printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); - return; - } - - memset(vboot_handoff, 0, sizeof(*vboot_handoff)); - - vboot_invoke_wrapper(vboot_handoff); - - timestamp_add_now(TS_END_VBOOT); - - /* Take RO firmware path since no RW area was selected. */ - if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && - vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { - printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", - vboot_handoff->selected_firmware); - return; - } - - /* Load ramstage from the vboot_handoff structure. */ - vboot_load_ramstage(vboot_handoff, handoff); -} +const struct ramstage_loader_ops vboot_ramstage_loader = { + .name = "VBOOT", + .vboot_load_ramstage, +};

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Patch set updated for coreboot: 450977a rambi: add initial rambi mainboard support
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4865 -gerrit commit 450977a7349c317657da7960b09f813207f734dd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 4 16:00:07 2013 -0500 rambi: add initial rambi mainboard support This is just a copy from bayleybay. BUG=chrome-os-partner:23121 BRANCH=None TEST=None Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171940 Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> --- src/mainboard/google/Kconfig | 3 + src/mainboard/google/rambi/Kconfig | 28 +++ src/mainboard/google/rambi/Makefile.inc | 24 +++ src/mainboard/google/rambi/acpi/chromeos.asl | 24 +++ src/mainboard/google/rambi/acpi/ec.asl | 37 ++++ src/mainboard/google/rambi/acpi/mainboard.asl | 28 +++ src/mainboard/google/rambi/acpi/platform.asl | 73 +++++++ src/mainboard/google/rambi/acpi/superio.asl | 20 ++ src/mainboard/google/rambi/acpi/thermal.asl | 246 ++++++++++++++++++++++ src/mainboard/google/rambi/acpi/video.asl | 43 ++++ src/mainboard/google/rambi/acpi_tables.c | 287 ++++++++++++++++++++++++++ src/mainboard/google/rambi/chromeos.c | 79 +++++++ src/mainboard/google/rambi/cmos.layout | 139 +++++++++++++ src/mainboard/google/rambi/devicetree.cb | 8 + src/mainboard/google/rambi/dsdt.asl | 55 +++++ src/mainboard/google/rambi/fadt.c | 156 ++++++++++++++ src/mainboard/google/rambi/gpio.c | 188 +++++++++++++++++ src/mainboard/google/rambi/mainboard.c | 143 +++++++++++++ src/mainboard/google/rambi/mainboard_smi.c | 63 ++++++ src/mainboard/google/rambi/romstage.c | 37 ++++ src/mainboard/google/rambi/thermal.h | 57 +++++ 21 files changed, 1738 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index c866c1f..b86b0ad 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -40,6 +40,8 @@ config BOARD_GOOGLE_PEPPY bool "Peppy" config BOARD_GOOGLE_PIT bool "Pit" +config BOARD_GOOGLE_RAMBI + bool "Rambi" config BOARD_GOOGLE_SLIPPY bool "Slippy" config BOARD_GOOGLE_SNOW @@ -56,6 +58,7 @@ source "src/mainboard/google/link/Kconfig" source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/peppy/Kconfig" source "src/mainboard/google/pit/Kconfig" +source "src/mainboard/google/rambi/Kconfig" source "src/mainboard/google/slippy/Kconfig" source "src/mainboard/google/snow/Kconfig" source "src/mainboard/google/stout/Kconfig" diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig new file mode 100644 index 0000000..0892139 --- /dev/null +++ b/src/mainboard/google/rambi/Kconfig @@ -0,0 +1,28 @@ +if BOARD_GOOGLE_RAMBI + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select SOC_INTEL_BAYTRAIL + select ENABLE_BUILTIN_COM1 + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MAINBOARD_HAS_CHROMEOS + select CHROMEOS + select MARK_GRAPHICS_MEM_WRCOMB + +config MAINBOARD_DIR + string + default google/rambi + +config MAINBOARD_PART_NUMBER + string + default "RAMBI" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +endif # BOARD_INTEL_BAYLEYBAY diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc new file mode 100644 index 0000000..d3c6f0d --- /dev/null +++ b/src/mainboard/google/rambi/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += gpio.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/mainboard/google/rambi/acpi/chromeos.asl b/src/mainboard/google/rambi/acpi/chromeos.asl new file mode 100644 index 0000000..40ffcf0 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/chromeos.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Name(OIPG, Package() { + Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery + Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer + Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect +}) diff --git a/src/mainboard/google/rambi/acpi/ec.asl b/src/mainboard/google/rambi/acpi/ec.asl new file mode 100644 index 0000000..9ae5951 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/ec.asl @@ -0,0 +1,37 @@ +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N + + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x03), + ACPR, 1, // AC Power (1=present) + , 2, + CFAN, 1, // CPU Fan (1=on) + , 2, + LIDS, 1, // Lid State (1=open) + , 1, + SPTR, 8, // SMBUS Protocol Register + SSTS, 8, // SMBUS Status Register + SADR, 8, // SMBUS Address Register + SCMD, 8, // SMBUS Command Register + SBFR, 256, // SMBUS Block Buffer + SCNT, 8, // SMBUS Block Count + + Offset (0x3a), + ECMD, 8, // EC Command Register + + Offset (0x82), + PECL, 8, // PECI fractional (1/64 Celsius) + PECH, 8, // PECI integer (Celsius) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) +} diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl new file mode 100644 index 0000000..3e0eb33 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) + + // Wake from deep sleep via GPIO27 + Name(_PRW, Package(){27, 4}) +} diff --git a/src/mainboard/google/rambi/acpi/platform.asl b/src/mainboard/google/rambi/acpi/platform.asl new file mode 100644 index 0000000..e069392 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/platform.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl new file mode 100644 index 0000000..9092a6c --- /dev/null +++ b/src/mainboard/google/rambi/acpi/superio.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ diff --git a/src/mainboard/google/rambi/acpi/thermal.asl b/src/mainboard/google/rambi/acpi/thermal.asl new file mode 100644 index 0000000..00a8750 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/thermal.asl @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 0 seconds + Name (_TZP, 0) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + Method (_TMP, 0, Serialized) + { + Return (CTOK (30)) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (\F0OF)) + } Else { + Return (CTOK (\F0ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (\F1OF)) + } Else { + Return (CTOK (\F1ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (\F2OF)) + } Else { + Return (CTOK (\F2ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (\F3OF)) + } Else { + Return (CTOK (\F3ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (\F4OF)) + } Else { + Return (CTOK (\F4ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (0, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (1, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (2, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (3, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + Method (_OFF) { + Store (4, \FLVL) + Notify (\_TZ.THRM, 0x81) + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/google/rambi/acpi/video.asl b/src/mainboard/google/rambi/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c new file mode 100644 index 0000000..3723021 --- /dev/null +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -0,0 +1,287 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <baytrail/acpi.h> +#include <baytrail/nvs.h> + +extern const unsigned char AmlCode[]; + +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->f4of = FAN4_THRESHOLD_OFF; + gnvs->f4on = FAN4_THRESHOLD_ON; + gnvs->f4pw = FAN4_PWM; + + gnvs->f3of = FAN3_THRESHOLD_OFF; + gnvs->f3on = FAN3_THRESHOLD_ON; + gnvs->f3pw = FAN3_PWM; + + gnvs->f2of = FAN2_THRESHOLD_OFF; + gnvs->f2on = FAN2_THRESHOLD_ON; + gnvs->f2pw = FAN2_PWM; + + gnvs->f1of = FAN1_THRESHOLD_OFF; + gnvs->f1on = FAN1_THRESHOLD_ON; + gnvs->f1pw = FAN1_PWM; + + gnvs->f0of = FAN0_THRESHOLD_OFF; + gnvs->f0on = FAN0_THRESHOLD_ON; + gnvs->f0pw = FAN0_PWM; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = 0; + + /* TPM Present */ + gnvs->tpmp = 1; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + +#if CONFIG_CHROMEOS + // TODO(reinauer) this could move elsewhere? + chromeos_init_vboot(&(gnvs->chromeos)); + /* Emerald Lake has no EC (?) */ + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif + + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> %p\n", i, gnvs); + *(u32*)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ + smm_setup_structures(gnvs, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); + ssdt = (acpi_header_t *)current; + acpi_create_serialio_ssdt(ssdt); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c new file mode 100644 index 0000000..2681b3a --- /dev/null +++ b/src/mainboard/google/rambi/chromeos.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> + +/* Compile-time settings for developer and recovery mode. */ +#define DEV_MODE_SETTING 1 +#define REC_MODE_SETTING 0 + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static void fill_lb_gpio(struct lb_gpio *gpio, int polarity, + const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = -1; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, ACTIVE_HIGH, "recovery", REC_MODE_SETTING); + fill_lb_gpio(gpio++, ACTIVE_HIGH, "developer", DEV_MODE_SETTING); + fill_lb_gpio(gpio++, ACTIVE_HIGH, "lid", 1); // force open + fill_lb_gpio(gpio++, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif + +int get_developer_mode_switch(void) +{ + return DEV_MODE_SETTING; +} + +int get_recovery_mode_switch(void) +{ + return REC_MODE_SETTING; +} + +int get_write_protect_state(void) +{ + return 0; +} + diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout new file mode 100644 index 0000000..afdd3c6 --- /dev/null +++ b/src/mainboard/google/rambi/cmos.layout @@ -0,0 +1,139 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb new file mode 100644 index 0000000..376aab6 --- /dev/null +++ b/src/mainboard/google/rambi/devicetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/baytrail + device cpu_cluster 0 on end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 1f.0 on end # LPC Bridge + end +end diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl new file mode 100644 index 0000000..172aaf4 --- /dev/null +++ b/src/mainboard/google/rambi/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ENABLE_TPM + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/baytrail/acpi/globalnvs.asl> + + //#include "acpi/thermal.asl" + + //#include <soc/intel/baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + //#include <soc/intel/baytrail/acpi/northcluster.asl> + #include <soc/intel/baytrail/acpi/southcluster.asl> + } + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/baytrail/acpi/sleepstates.asl> +} diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c new file mode 100644 index 0000000..9c8bd60 --- /dev/null +++ b/src/mainboard/google/rambi/fadt.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + /* FIXME: hard coded address. */ + u16 pmbase = 0x400; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c new file mode 100644 index 0000000..8393e33 --- /dev/null +++ b/src/mainboard/google/rambi/gpio.c @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <baytrail/gpio.h> + +/* SCORE GPIOs */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_DEFAULT, /* GPIO 0 */ + GPIO_DEFAULT, /* GPIO 1 */ + GPIO_DEFAULT, /* GPIO 2 */ + GPIO_DEFAULT, /* GPIO 3 */ + GPIO_DEFAULT, /* GPIO 4 */ + GPIO_DEFAULT, /* GPIO 5 */ + GPIO_DEFAULT, /* GPIO 6 */ + GPIO_DEFAULT, /* GPIO 7 */ + GPIO_DEFAULT, /* GPIO 8 */ + GPIO_DEFAULT, /* GPIO 9 */ + GPIO_DEFAULT, /* GPIO 10 */ + GPIO_DEFAULT, /* GPIO 11 */ + GPIO_DEFAULT, /* GPIO 12 */ + GPIO_DEFAULT, /* GPIO 13 */ + GPIO_DEFAULT, /* GPIO 14 */ + GPIO_DEFAULT, /* GPIO 15 */ + GPIO_DEFAULT, /* GPIO 16 */ + GPIO_DEFAULT, /* GPIO 17 */ + GPIO_DEFAULT, /* GPIO 18 */ + GPIO_DEFAULT, /* GPIO 19 */ + GPIO_DEFAULT, /* GPIO 20 */ + GPIO_DEFAULT, /* GPIO 21 */ + GPIO_DEFAULT, /* GPIO 22 */ + GPIO_DEFAULT, /* GPIO 23 */ + GPIO_DEFAULT, /* GPIO 24 */ + GPIO_DEFAULT, /* GPIO 25 */ + GPIO_DEFAULT, /* GPIO 26 */ + GPIO_DEFAULT, /* GPIO 27 */ + GPIO_DEFAULT, /* GPIO 28 */ + GPIO_DEFAULT, /* GPIO 29 */ + GPIO_DEFAULT, /* GPIO 30 */ + GPIO_DEFAULT, /* GPIO 31 */ + GPIO_DEFAULT, /* GPIO 32 */ + GPIO_DEFAULT, /* GPIO 33 */ + GPIO_DEFAULT, /* GPIO 34 */ + GPIO_DEFAULT, /* GPIO 35 */ + GPIO_DEFAULT, /* GPIO 36 */ + GPIO_DEFAULT, /* GPIO 37 */ + GPIO_DEFAULT, /* GPIO 38 */ + GPIO_DEFAULT, /* GPIO 39 */ + GPIO_DEFAULT, /* GPIO 40 */ + GPIO_DEFAULT, /* GPIO 41 */ + GPIO_DEFAULT, /* GPIO 42 */ + GPIO_DEFAULT, /* GPIO 43 */ + GPIO_DEFAULT, /* GPIO 44 */ + GPIO_DEFAULT, /* GPIO 45 */ + GPIO_DEFAULT, /* GPIO 46 */ + GPIO_DEFAULT, /* GPIO 47 */ + GPIO_DEFAULT, /* GPIO 48 */ + GPIO_DEFAULT, /* GPIO 49 */ + GPIO_DEFAULT, /* GPIO 50 */ + GPIO_FUNC1, /* GPIO 51 - SMBus DATA */ + GPIO_FUNC1, /* GPIO 52 - SMBus CLK */ + GPIO_DEFAULT, /* GPIO 53 */ + GPIO_DEFAULT, /* GPIO 54 */ + GPIO_DEFAULT, /* GPIO 55 */ + GPIO_DEFAULT, /* GPIO 56 */ + GPIO_FUNC1, /* GPIO 57 - COM1 TXD */ + GPIO_DEFAULT, /* GPIO 58 */ + GPIO_DEFAULT, /* GPIO 59 */ + GPIO_DEFAULT, /* GPIO 60 */ + GPIO_FUNC1, /* GPIO 61 - COM1 RXD */ + GPIO_DEFAULT, /* GPIO 62 */ + GPIO_DEFAULT, /* GPIO 63 */ + GPIO_DEFAULT, /* GPIO 64 */ + GPIO_DEFAULT, /* GPIO 65 */ + GPIO_DEFAULT, /* GPIO 66 */ + GPIO_DEFAULT, /* GPIO 67 */ + GPIO_DEFAULT, /* GPIO 68 */ + GPIO_DEFAULT, /* GPIO 69 */ + GPIO_DEFAULT, /* GPIO 70 */ + GPIO_DEFAULT, /* GPIO 71 */ + GPIO_DEFAULT, /* GPIO 72 */ + GPIO_DEFAULT, /* GPIO 73 */ + GPIO_DEFAULT, /* GPIO 74 */ + GPIO_DEFAULT, /* GPIO 75 */ + GPIO_DEFAULT, /* GPIO 76 */ + GPIO_DEFAULT, /* GPIO 77 */ + GPIO_DEFAULT, /* GPIO 78 */ + GPIO_DEFAULT, /* GPIO 79 */ + GPIO_DEFAULT, /* GPIO 80 */ + GPIO_DEFAULT, /* GPIO 81 */ + GPIO_DEFAULT, /* GPIO 82 */ + GPIO_DEFAULT, /* GPIO 83 */ + GPIO_DEFAULT, /* GPIO 84 */ + GPIO_DEFAULT, /* GPIO 85 */ + GPIO_DEFAULT, /* GPIO 86 */ + GPIO_DEFAULT, /* GPIO 87 */ + GPIO_DEFAULT, /* GPIO 88 */ + GPIO_DEFAULT, /* GPIO 89 */ + GPIO_DEFAULT, /* GPIO 90 */ + GPIO_DEFAULT, /* GPIO 91 */ + GPIO_DEFAULT, /* GPIO 92 */ + GPIO_DEFAULT, /* GPIO 93 */ + GPIO_DEFAULT, /* GPIO 94 */ + GPIO_DEFAULT, /* GPIO 95 */ + GPIO_DEFAULT, /* GPIO 96 */ + GPIO_DEFAULT, /* GPIO 97 */ + GPIO_DEFAULT, /* GPIO 98 */ + GPIO_DEFAULT, /* GPIO 99 */ + GPIO_DEFAULT, /* GPIO 100 */ + GPIO_DEFAULT, /* GPIO 101 */ + GPIO_END +}; + +/* SSUS GPIOs */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_DEFAULT, /* GPIO 0 */ + GPIO_DEFAULT, /* GPIO 1 */ + GPIO_DEFAULT, /* GPIO 2 */ + GPIO_DEFAULT, /* GPIO 3 */ + GPIO_DEFAULT, /* GPIO 4 */ + GPIO_DEFAULT, /* GPIO 5 */ + GPIO_DEFAULT, /* GPIO 6 */ + GPIO_DEFAULT, /* GPIO 7 */ + GPIO_DEFAULT, /* GPIO 8 */ + GPIO_DEFAULT, /* GPIO 9 */ + GPIO_DEFAULT, /* GPIO 10 */ + GPIO_DEFAULT, /* GPIO 11 */ + GPIO_DEFAULT, /* GPIO 12 */ + GPIO_DEFAULT, /* GPIO 13 */ + GPIO_DEFAULT, /* GPIO 14 */ + GPIO_DEFAULT, /* GPIO 15 */ + GPIO_DEFAULT, /* GPIO 16 */ + GPIO_DEFAULT, /* GPIO 17 */ + GPIO_DEFAULT, /* GPIO 18 */ + GPIO_DEFAULT, /* GPIO 19 */ + GPIO_DEFAULT, /* GPIO 20 */ + GPIO_DEFAULT, /* GPIO 21 */ + GPIO_DEFAULT, /* GPIO 22 */ + GPIO_DEFAULT, /* GPIO 23 */ + GPIO_DEFAULT, /* GPIO 24 */ + GPIO_DEFAULT, /* GPIO 25 */ + GPIO_DEFAULT, /* GPIO 26 */ + GPIO_DEFAULT, /* GPIO 27 */ + GPIO_DEFAULT, /* GPIO 28 */ + GPIO_DEFAULT, /* GPIO 29 */ + GPIO_DEFAULT, /* GPIO 30 */ + GPIO_DEFAULT, /* GPIO 31 */ + GPIO_DEFAULT, /* GPIO 32 */ + GPIO_DEFAULT, /* GPIO 33 */ + GPIO_DEFAULT, /* GPIO 34 */ + GPIO_DEFAULT, /* GPIO 35 */ + GPIO_DEFAULT, /* GPIO 36 */ + GPIO_DEFAULT, /* GPIO 37 */ + GPIO_DEFAULT, /* GPIO 38 */ + GPIO_DEFAULT, /* GPIO 39 */ + GPIO_DEFAULT, /* GPIO 40 */ + GPIO_DEFAULT, /* GPIO 41 */ + GPIO_DEFAULT, /* GPIO 42 */ + GPIO_DEFAULT, /* GPIO 43 */ + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = NULL, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map +}; + +struct soc_gpio_config* mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c new file mode 100644 index 0000000..d2bfea3 --- /dev/null +++ b/src/mainboard/google/rambi/mainboard.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 1; + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CX = 0x0001; + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) * + * bit 2 = EFP * + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) * + * bit 6 = EFP2 * + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0003; + res = 1; + break; + case 0x5f70: + switch ((X86_CX >> 8) & 0xff) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, + "Unknown INT15 5f70 function: 0x%02x\n", + ((X86_CX >> 8) & 0xff)); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c new file mode 100644 index 0000000..0571baf --- /dev/null +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <baytrail/nvs.h> + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#define APMC_FINALIZE 0xcb + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APMC_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return 0; + } + + mainboard_finalized = 1; + break; + } + return 0; +} diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c new file mode 100644 index 0000000..f845173 --- /dev/null +++ b/src/mainboard/google/rambi/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <console/console.h> +#include <baytrail/mrc_wrapper.h> +#include <baytrail/romstage.h> + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct mrc_params mp = { + .mainboard = { + .dram_type = DRAM_DDR3L, + .dram_info_location = DRAM_INFO_SPD_SMBUS, + .spd_addrs = { 0xa0, 0xa2 }, + }, + }; + rp->mrc_params = &mp; + romstage_common(rp); +} diff --git a/src/mainboard/google/rambi/thermal.h b/src/mainboard/google/rambi/thermal.h new file mode 100644 index 0000000..f771014 --- /dev/null +++ b/src/mainboard/google/rambi/thermal.h @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYLEYBAY_THERMAL_H +#define BAYLEYBAY_THERMAL_H + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x00 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 48 +#define FAN3_THRESHOLD_ON 55 +#define FAN3_PWM 0x40 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 52 +#define FAN2_THRESHOLD_ON 64 +#define FAN2_PWM 0x80 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 60 +#define FAN1_THRESHOLD_ON 68 +#define FAN1_PWM 0xb0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 66 +#define FAN0_THRESHOLD_ON 78 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 100 + +#endif

1 0

Patch set updated for coreboot: 2633ac8 coreboot: infrastructure for different ramstage loaders
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5087 -gerrit commit 2633ac81a78eef0d7d5c0357947b6eff3f15d251 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 17:19:46 2014 -0600 coreboot: infrastructure for different ramstage loaders WARNING: Not compile tested. proof of concept. There are 2 methods currently avaiable in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/lib/cbfs_and_run.c | 21 +----- src/cpu/intel/haswell/romstage.c | 2 - src/include/cbfs.h | 22 +++++- src/include/cbmem.h | 4 ++ src/include/ramstage_loader.h | 34 +++++++++ src/include/romstage_handoff.h | 10 ++- src/lib/Makefile.inc | 1 + src/lib/cbfs.c | 53 -------------- src/lib/loaders/Makefile.inc | 21 ++++++ src/lib/loaders/cbfs_ramstage_loader.c | 67 +++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 100 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/chromeos.h | 4 -- src/vendorcode/google/chromeos/vboot_loader.c | 86 ++++++++++------------ 13 files changed, 295 insertions(+), 130 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 3d56e19..ca8d61b 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -17,27 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <cbfs.h> #include <arch/stages.h> -#include <timestamp.h> - -static void cbfs_and_run_core(const char *filename) -{ - u8 *dst; - - timestamp_add_now(TS_START_COPYRAM); - print_debug("Loading image.\n"); - dst = cbfs_load_stage(CBFS_DEFAULT_MEDIA, filename); - if ((void *)dst == (void *) -1) - die("FATAL: Essential component is missing.\n"); - - timestamp_add_now(TS_END_COPYRAM); - print_debug("Jumping to image.\n"); - stage_exit(dst); -} +#include <ramstage_loader.h> void asmlinkage copy_and_run(void) { - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram"); + run_ramstage(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 60a1c3a..9e27668 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -309,8 +309,6 @@ void romstage_after_car(void) prepare_for_resume(handoff); - vboot_verify_firmware(handoff); - /* Load the ramstage. */ copy_and_run(); } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index c05566d..9ce862b 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -83,6 +83,10 @@ void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); +#if defined(__PRE_RAM__) +struct romstage_handoff; +struct cbmem_entry; + #if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) /* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined * to be weak so that board and chipset code may override them. Their job is to @@ -90,9 +94,6 @@ int init_default_cbfs_media(struct cbfs_media *media); * relocated ramstage is saved using the cbmem infrastructure. These * functions are only valid during romstage. */ -struct romstage_handoff; -struct cbmem_entry; - /* The implementer of cache_loaded_ramstage() may use the romstage_handoff * structure to store information, but note that the handoff variable can be * NULL. The ramstage cbmem_entry represents the region occupied by the loaded @@ -105,7 +106,22 @@ cache_loaded_ramstage(struct romstage_handoff *handoff, void * __attribute__((weak)) load_cached_ramstage(struct romstage_handoff *handoff, const struct cbmem_entry *ramstage); +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static inline void cache_loaded_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage, void *entry_point) +{ +} + +static inline void * +load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage) +{ + return NULL; +} + #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ +#endif /* defined(__PRE_RAM__) */ #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9e68ba9..7a936c2 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -150,6 +150,10 @@ void cbmem_late_set_table(uint64_t base, uint64_t size); void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); +static inline const struct cbmem_entry *cbmem_entry_find(u32 id) +{ + return NULL; +} #endif /* CONFIG_DYNAMIC_CBMEM */ /* Common API between cbmem and dynamic cbmem. */ diff --git a/src/include/ramstage_loader.h b/src/include/ramstage_loader.h new file mode 100644 index 0000000..67003d4 --- /dev/null +++ b/src/include/ramstage_loader.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 20l4 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef RAMSTAGE_LOADER_H +#define RAMSTAGE_LOADER_H + +#include <stdint.h> +struct cbmem_entry; + +/* Run ramstage from romstage. */ +void run_ramstage(void); + +struct ramstage_loader_ops { + const char *name; + void *(*load)(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry); +}; + +#endif /* RAMSTAGE_LOADER_H */ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 699838a..307babd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -41,6 +41,7 @@ struct romstage_handoff { }; #if defined(__PRE_RAM__) +#if CONFIG_EARLY_CBMEM_INIT /* The romstage_handoff_find_or_add() function provides the necessary logic * for initializing the romstage_handoff structure in cbmem. Different components * of the romstage may be responsible for setting up different fields. Therefore @@ -63,7 +64,14 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) return handoff; } -#endif +#else /* CONFIG_EARLY_CBMEM_INIT */ +static inline struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + return NULL; +} +#endif /* CONFIG_EARLY_CBMEM_INIT */ + +#endif /* defined(__PRE_RAM__) */ #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 18b30ef..55a946f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -16,6 +16,7 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-y += loaders bootblock-y += cbfs.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..f2a2587 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -123,58 +123,6 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -#if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) - -#include <rmodule.h> -#include <romstage_handoff.h> -static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, - struct romstage_handoff *handoff) -{ - struct rmod_stage_load rmod_ram = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = name, - }; - - if (rmodule_stage_load_from_cbfs(&rmod_ram)) { - printk(BIOS_DEBUG, "Could not load ramstage.\n"); - return (void *) -1; - } - - cache_loaded_ramstage(handoff, rmod_ram.cbmem_entry, rmod_ram.entry); - - return rmod_ram.entry; -} - -void * cbfs_load_stage(struct cbfs_media *media, const char *name) -{ - struct romstage_handoff *handoff; - const struct cbmem_entry *ramstage; - void *entry; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) { - LOG("Couldn't find or allocate romstage handoff.\n"); - return load_stage_from_cbfs(media, name, handoff); - } else if (!handoff->s3_resume) - return load_stage_from_cbfs(media, name, handoff); - - ramstage = cbmem_entry_find(CBMEM_ID_RAMSTAGE); - - if (ramstage == NULL) - return load_stage_from_cbfs(media, name, handoff); - - /* S3 resume path. Load a cached copy of the loaded ramstage. If - * return value is NULL load from cbfs. */ - entry = load_cached_ramstage(handoff, ramstage); - if (entry == NULL) - return load_stage_from_cbfs(media, name, handoff); - - return entry; -} - -#else - void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) @@ -211,7 +159,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ #if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc new file mode 100644 index 0000000..eceaa00 --- /dev/null +++ b/src/lib/loaders/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += cbfs_ramstage_loader.c +romstage-y += load_and_run_ramstage.c diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c new file mode 100644 index 0000000..6e5fe8e --- /dev/null +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <cbfs.h> +#include <arch/stages.h> +#include <ramstage_loader.h> +#include <timestamp.h> + +#if CONFIG_RELOCATABLE_RAMSTAGE +#include <rmodule.h> + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **entry) +{ + struct rmod_stage_load rmod_ram = { + .cbmem_id = cbmem_id, + .name = name, + }; + + if (rmodule_stage_load_from_cbfs(&rmod_ram)) { + printk(BIOS_DEBUG, "Could not load ramstage.\n"); + return NULL; + } + + *cbmem_entry = rmod_ram.cbmem_entry; + + return rmod_ram.entry; +} + +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name); + + if ((void *)entry == (void *) -1) + entry = NULL; + + return entry; +} + +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ + +const struct ramstage_loader_ops cbfs_ramstage_loader = { + .name = "CBFS", + .load = cbfs_load_ramstage, +}; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c new file mode 100644 index 0000000..a4c400a --- /dev/null +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 20l4 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <cbmem.h> +#include <ramstage_loader.h> +#include <romstage_handoff.h> +#include <timestamp.h> + +extern const struct ramstage_loader_ops cbfs_ramstage_loader; +extern const struct ramstage_loader_ops vboot_ramstage_loader; + +static const struct ramstage_loader_ops *loaders[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_ramstage_loader, +#endif + &cbfs_ramstage_loader, +}; + +static const char *ramstage_name = CONFIG_CBFS_PREFIX "/coreboot_ram"; +static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; + +static void +load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) +{ + const struct cbmem_entry *cbmem_entry; + void *entry_point; + + timestamp_add_now(TS_START_COPYRAM); + entry_point = ops->load(ramstage_id, ramstage_name, &cbmem_entry); + + if (entry_point == NULL) + return; + + cache_loaded_ramstage(handoff, cbmem_entry, entry_point); + + timestamp_add_now(TS_END_COPYRAM); + + stage_exit(entry_point); +} + +static void run_ramstage_from_resume(struct romstage_handoff *handoff) +{ + void *entry; + const struct cbmem_entry *cbmem_entry; + + if (handoff != NULL && handoff->s3_resume) { + cbmem_entry = cbmem_entry_find(ramstage_id); + + /* No place to load ramstage. */ + if (cbmem_entry == NULL) + return; + + /* Load the cached ramstage to runtime location. */ + entry = load_cached_ramstage(handoff, cbmem_entry); + + if (entry != NULL) { + print_debug("Jumping to image.\n"); + stage_exit(entry); + } + } +} + +void run_ramstage(void) +{ + struct romstage_handoff *handoff; + const struct ramstage_loader_ops *ops; + int i; + + handoff = romstage_handoff_find_or_add(); + + run_ramstage_from_resume(handoff); + + for (i = 0; i < ARRAY_SIZE(loaders); i++) { + ops = loaders[i]; + printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); + load_ramstage(ops, handoff); + } + + die("Ramstage was not loaded!\n"); +} diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 5493801..0359c91 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,14 +46,10 @@ int recovery_mode_enabled(void); /* functions implemented in vboot.c */ void init_chromeos(int bootmode); -struct romstage_handoff; #if CONFIG_VBOOT_VERIFY_FIRMWARE -void vboot_verify_firmware(struct romstage_handoff *handoff); void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); -#else -static inline void vboot_verify_firmware(struct romstage_handoff *h) {} #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index cc7c25d..2094657 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -141,27 +141,52 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) vboot_run_stub(&context); } -static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, - struct romstage_handoff *handoff) +static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **entry) { + struct vboot_handoff *vboot_handoff; struct cbfs_stage *stage; const struct firmware_component *fwc; struct rmod_stage_load rmod_load = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = CONFIG_CBFS_PREFIX "/coreboot_ram", + .cbmem_id = cbmem_id, + .name = name, }; + timestamp_add_now(TS_START_VBOOT); + + vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, + sizeof(*vboot_handoff)); + + if (vboot_handoff == NULL) { + printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); + return NULL; + } + + memset(vboot_handoff, 0, sizeof(*vboot_handoff)); + + vboot_invoke_wrapper(vboot_handoff); + + timestamp_add_now(TS_END_VBOOT); + + /* Take RO firmware path since no RW area was selected. */ + if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && + vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { + printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", + vboot_handoff->selected_firmware); + return NULL; + } + if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) { printk(BIOS_ERR, "Invalid ramstage index: %d\n", CONFIG_VBOOT_RAMSTAGE_INDEX); - return; + return NULL; } /* Check for invalid address. */ fwc = &vboot_handoff->components[CONFIG_VBOOT_RAMSTAGE_INDEX]; if (fwc->address == 0) { printk(BIOS_DEBUG, "RW ramstage image address invalid.\n"); - return; + return NULL; } printk(BIOS_DEBUG, "RW ramstage image at 0x%08x, 0x%08x bytes.\n", @@ -169,53 +194,18 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, stage = (void *)fwc->address; - timestamp_add_now(TS_START_COPYRAM); - if (rmodule_stage_load(&rmod_load, stage)) { vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; printk(BIOS_DEBUG, "Could not load ramstage region.\n"); - return; + return NULL; } - cache_loaded_ramstage(handoff, rmod_load.cbmem_entry, rmod_load.entry); - - timestamp_add_now(TS_END_COPYRAM); + *cbmem_entry = rmod_load.cbmem_entry; - stage_exit(rmod_load.entry); + return rmod_load.entry; } -void vboot_verify_firmware(struct romstage_handoff *handoff) -{ - struct vboot_handoff *vboot_handoff; - - /* Don't go down verified boot path on S3 resume. */ - if (handoff != NULL && handoff->s3_resume) - return; - - timestamp_add_now(TS_START_VBOOT); - - vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, - sizeof(*vboot_handoff)); - - if (vboot_handoff == NULL) { - printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); - return; - } - - memset(vboot_handoff, 0, sizeof(*vboot_handoff)); - - vboot_invoke_wrapper(vboot_handoff); - - timestamp_add_now(TS_END_VBOOT); - - /* Take RO firmware path since no RW area was selected. */ - if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && - vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { - printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", - vboot_handoff->selected_firmware); - return; - } - - /* Load ramstage from the vboot_handoff structure. */ - vboot_load_ramstage(vboot_handoff, handoff); -} +const struct ramstage_loader_ops vboot_ramstage_loader = { + .name = "VBOOT", + .vboot_load_ramstage, +};

1 0

Patch set updated for coreboot: 2d73dd0 baytrail: set host memory map
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4852 -gerrit commit 2d73dd01523a8268beb8c1ca99dc09038140f0a7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 24 12:41:08 2013 -0500 baytrail: set host memory map Prior to this commit the coreboot resource allocator was not using proper addresses. That's not surprising there wasn't any code to initialize the resources properly. This commit initializes the memory map accoring to the BUNIT registers. BUG=chrome-os-partner:22860 BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted. Noted output for resource assignments is sane. Change-Id: Ice8d067d8b993736de5c5b273a0f642fa034a024 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170429 --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/northcluster.c | 149 ++++++++++++++++++++++++++++++++++ 2 files changed, 150 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 90b39eb..d8dcaf6 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -15,6 +15,7 @@ ramstage-y += spi.c ramstage-y += chip.c ramstage-y += iosf.c romstage-y += iosf.c +ramstage-y += northcluster.c # Remove as ramstage gets fleshed out diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c new file mode 100644 index 0000000..0616e5d --- /dev/null +++ b/src/soc/intel/baytrail/northcluster.c @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> + +/* Host Memory Map: + * + * +--------------------------+ BMBOUND_HI + * | Usable DRAM | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ BMBOUND + * | TPM | + * +--------------------------+ IMR2 + * | TXE | + * +--------------------------+ IMR1 + * | iGD | + * +--------------------------+ + * | GTT | + * +--------------------------+ SMMRRH, IRM0 + * | TSEG | + * +--------------------------+ SMMRRL + * | Usable DRAM | + * +--------------------------+ 0 + * + * Note that there are really only a few regions that need to enumerated w.r.t. + * coreboot's resrouce model: + * + * +--------------------------+ BMBOUND_HI + * | Cacheable/Usable | + * +--------------------------+ 4GiB + * + * +--------------------------+ BMBOUND + * | Uncacheable/Reserved | + * +--------------------------+ SMMRRH + * | Cacheable/Reserved | + * +--------------------------+ SMMRRL + * | Cacheable/Usable | + * +--------------------------+ 0 + */ +#define RES_IN_KiB(r) ((r) >> 10) + +static void soc_trans_router_read_resources(device_t dev) +{ + unsigned long mmconf; + unsigned long bmbound; + unsigned long bmbound_hi; + unsigned long smmrrh; + unsigned long smmrrl; + unsigned long base_k, size_k; + const unsigned long four_gig_kib = (4 << (30 - 10)); + int index = 0; + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* PCIe memory-mapped config space access - 256 MiB. */ + mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); + mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); + + /* 0 -> SMM_DEFAULT_BASE cacheable ram. */ + ram_resource(dev, index++, 0, RES_IN_KiB(SMM_DEFAULT_BASE)); + /* Default SMM region is cacheable but reserved for coreboot */ + reserved_ram_resource(dev, index++, RES_IN_KiB(SMM_DEFAULT_BASE), + RES_IN_KiB(SMM_DEFAULT_SIZE)); + + /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE - > 0xa0000 */ + base_k = RES_IN_KiB(SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE); + size_k = RES_IN_KiB(0xa0000) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* The SMMRR registers are 1MiB granularity with smmrrh being + * inclusive of the SMM region. */ + smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; + smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; + + /* 0xc0000 -> smrrl - cacheable and usable */ + base_k = RES_IN_KiB(0xc0000); + size_k = smmrrl - base_k; + ram_resource(dev, index++, base_k, size_k); + + if (smmrrh > smmrrl) + reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); + + /* All address space between bmbound and smmrrh is unusable. */ + bmbound = RES_IN_KiB(iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1)); + mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); + + /* The BMBOUND_HI register matches register bits of 31:24 with address + * bits of 35:28. Therefore, shift register to align properly. */ + bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); + bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; + if (bmbound_hi > four_gig_kib) + ram_resource(dev, index++, four_gig_kib, + bmbound_hi - four_gig_kib); +} + +static void nc_read_resources(device_t dev) +{ + /* For some reason the graphics pci device (0, 2, 0) and the SoC + * transaction router are coming up with the same device id. */ + if (dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)) == dev) + return soc_trans_router_read_resources(dev); + else + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + +} + +static struct device_operations nc_ops = { + .read_resources = nc_read_resources, + .set_resources = NULL, + .enable_resources = NULL, + .init = NULL, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver nc_driver __pci_driver = { + .ops = &nc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = SOC_DEVID, +}; +

1 0

Patch set updated for coreboot: 47aaf44 baytrail: add dunit access and registers
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4853 -gerrit commit 47aaf442d257c05f0c49c5a40bb142278c8640e3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Sep 23 14:17:35 2013 -0500 baytrail: add dunit access and registers The dunit on baytrail is the dram unit. Provide a means to access the configuration registers there using the proper IOSF mechanisms. BUG=chrome-os-partner:22875 BRANCH=none TEST=Built and booted. Able to read dram registers. Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170490 --- src/soc/intel/baytrail/baytrail/iosf.h | 16 ++++++++++++++++ src/soc/intel/baytrail/iosf.c | 21 +++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 6ff087b..444dc38 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -51,6 +51,8 @@ uint32_t iosf_bunit_read(int reg); void iosf_bunit_write(int reg, uint32_t val); +uint32_t iosf_dunit_read(int reg); +void iosf_dunit_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -106,6 +108,20 @@ void iosf_bunit_write(int reg, uint32_t val); #define BUNIT_SMRRH 0x2f # define BUNIT_SMRR_ENABLE (1 << 31) +/* + * DUNIT Registers. + */ +#define DRP 0x00 +# define DRP_CH0_RANK0_EN (0x01 << 0) +# define DRP_CH0_RANK1_EN (0x01 << 1) +# define DRP_CH1_RANK0_EN (0x01 << 2) +# define DRP_CH1_RANK1_EN (0x01 << 3) +#define DTR0 0x01 +# define DTR0_SPEED_MASK 0x03 +# define DTR0_SPEED_800 0x00 +# define DTR0_SPEED_1066 0x01 +# define DTR0_SPEED_1333 0x02 +# define DTR0_SPEED_1600 0x03 #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 6d4cba9..2373d81 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -59,3 +59,24 @@ void iosf_bunit_write(int reg, uint32_t val) write_iosf_reg(MCR_REG, cr); write_iosf_reg(MDR_REG, val); } + +uint32_t iosf_dunit_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | + IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_dunit_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) | + IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + + write_iosf_reg(MCR_REG, cr); + write_iosf_reg(MDR_REG, val); +}

1 0

Patch set updated for coreboot: f5ddb61 baytrail: introduce pattrs
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4854 -gerrit commit f5ddb6140f499ee0e869bf057e344bfeb3a94e9f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 24 16:47:49 2013 -0500 baytrail: introduce pattrs The pattrs structure is intended for the supporting coreboot code to reference instead of going back to the source of the values (msrs, cpuid, etc). It essentially serves as a global structure for collecting attributes about the platform/processor. Additionally, the implementation provides a point during boot to hoook work before device enumeration/initialization by providing a init() function to soc_intel_baytrail_ops that is called before device work in the boot state machine. BUG=chrome-os-partner:22862 BUG=chrome-os-partner:22863 BRANCH=None TEST=Built and booted. Noted pattrs output. Change-Id: I073da8aca29635146fb0d4a2625b2b7564fd8414 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170403 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 2 + src/soc/intel/baytrail/baytrail/lpc.h | 13 ++++ src/soc/intel/baytrail/baytrail/msr.h | 7 +- src/soc/intel/baytrail/baytrail/pattrs.h | 56 +++++++++++++++ src/soc/intel/baytrail/baytrail/ramstage.h | 4 ++ src/soc/intel/baytrail/chip.c | 7 ++ src/soc/intel/baytrail/ramstage.c | 107 +++++++++++++++++++++++++++++ 7 files changed, 195 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d8dcaf6..756fd39 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -3,6 +3,7 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/intel/microcode ramstage-y += memmap.c romstage-y += memmap.c @@ -16,6 +17,7 @@ ramstage-y += chip.c ramstage-y += iosf.c romstage-y += iosf.c ramstage-y += northcluster.c +ramstage-y += ramstage.c # Remove as ramstage gets fleshed out diff --git a/src/soc/intel/baytrail/baytrail/lpc.h b/src/soc/intel/baytrail/baytrail/lpc.h index 17dc4b5..05220e4 100644 --- a/src/soc/intel/baytrail/baytrail/lpc.h +++ b/src/soc/intel/baytrail/baytrail/lpc.h @@ -21,6 +21,7 @@ #define _BAYTRAIL_LPC_H_ /* PCI config registers in LPC bridge. */ +#define REVID 0x08 #define ABASE 0x40 #define PBASE 0x44 #define GBASE 0x48 @@ -31,4 +32,16 @@ #define UART_CONT 0x80 #define RCBA 0xf0 + +#define RID_A_STEPPING_START 1 +#define RID_B_STEPPING_START 5 +enum baytrail_stepping { + STEP_A0, + STEP_A1, + STEP_B0, + STEP_B1, + STEP_B2, + STEP_B3, +}; + #endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h index 1934a31..7f3b3b2 100644 --- a/src/soc/intel/baytrail/baytrail/msr.h +++ b/src/soc/intel/baytrail/baytrail/msr.h @@ -20,6 +20,11 @@ #ifndef _BAYTRAIL_MSR_H_ #define _BAYTRAIL_MSR_H_ -#define MSR_PLATFORM_INFO 0xce +#define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_PLATFORM_INFO 0xce +#define MSR_IA32_PERF_CTL 0x199 +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define MSR_IACORE_RATIOS 0x66a +#define MSR_IACORE_VIDS 0x66b #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/pattrs.h b/src/soc/intel/baytrail/baytrail/pattrs.h new file mode 100644 index 0000000..7c210b9 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/pattrs.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PATTRS_H_ +#define _PATTRS_H_ + +#include <stdint.h> +#include <cpu/x86/msr.h> + +/* The pattrs structure is a common place to stash pertinent information + * about the processor or platform. Instead of going to the source (msrs, cpuid) + * every time an attribute is needed use the pattrs structure. + */ +struct pattrs { + msr_t platform_id; + msr_t platform_info; + msr_t iacore_ratios; + msr_t iacore_vids; + uint32_t cpuid; + int revid; + int stepping; + const void *microcode_patch; + int address_bits; + int num_cpus; +}; + +/* This is just to hide the abstraction w/o relying on how the underlying + * storage is allocated. */ +#define PATTRS_GLOB_NAME __global_pattrs +#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME +extern DEFINE_PATTRS; + +static inline const struct pattrs *pattrs_get(void) +{ + return &PATTRS_GLOB_NAME; +} + + +#endif /* _PATTRS_H_ */ + diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index 61fe9c3..d1fe0f1 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -22,6 +22,10 @@ #include <device/device.h> +/* The baytrail_init_pre_device() function is called prior to device + * initialization, but it's after console and cbmem has been reinitialized. */ +void baytrail_init_pre_device(void); + extern struct pci_operations soc_pci_ops; #endif /* _BAYTRAIL_RAMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 09c36df..5a898f6 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -68,9 +68,16 @@ static void enable_dev(device_t dev) } } +/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ +static void soc_init(void *chip_info) +{ + baytrail_init_pre_device(); +} + struct chip_operations soc_intel_baytrail_ops = { CHIP_NAME("Intel BayTrail SoC") .enable_dev = enable_dev, + .init = soc_init, }; static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c new file mode 100644 index 0000000..e30fc89 --- /dev/null +++ b/src/soc/intel/baytrail/ramstage.c @@ -0,0 +1,107 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <stdlib.h> + +#include <baytrail/pattrs.h> +#include <baytrail/lpc.h> +#include <baytrail/msr.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> + +/* Global PATTRS */ +DEFINE_PATTRS; + +#define SHOW_PATTRS 1 + +static void detect_num_cpus(struct pattrs *attrs) +{ + int ecx = 0; + + while (1) { + struct cpuid_result leaf_b; + + leaf_b = cpuid_ext(0xb, ecx); + + /* Bay Trail doesn't have hyperthreading so just determine the + * number of cores by from level type (ecx[15:8] == * 2). */ + if ((leaf_b.ecx & 0xff00) == 0x0200) { + attrs->num_cpus = leaf_b.ebx & 0xffff; + break; + } + ecx++; + } +} + +static inline void fill_in_msr(msr_t *msr, int idx) +{ + *msr = rdmsr(idx); + if (SHOW_PATTRS) { + printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", + idx, msr->hi, msr->lo); + } +} + +static const char *stepping_str[] = { "A0", "A1", "B0", "B1", "B2", "B3" }; + +static void fill_in_pattrs(void) +{ + device_t dev; + struct pattrs *attrs = (struct pattrs *)pattrs_get(); + + attrs->cpuid = cpuid_eax(1); + dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + attrs->revid = pci_read_config8(dev, REVID); + /* The revision to stepping IDs have two values per metal stepping. */ + if (attrs->revid >= RID_B_STEPPING_START) { + attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; + attrs->stepping += STEP_B0; + } else { + attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; + attrs->stepping += STEP_A0; + } + + attrs->microcode_patch = intel_microcode_find(); + attrs->address_bits = cpuid_eax(0x80000008) & 0xff; + detect_num_cpus(attrs); + + if (SHOW_PATTRS) { + printk(BIOS_DEBUG, "BYT: cpuid %08x cpus %d rid %02x step %s\n", + attrs->cpuid, attrs->num_cpus, attrs->revid, + (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : + stepping_str[attrs->stepping]); + } + + fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); + fill_in_msr(&attrs->iacore_ratios, MSR_IACORE_RATIOS); + fill_in_msr(&attrs->iacore_vids, MSR_IACORE_VIDS); +} + +void baytrail_init_pre_device(void) +{ + fill_in_pattrs(); +}

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Patch set updated for coreboot: 156724d baytrail: Add GPIO initial configuration infrastructure.
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4855 -gerrit commit 156724d0318dbc99f97184e6844d0e1591ca29cf Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu Sep 26 16:44:14 2013 -0700 baytrail: Add GPIO initial configuration infrastructure. During ramstage, call mainboard_get_gpios to get initial GPIO configuration from the mainboard code, then initialize GPIOs as requested. BUG=chrome-os-partner:22863 TEST=Manual. Using bayleybay GPIO table, set UART GPIOs to 'function 1', and verify UART still works after GPIO configuration. Also, verify legacy GPIO config is functional by toggling test pin. Change-Id: Ic58d8ddd15c4dc48a751a83f6d26c7809c1efc42 Reviewed-on: https://chromium-review.googlesource.com/170306 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 2 +- src/soc/intel/baytrail/baytrail/gpio.h | 178 +++++++++++++++++++++++++++++++-- src/soc/intel/baytrail/gpio.c | 166 ++++++++++++++++++++++++++++++ src/soc/intel/baytrail/ramstage.c | 8 ++ 4 files changed, 342 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 756fd39..ebcda6b 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -18,7 +18,7 @@ ramstage-y += iosf.c romstage-y += iosf.c ramstage-y += northcluster.c ramstage-y += ramstage.c - +ramstage-y += gpio.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index 68e3241..32b991e 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -24,20 +24,181 @@ #include <arch/io.h> #include <baytrail/iomap.h> -/* Registers sitting behind the IO_BASE_ADDRESS */ +/* #define GPIO_DEBUG */ -#define SCORE_PCONF_OFFSET 0x0000 -#define SSUS_PCONF_OFFSET 0x2000 +/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ +#define GPSCORE_PAD_BASE IO_BASE_ADDRESS + 0x0000 +#define GPNCORE_PAD_BASE IO_BASE_ADDRESS + 0x1000 +#define GPSSUS_PAD_BASE IO_BASE_ADDRESS + 0x2000 + +/* Pad register offset */ +#define PAD_CONF0_REG 0x0 +#define PAD_CONF1_REG 0x4 +#define PAD_VAL_REG 0x8 + +/* Legacy IO register base */ +#define GPSCORE_LEGACY_BASE GPIO_BASE_ADDRESS + 0x00 +#define GPSSUS_LEGACY_BASE GPIO_BASE_ADDRESS + 0x80 +/* Some banks have no legacy GPIO interface */ +#define GP_LEGACY_BASE_NONE 0xFFFF + +#define LEGACY_USE_SEL_REG 0x00 +#define LEGACY_IO_SEL_REG 0x04 +#define LEGACY_GP_LVL_REG 0x08 +#define LEGACY_TPE_REG 0x0C +#define LEGACY_TNE_REG 0x10 +#define LEGACY_TS_REG 0x14 +#define LEGACY_WAKE_EN_REG 0x18 + +/* Number of GPIOs in each bank */ +#define GPNCORE_COUNT 27 +#define GPSCORE_COUNT 102 +#define GPSSUS_COUNT 44 + +/* GPIO legacy IO register settings */ +#define GPIO_USE_PAD 0 +#define GPIO_USE_LEGACY 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_PEDGE_DISABLE 0 +#define GPIO_PEDGE_ENABLE 1 + +#define GPIO_NEDGE_DISABLE 0 +#define GPIO_NEDGE_ENABLE 1 + +/* PAD_CONF0 settings */ +#define PAD_IRQ_EN (1 << 27) +#define PAD_LEVEL_IRQ (1 << 24) + +#define PAD_PU_2K (0 << 9) +#define PAD_PU_10K (1 << 9) +#define PAD_PU_20K (2 << 9) +#define PAD_PU_40K (3 << 9) + +#define PAD_PU_DISABLE (0 << 7) +#define PAD_PU_UP (1 << 7) +#define PAD_PU_DOWN (2 << 7) + +#define PAD_FUNC0 0x0 +#define PAD_FUNC1 0x1 +#define PAD_FUNC2 0x2 +#define PAD_FUNC3 0x3 +#define PAD_FUNC4 0x4 +#define PAD_FUNC5 0x5 +#define PAD_FUNC6 0x6 + +/* PAD_VAL settings */ +#define PAD_INPUT_ENABLE (1 << 2) +#define PAD_OUTPUT_ENABLE (1 << 1) + +/* End marker */ +#define GPIO_LIST_END 0xffffffff + +#define GPIO_INPUT_PU_10K \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_UP, \ + .pad_val = PAD_INPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT } + +#define GPIO_OUT_LOW \ + { .pad_conf0 = PAD_PU_DISABLE, \ + .pad_val = PAD_OUTPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_LOW } + +#define GPIO_OUT_HIGH \ + { .pad_conf0 = PAD_PU_DISABLE, \ + .pad_val = PAD_OUTPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_HIGH } + +#define GPIO_FUNC0 \ + { .use_sel = GPIO_USE_PAD, \ + .pad_conf0 = PAD_FUNC0 } + +#define GPIO_FUNC1 \ + { .use_sel = GPIO_USE_PAD, \ + .pad_conf0 = PAD_FUNC1 } + +#define GPIO_FUNC2 \ + { .use_sel = GPIO_USE_PAD, \ + .pad_conf0 = PAD_FUNC2 } + +#define GPIO_FUNC3 \ + { .use_sel = GPIO_USE_PAD, \ + .pad_conf0 = PAD_FUNC3 } + +#define GPIO_FUNC4 \ + { .use_sel = GPIO_USE_PAD, \ + .pad_conf0 = PAD_FUNC4 } + +#define GPIO_FUNC5 \ + { .use_sel = GPIO_USE_PAD, \ + .pad_conf0 = PAD_FUNC5 } + +#define GPIO_FUNC6 \ + { .use_sel = GPIO_USE_PAD, \ + .pad_conf0 = PAD_FUNC6 } + +#define GPIO_END \ + { .pad_conf0 = GPIO_LIST_END } + +/* Common default GPIO settings */ +#define GPIO_INPUT GPIO_INPUT_PU_10K +#define GPIO_UNUSED GPIO_INPUT_PU_10K +#define GPIO_DEFAULT GPIO_FUNC0 + +struct soc_gpio_map { + u32 pad_conf0; + u32 pad_conf1; + u32 pad_val; + u8 use_sel : 1; + u8 io_sel : 1; + u8 gp_lvl : 1; + u8 tpe : 1; + u8 tne : 1; + u8 wake_en : 1; +} __attribute__ ((packed)); + +struct soc_gpio_config { + const struct soc_gpio_map *ncore; + const struct soc_gpio_map *score; + const struct soc_gpio_map *ssus; +}; + +/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ +struct gpio_bank { + const int gpio_count; + const u8* gpio_to_pad; + const int legacy_base; + const unsigned long pad_base; + const u8 has_wake_en :1; +}; + +void setup_soc_gpios(struct soc_gpio_config *config); +/* This function is weak and can be overridden by a mainboard function. */ +struct soc_gpio_config* mainboard_get_gpios(void); + +/* Functions / defines for changing GPIOs in romstage */ +/* SCORE Pad definitions. */ +#define PCU_SMB_CLK_PAD 88 +#define PCU_SMB_DATA_PAD 90 static inline unsigned int score_pconf0(int pad_num) { - return IO_BASE_ADDRESS + SCORE_PCONF_OFFSET + pad_num * 16; + return GPSCORE_PAD_BASE + pad_num * 16; } - static inline unsigned int ssus_pconf0(int pad_num) { - return IO_BASE_ADDRESS + SSUS_PCONF_OFFSET + pad_num * 16; + return GPSSUS_PAD_BASE + pad_num * 16; } static inline void score_select_func(int pad, int func) @@ -62,9 +223,4 @@ static inline void ssus_select_func(int pad, int func) write32(pconf0_addr, reg); } -/* SCORE Pad definitions. */ -#define PCU_SMB_CLK_PAD 88 -#define PCU_SMB_DATA_PAD 90 -#define PCU_SMB_ALERT_PAD 92 - #endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c new file mode 100644 index 0000000..8118aeb --- /dev/null +++ b/src/soc/intel/baytrail/gpio.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <baytrail/gpio.h> +#include <device/pci.h> +#include <console/console.h> + +/* GPIO-to-Pad LUTs */ +static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = + { 25, 24, 23, 32, 33, 34, 36, 37, 35, 22, + 20, 21, 18, 38, 39, 1, 4, 8, 17, 0, + 3, 6, 16, 19, 2, 5, 9 }; + +static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = + { 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, + 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, + 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, + 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, + 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, + 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, + 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, + 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, + 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, + 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, + 97, 100 }; + +static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = + { 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, + 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, + 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, + 26, 51, 56, 54, 49, 55, 48, 47, 50, 58, + 52, 53, 59, 40 }; + +/* GPIO bank descriptions */ +static const struct gpio_bank gpncore_bank = { + .gpio_count = GPNCORE_COUNT, + .gpio_to_pad = gpncore_gpio_to_pad, + .legacy_base = GP_LEGACY_BASE_NONE, + .pad_base = GPNCORE_PAD_BASE, + .has_wake_en = 0, +}; + +static const struct gpio_bank gpscore_bank = { + .gpio_count = GPSCORE_COUNT, + .gpio_to_pad = gpscore_gpio_to_pad, + .legacy_base = GPSCORE_LEGACY_BASE, + .pad_base = GPSCORE_PAD_BASE, + .has_wake_en = 0, +}; + +static const struct gpio_bank gpssus_bank = { + .gpio_count = GPSSUS_COUNT, + .gpio_to_pad = gpssus_gpio_to_pad, + .legacy_base = GPSSUS_LEGACY_BASE, + .pad_base = GPSSUS_PAD_BASE, + .has_wake_en = 1, +}; + +static void setup_gpios(const struct soc_gpio_map *gpios, + const struct gpio_bank *bank) +{ + const struct soc_gpio_map *config; + int gpio = 0; + u32 reg; + u8 set, bit; + + u32 use_sel[4] = {0}; + u32 io_sel[4] = {0}; + u32 gp_lvl[4] = {0}; + u32 tpe[4] = {0}; + u32 tne[4] = {0}; + u32 wake_en[4] = {0}; + + if (!gpios) + return; + + for (config = gpios; config->pad_conf0 != GPIO_LIST_END; + config++, gpio++) { + if (gpio > bank->gpio_count) + break; + + set = gpio >> 5; + bit = gpio % 32; + + if (bank->legacy_base != GP_LEGACY_BASE_NONE) { + /* Legacy IO configuration */ + use_sel[set] |= config->use_sel << bit; + io_sel[set] |= config->io_sel << bit; + gp_lvl[set] |= config->gp_lvl << bit; + tpe[set] |= config->tpe << bit; + tne[set] |= config->tne << bit; + + /* Some banks do not have wake_en ability */ + if (bank->has_wake_en) + wake_en[set] |= config->wake_en << bit; + } + + /* Pad configuration registers */ + reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio]; + +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n", + reg, config->pad_conf0, config->pad_conf1, + config->pad_val ); +#endif + + write32(reg + PAD_CONF0_REG, config->pad_conf0); + write32(reg + PAD_CONF1_REG, config->pad_conf1); + write32(reg + PAD_VAL_REG, config->pad_val); + } + + if (bank->legacy_base != GP_LEGACY_BASE_NONE) + for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) { + reg = bank->legacy_base + 0x20 * set; + +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, + "Write GPIO: Reg(%x) - %x %x %x %x %x\n", + reg, use_sel[set], io_sel[set], gp_lvl[set], + tpe[set], tne[set]); +#endif + + outl(use_sel[set], reg + LEGACY_USE_SEL_REG); + outl(io_sel[set], reg + LEGACY_IO_SEL_REG); + outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG); + outl(tpe[set], reg + LEGACY_TPE_REG); + outl(tne[set], reg + LEGACY_TNE_REG); + + /* TS registers are WOC */ + outl(0, reg + LEGACY_TS_REG); + + if (bank->has_wake_en) + outl(wake_en[set], reg + LEGACY_WAKE_EN_REG); + } +} + +void setup_soc_gpios(struct soc_gpio_config *config) +{ + if (config) { + setup_gpios(config->ncore, &gpncore_bank); + setup_gpios(config->score, &gpscore_bank); + setup_gpios(config->ssus, &gpssus_bank); + } +} + +struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) +{ + printk(BIOS_DEBUG, "Default/empty GPIO config\n"); + return NULL; +} diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index e30fc89..10c030f 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -31,6 +31,7 @@ #include <baytrail/msr.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> +#include <baytrail/gpio.h> /* Global PATTRS */ DEFINE_PATTRS; @@ -101,7 +102,14 @@ static void fill_in_pattrs(void) fill_in_msr(&attrs->iacore_vids, MSR_IACORE_VIDS); } + void baytrail_init_pre_device(void) { + struct soc_gpio_config *config; + fill_in_pattrs(); + + /* Get GPIO initial states from mainboard */ + config = mainboard_get_gpios(); + setup_soc_gpios(config); }

1 0

Patch set updated for coreboot: e916375 baytrail: update microcode to version 313
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4848 -gerrit commit e916375aa79e54bb45fe4799e143b14c1ac6f84b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Sep 23 13:18:16 2013 -0500 baytrail: update microcode to version 313 B2 and B3 steppings are now bumped to version 313. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built. Change-Id: I09ae5110b66c725e959e95fc15bc85ccf371495d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170425 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- .../intel/baytrail/microcode/M0C3067_0000030f.h | 13056 ------------------- .../intel/baytrail/microcode/M0C3067_00000313.h | 13056 +++++++++++++++++++ src/soc/intel/baytrail/microcode/microcode_blob.c | 2 +- 3 files changed, 13057 insertions(+), 13057 deletions(-) diff --git a/src/soc/intel/baytrail/microcode/M0C3067_0000030f.h b/src/soc/intel/baytrail/microcode/M0C3067_0000030f.h deleted file mode 100644 index aa39049..0000000 --- a/src/soc/intel/baytrail/microcode/M0C3067_0000030f.h +++ /dev/null @@ -1,13056 +0,0 @@ -0x000000001, -0x00000030f, -0x008132013, -0x000030673, -0x08692d626, -0x000000001, -0x00000000c, -0x00000cbd0, -0x00000cc00, -0x000000000, -0x000000000, -0x000000000, -0x000000000, -0x0000000a1, -0x000020001, -0x00000030f, -0x000000000, -0x000000000, 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b/src/soc/intel/baytrail/microcode/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode[] = { -#include "M0C3067_0000030f.h" +#include "M0C3067_00000313.h" };

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Patch set updated for coreboot: 0fffd48 baytrail: cache ROM space early in bootblock
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4849 -gerrit commit 0fffd48d53d3e4d2bcecf256060f31337eb81300 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Sep 23 14:15:42 2013 -0500 baytrail: cache ROM space early in bootblock Take advantage of the cache early in bootblock. The intent is to speed up cbfs walking when trying to locate romstage. BUG=chrome-os-partner:22857 BRANCH=None TEST=Built and booted. Change-Id: If03210103c9782390230915db3b4a9759d172dce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170426 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/bootblock/bootblock.c | 31 ++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 66120d9..70ccc21 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -18,12 +18,43 @@ */ #include <arch/io.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <baytrail/iosf.h> +static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +{ + msr_t basem, maskm; + basem.lo = base | type; + basem.hi = 0; + wrmsr(MTRRphysBase_MSR(reg), basem); + maskm.lo = ~(size - 1) | MTRRphysMaskValid; + maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(reg), maskm); +} + +static void enable_rom_caching(void) +{ + msr_t msr; + + disable_cache(); + /* Why only top 4MiB ? */ + set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); + enable_cache(); + + /* Enable Variable MTRRs */ + msr.hi = 0x00000000; + msr.lo = 0x00000800; + wrmsr(MTRRdefType_MSR, msr); +} + static void bootblock_cpu_init(void) { uint32_t reg; + enable_rom_caching(); + /* Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to * properly configure as the IOSF access registers live in PCI

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coreboot-gerrit January 2014