coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 36614ea baytrail: update microcode to version 313
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit 36614ea4cc91e7f9b2647a00d1f9f3fdbe812d0c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Sep 23 13:18:16 2013 -0500 baytrail: update microcode to version 313 B2 and B3 steppings are now bumped to version 313. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built. Change-Id: I09ae5110b66c725e959e95fc15bc85ccf371495d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170425 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4848 for details. -gerrit

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Patch merged into coreboot/master: 5340b39 utils: Install man pages as non-executable (chmod 644)
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit 5340b39850558ced40746f5641e8c35e94c12506 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Tue Jan 28 16:52:48 2014 +0000 utils: Install man pages as non-executable (chmod 644) This bothers rpmlint. Change-Id: I27d9cfac3ef6834ff87acc5a5ccbf332e59eeb1a Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> See http://review.coreboot.org/5075 for details. -gerrit

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Patch set updated for coreboot: 5340b39 utils: Install man pages as non-executable (chmod 644)
by Alexandru Gagniuc 31 Jan '14

31 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5075 -gerrit commit 5340b39850558ced40746f5641e8c35e94c12506 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Tue Jan 28 16:52:48 2014 +0000 utils: Install man pages as non-executable (chmod 644) This bothers rpmlint. Change-Id: I27d9cfac3ef6834ff87acc5a5ccbf332e59eeb1a Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/inteltool/Makefile | 2 +- util/nvramtool/Makefile | 2 +- util/superiotool/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 2028a4a..6682444 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -82,7 +82,7 @@ install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) -p -m644 $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 .PHONY: all clean distclean dep pciutils diff --git a/util/nvramtool/Makefile b/util/nvramtool/Makefile index b1cb27c..12f4a5c 100644 --- a/util/nvramtool/Makefile +++ b/util/nvramtool/Makefile @@ -66,7 +66,7 @@ install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 - $(INSTALL) cli/$(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) -p -m644 cli/$(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 .PHONY: all clean distclean dep diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 900b8ae..7ce5ede 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -70,7 +70,7 @@ install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) -p -m644 $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 clean: rm -f $(PROGRAM) *.o

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Patch set updated for coreboot: 7bb2f78 utils: Do not install manual pages executable
by Lubomir Rintel 31 Jan '14

31 Jan '14

Lubomir Rintel (lkundrak(a)v3.sk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5075 -gerrit commit 7bb2f78aa5b48ba22881104ff4578f3a185ce5a8 Author: Lubomir Rintel <lkundrak(a)v3.sk> Date: Tue Jan 28 16:52:48 2014 +0000 utils: Do not install manual pages executable This bothers rpmlint. Change-Id: I27d9cfac3ef6834ff87acc5a5ccbf332e59eeb1a Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- util/inteltool/Makefile | 2 +- util/nvramtool/Makefile | 2 +- util/superiotool/Makefile | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 2028a4a..6682444 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -82,7 +82,7 @@ install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) -p -m644 $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 .PHONY: all clean distclean dep pciutils diff --git a/util/nvramtool/Makefile b/util/nvramtool/Makefile index b1cb27c..12f4a5c 100644 --- a/util/nvramtool/Makefile +++ b/util/nvramtool/Makefile @@ -66,7 +66,7 @@ install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 - $(INSTALL) cli/$(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) -p -m644 cli/$(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 .PHONY: all clean distclean dep diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile index 900b8ae..7ce5ede 100644 --- a/util/superiotool/Makefile +++ b/util/superiotool/Makefile @@ -70,7 +70,7 @@ install: $(PROGRAM) mkdir -p $(DESTDIR)$(PREFIX)/sbin $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/sbin mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8 - $(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 + $(INSTALL) -p -m644 $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8 clean: rm -f $(PROGRAM) *.o

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New patch to review for coreboot: 16f64af AMD cimx/sb800: Set SPI frequency and prefetch
by Kyösti Mälkki 31 Jan '14

31 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5089 -gerrit commit 16f64af25cc2b79975698598ab57a40ff8110d15 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jan 31 20:32:54 2014 +0200 AMD cimx/sb800: Set SPI frequency and prefetch Broken with/since commit d1cb0eec. Original intention was to set the frequency for 'Fast Read' command in bits 15..14, and enable 'Fast Read' command. Modified register contains SPI frequency for 'Normal Read' command in bits 13..12. Default for this is 11b for 16.5 MHz. Existing code unintentionally clears these bits, increasing SPI frequency to 66MHz for 'Normal Read' command. This is above specifications for many common SPI flash components and also makes flashrom older than 0.9.7-r1750 to operate unreliably on read/write/erase for these platforms. Change-Id: I30109e2a0410c0bb0bdc968ea71787396b32e761 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/cimx/sb800/bootblock.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index ac9351e..4fd2739 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -66,7 +66,6 @@ static void enable_prefetch(void) static void enable_spi_fast_mode(void) { - u8 byte; u32 dword; device_t dev = PCI_DEV(0, 0x14, 0x03); @@ -76,8 +75,8 @@ static void enable_spi_fast_mode(void) pci_io_write_config32(dev, 0xa0, (u32) spi_base | 2); // early enable of SPI 33 MHz fast mode read - byte = spi_base[3]; - spi_base[3] = (byte & ~(3 << 14)) | (1 << 14); + dword = spi_base[3]; + spi_base[3] = (dword & ~(3 << 14)) | (1 << 14); spi_base[0] = spi_base[0] | (1 << 18); // fast read enable pci_io_write_config32(dev, 0xa0, save);

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Patch merged into coreboot/master: 4eb3ddf baytrail: add initial support
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit 4eb3ddf2b20d1472bea54903a2403aba05907aaa Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 7 00:41:48 2013 -0500 baytrail: add initial support The initial Bay Trail code is intended to support the mobile and desktop version of Bay Trail. This support can train memory and execute through ramstage. However, the resource allocation is not curently handled correctly. The MRC cache parameters are successfully saved and reused after the initial cold boot. BUG=chrome-os-partner:22292 BRANCH=None TEST=Built and booted on a reference board through ramstage. Change-Id: I238ede326802aad272c6cca39d7ad4f161d813f5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168387 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4847 for details. -gerrit

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Patch set updated for coreboot: ec23eff amd/cimx: fix sb(8|9)00 NULL type redefine
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5088 -gerrit commit ec23eff3f6240ff7a8a72ca45b8960fc465bd0c6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 22:20:01 2014 -0600 amd/cimx: fix sb(8|9)00 NULL type redefine It is inappropriate for chipset code to be redefining types -- especially NULL to a non-pointer type. There's only one non-straight forward change. A condition being checked was '!ptr_type == NULL' (0 as int). That check is actually 'ptr_type != NULL'. Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 6 +----- src/southbridge/amd/cimx/sb900/SbPlatform.h | 6 +----- src/southbridge/amd/cimx/sb900/cfg.c | 6 +++--- src/vendorcode/amd/cimx/sb800/AZALIA.c | 2 +- src/vendorcode/amd/cimx/sb800/GEC.c | 2 +- src/vendorcode/amd/cimx/sb800/SATA.c | 14 +++++++------- src/vendorcode/amd/cimx/sb800/SBCMN.c | 4 ++-- src/vendorcode/amd/cimx/sb800/SBPOR.c | 2 +- src/vendorcode/amd/cimx/sb800/USB.c | 6 +++--- src/vendorcode/amd/cimx/sb900/Azalia.c | 2 +- src/vendorcode/amd/cimx/sb900/Gec.c | 2 +- src/vendorcode/amd/cimx/sb900/Sata.c | 2 +- src/vendorcode/amd/cimx/sb900/SbCmn.c | 4 ++-- src/vendorcode/amd/cimx/sb900/Usb.c | 6 +++--- 14 files changed, 28 insertions(+), 36 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index fa7d196..ea3f719 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -24,11 +24,7 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -//#include "cbtypes.h" -#ifdef NULL - #undef NULL -#endif -#define NULL 0 +#include <stddef.h> typedef unsigned long long PLACEHOLDER; diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 5e41978..176ad87 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -24,11 +24,7 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -//#include "cbtypes.h" -#ifdef NULL - #undef NULL -#endif -#define NULL 0 +#include <stddef.h> typedef unsigned long long PLACEHOLDER; diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index 58c0abe..ac7e551 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -178,7 +178,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) // sb_config->HpetMsiDis = 0; // Field Retired // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired // sb_config->PcibAutoClkCtr = 0; // Field Retired - sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used @@ -213,7 +213,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->TempMMIO = NULL; // CIMx Internal Used + sb_config->TempMMIO = (typeof(sb_config->TempMMIO))NULL; // CIMx Internal Used // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option @@ -296,7 +296,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_config) sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option sb_config->NbSbGen2 = NB_SB_GEN2; // External Option sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option - sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level sb_config->sdbEnable = 0; // CIMx Internal Used sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c index edd335f..e402ae8 100644 --- a/src/vendorcode/amd/cimx/sb800/AZALIA.c +++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c @@ -284,7 +284,7 @@ azaliaInitAfterPciEnum ( if ( pConfig->AzaliaController != 1 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); - if ( pConfig->BuildParameters.AzaliaSsid != NULL ) { + if ( pConfig->BuildParameters.AzaliaSsid != 0 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); } ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c index 6ee142f..582181b 100644 --- a/src/vendorcode/amd/cimx/sb800/GEC.c +++ b/src/vendorcode/amd/cimx/sb800/GEC.c @@ -113,7 +113,7 @@ gecInitAfterPciEnum ( ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); dbTemp = 0x07; WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp); - if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) { + if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) { GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 5966ec8..a301208 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -258,7 +258,7 @@ sataInitBeforePciEnum ( UINT16 i; SATAPHYSETTING *pPhyTable; - ddTempVar = NULL; + ddTempVar = 0; // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h // BIT4: Disable fast boot RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4); @@ -292,17 +292,17 @@ sataInitBeforePciEnum ( //Set PATA controller to native mode RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); } - if (pConfig->BuildParameters.IdeSsid != NULL ) { + if (pConfig->BuildParameters.IdeSsid != 0 ) { RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); } // SATA Controller Class ID & SSID pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); - if ( pConfig->BuildParameters.SataIDESsid != NULL ) { + if ( pConfig->BuildParameters.SataIDESsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataIDESsid; } dwDeviceId = pDeviceIdptr[dbValue]; if ( pConfig->SataClass == RAID_MODE) { - if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) { + if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) { ddTempVar = pConfig->BuildParameters.SataRAID5Ssid; } dwDeviceId = V_SB_SATA_RAID5_DID; @@ -310,19 +310,19 @@ sataInitBeforePciEnum ( getEfuseStatus (&pValue); if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) { dwDeviceId = V_SB_SATA_RAID_DID; - if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) { + if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataRAIDSsid; } } } if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) || ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) { - if ( pConfig->BuildParameters.SataAHCISsid != NULL ) { + if ( pConfig->BuildParameters.SataAHCISsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataAHCISsid; } } RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); - if ( ddTempVar != NULL ) { + if ( ddTempVar != 0 ) { RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); } // SATA IRQ Resource diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index ea1c029..07adf56 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -378,7 +378,7 @@ commonInitEarlyBoot ( RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); //Early post initialization of pci config space programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); - if ( pConfig->BuildParameters.SmbusSsid != NULL ) { + if ( pConfig->BuildParameters.SmbusSsid != 0 ) { RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); } //Make BAR registers of smbus invisible. @@ -388,7 +388,7 @@ commonInitEarlyBoot ( // LPC CFG programming // // SSID for LPC Controller - if (pConfig->BuildParameters.LpcSsid != NULL ) { + if (pConfig->BuildParameters.LpcSsid != 0 ) { RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); } // LPC MSI diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c index daf13c7..752c64e 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPOR.c +++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c @@ -150,7 +150,7 @@ sbPowerOnInit ( cimNbSbGen2 = pConfig->NbSbGen2; cimSataMode = pConfig->SATAMODE.SataModeReg; // Adding Fast Read Function support - if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) { + if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) { cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; } else { cimSpiFastReadEnable = cimSpiFastReadEnableDefault; diff --git a/src/vendorcode/amd/cimx/sb800/USB.c b/src/vendorcode/amd/cimx/sb800/USB.c index 0918e3a..c9e1b24 100644 --- a/src/vendorcode/amd/cimx/sb800/USB.c +++ b/src/vendorcode/amd/cimx/sb800/USB.c @@ -196,7 +196,7 @@ EhciInitAfterPciInit ( if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { //Enable Memory access RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - if (pConfig->BuildParameters.EhciSsid != NULL ) { + if (pConfig->BuildParameters.EhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); } //USB Common PHY CAL & Control Register setting @@ -308,7 +308,7 @@ usb4OhciInitAfterPciInit ( UINT32 ddDeviceId; ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); OhciInitAfterPciInit (ddDeviceId, pConfig); - if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + if (pConfig->BuildParameters.Ohci4Ssid != 0 ) { RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); } } @@ -327,7 +327,7 @@ OhciInitAfterPciInit ( // SB02186 RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00); if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { - if ( pConfig->BuildParameters.OhciSsid != NULL ) { + if ( pConfig->BuildParameters.OhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); } } diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c index 3fe4647..7a1277c 100644 --- a/src/vendorcode/amd/cimx/sb900/Azalia.c +++ b/src/vendorcode/amd/cimx/sb900/Azalia.c @@ -282,7 +282,7 @@ azaliaInitAfterPciEnum ( if ( pConfig->AzaliaController != 1 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); - if ( pConfig->BuildParameters.AzaliaSsid != NULL ) { + if ( pConfig->BuildParameters.AzaliaSsid != 0 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); } ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); diff --git a/src/vendorcode/amd/cimx/sb900/Gec.c b/src/vendorcode/amd/cimx/sb900/Gec.c index cfd830d..4afd6e9 100644 --- a/src/vendorcode/amd/cimx/sb900/Gec.c +++ b/src/vendorcode/amd/cimx/sb900/Gec.c @@ -109,7 +109,7 @@ gecInitAfterPciEnum ( VOID* GecRomAddress; VOID* GecShadowRomAddress; UINT32 ddTemp; - if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) { + if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) { GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c index fca8005..5c3a621 100644 --- a/src/vendorcode/amd/cimx/sb900/Sata.c +++ b/src/vendorcode/amd/cimx/sb900/Sata.c @@ -458,7 +458,7 @@ sataInitBeforePciEnum ( //Set PATA controller to native mode RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); } - if (pConfig->BuildParameters.IdeSsid != NULL ) { + if (pConfig->BuildParameters.IdeSsid != 0 ) { RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); } // SATA Controller Class ID & SSID diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c index 29f6fd1..bd50dde 100644 --- a/src/vendorcode/amd/cimx/sb900/SbCmn.c +++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c @@ -398,7 +398,7 @@ commonInitEarlyBoot ( RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); //Early post initialization of pci config space programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); - if ( pConfig->BuildParameters.SmbusSsid != NULL ) { + if ( pConfig->BuildParameters.SmbusSsid != 0 ) { RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); } //Make BAR registers of smbus invisible. @@ -408,7 +408,7 @@ commonInitEarlyBoot ( // LPC CFG programming // // SSID for LPC Controller - if (pConfig->BuildParameters.LpcSsid != NULL ) { + if (pConfig->BuildParameters.LpcSsid != 0 ) { RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); } // LPC MSI diff --git a/src/vendorcode/amd/cimx/sb900/Usb.c b/src/vendorcode/amd/cimx/sb900/Usb.c index 2ae03b3..2d635ec 100644 --- a/src/vendorcode/amd/cimx/sb900/Usb.c +++ b/src/vendorcode/amd/cimx/sb900/Usb.c @@ -357,7 +357,7 @@ EhciInitAfterPciInit ( if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { //Enable Memory access RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - if (pConfig->BuildParameters.EhciSsid != NULL ) { + if (pConfig->BuildParameters.EhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); } //USB Common PHY CAL & Control Register setting @@ -571,7 +571,7 @@ usb4OhciInitAfterPciInit ( UINT32 ddDeviceId; ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); OhciInitAfterPciInit (ddDeviceId, pConfig); - if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + if (pConfig->BuildParameters.Ohci4Ssid != 0 ) { RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); } } @@ -595,7 +595,7 @@ OhciInitAfterPciInit ( // RPR USB SMI Handshake RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00); if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { - if ( pConfig->BuildParameters.OhciSsid != NULL ) { + if ( pConfig->BuildParameters.OhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); } }

1 0

Patch set updated for coreboot: b656b05 x86: provide stage_exit() like arm
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5086 -gerrit commit b656b05d6f315407f75d96e8b50b85eeb149032d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 15:48:29 2014 -0600 x86: provide stage_exit() like arm The arm architectures have a stage_exit() function which takes a void * pointer as an entry point. Provide the same API for x86. This can make the booting paths less architecture-specific. Change-Id: I4ecfbf32f38f2e3817381b63e1f97e92654c5f97 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/stages.h | 8 ++++++++ src/arch/x86/lib/cbfs_and_run.c | 5 +---- src/vendorcode/google/chromeos/vboot_loader.c | 7 ++----- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 8cbf5da..91d0db6 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -24,4 +24,12 @@ void asmlinkage copy_and_run(void); void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); + +static inline void stage_exit(void *entry) +{ + __asm__ volatile ( + "jmp *%%edi\n" + :: "D"(entry) + ); +} #endif diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 6379842..3d56e19 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -34,10 +34,7 @@ static void cbfs_and_run_core(const char *filename) timestamp_add_now(TS_END_COPYRAM); print_debug("Jumping to image.\n"); - __asm__ volatile ( - "jmp *%%edi\n" - :: "D"(dst) - ); + stage_exit(dst); } void asmlinkage copy_and_run(void) diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index badff27..cc7c25d 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/stages.h> #include <stdint.h> #include <stddef.h> #include <cbfs.h> @@ -180,11 +181,7 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, timestamp_add_now(TS_END_COPYRAM); - __asm__ volatile ( - "movl $0, %%ebp\n" - "jmp *%%edi\n" - :: "D"(rmod_load.entry) - ); + stage_exit(rmod_load.entry); } void vboot_verify_firmware(struct romstage_handoff *handoff)

1 0

Patch set updated for coreboot: 52283c8 coreboot: infrastructure for different ramstage loaders
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5087 -gerrit commit 52283c8f3ff857724d20fadde35209f4fea63de8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 17:19:46 2014 -0600 coreboot: infrastructure for different ramstage loaders WARNING: Not compile tested. proof of concept. There are 2 methods currently avaiable in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/lib/cbfs_and_run.c | 21 +----- src/cpu/intel/haswell/romstage.c | 2 - src/include/cbfs.h | 22 +++++- src/include/cbmem.h | 5 ++ src/include/ramstage_loader.h | 34 +++++++++ src/include/romstage_handoff.h | 10 ++- src/lib/Makefile.inc | 1 + src/lib/cbfs.c | 53 -------------- src/lib/loaders/Makefile.inc | 21 ++++++ src/lib/loaders/cbfs_ramstage_loader.c | 67 +++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 100 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/chromeos.h | 4 -- src/vendorcode/google/chromeos/vboot_loader.c | 86 ++++++++++------------ 13 files changed, 296 insertions(+), 130 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 3d56e19..ca8d61b 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -17,27 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <cbfs.h> #include <arch/stages.h> -#include <timestamp.h> - -static void cbfs_and_run_core(const char *filename) -{ - u8 *dst; - - timestamp_add_now(TS_START_COPYRAM); - print_debug("Loading image.\n"); - dst = cbfs_load_stage(CBFS_DEFAULT_MEDIA, filename); - if ((void *)dst == (void *) -1) - die("FATAL: Essential component is missing.\n"); - - timestamp_add_now(TS_END_COPYRAM); - print_debug("Jumping to image.\n"); - stage_exit(dst); -} +#include <ramstage_loader.h> void asmlinkage copy_and_run(void) { - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram"); + run_ramstage(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 60a1c3a..9e27668 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -309,8 +309,6 @@ void romstage_after_car(void) prepare_for_resume(handoff); - vboot_verify_firmware(handoff); - /* Load the ramstage. */ copy_and_run(); } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index c05566d..9ce862b 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -83,6 +83,10 @@ void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); +#if defined(__PRE_RAM__) +struct romstage_handoff; +struct cbmem_entry; + #if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) /* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined * to be weak so that board and chipset code may override them. Their job is to @@ -90,9 +94,6 @@ int init_default_cbfs_media(struct cbfs_media *media); * relocated ramstage is saved using the cbmem infrastructure. These * functions are only valid during romstage. */ -struct romstage_handoff; -struct cbmem_entry; - /* The implementer of cache_loaded_ramstage() may use the romstage_handoff * structure to store information, but note that the handoff variable can be * NULL. The ramstage cbmem_entry represents the region occupied by the loaded @@ -105,7 +106,22 @@ cache_loaded_ramstage(struct romstage_handoff *handoff, void * __attribute__((weak)) load_cached_ramstage(struct romstage_handoff *handoff, const struct cbmem_entry *ramstage); +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static inline void cache_loaded_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage, void *entry_point) +{ +} + +static inline void * +load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage) +{ + return NULL; +} + #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ +#endif /* defined(__PRE_RAM__) */ #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9e68ba9..0b6031e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -66,6 +66,7 @@ #define CBMEM_ID_HOB_POINTER 0x484f4221 #ifndef __ASSEMBLER__ +#include <stddef.h> #include <stdint.h> struct cbmem_entry; @@ -150,6 +151,10 @@ void cbmem_late_set_table(uint64_t base, uint64_t size); void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); +static inline const struct cbmem_entry *cbmem_entry_find(u32 id) +{ + return NULL; +} #endif /* CONFIG_DYNAMIC_CBMEM */ /* Common API between cbmem and dynamic cbmem. */ diff --git a/src/include/ramstage_loader.h b/src/include/ramstage_loader.h new file mode 100644 index 0000000..67003d4 --- /dev/null +++ b/src/include/ramstage_loader.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 20l4 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef RAMSTAGE_LOADER_H +#define RAMSTAGE_LOADER_H + +#include <stdint.h> +struct cbmem_entry; + +/* Run ramstage from romstage. */ +void run_ramstage(void); + +struct ramstage_loader_ops { + const char *name; + void *(*load)(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry); +}; + +#endif /* RAMSTAGE_LOADER_H */ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 699838a..307babd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -41,6 +41,7 @@ struct romstage_handoff { }; #if defined(__PRE_RAM__) +#if CONFIG_EARLY_CBMEM_INIT /* The romstage_handoff_find_or_add() function provides the necessary logic * for initializing the romstage_handoff structure in cbmem. Different components * of the romstage may be responsible for setting up different fields. Therefore @@ -63,7 +64,14 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) return handoff; } -#endif +#else /* CONFIG_EARLY_CBMEM_INIT */ +static inline struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + return NULL; +} +#endif /* CONFIG_EARLY_CBMEM_INIT */ + +#endif /* defined(__PRE_RAM__) */ #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 18b30ef..55a946f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -16,6 +16,7 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-y += loaders bootblock-y += cbfs.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..f2a2587 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -123,58 +123,6 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -#if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) - -#include <rmodule.h> -#include <romstage_handoff.h> -static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, - struct romstage_handoff *handoff) -{ - struct rmod_stage_load rmod_ram = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = name, - }; - - if (rmodule_stage_load_from_cbfs(&rmod_ram)) { - printk(BIOS_DEBUG, "Could not load ramstage.\n"); - return (void *) -1; - } - - cache_loaded_ramstage(handoff, rmod_ram.cbmem_entry, rmod_ram.entry); - - return rmod_ram.entry; -} - -void * cbfs_load_stage(struct cbfs_media *media, const char *name) -{ - struct romstage_handoff *handoff; - const struct cbmem_entry *ramstage; - void *entry; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) { - LOG("Couldn't find or allocate romstage handoff.\n"); - return load_stage_from_cbfs(media, name, handoff); - } else if (!handoff->s3_resume) - return load_stage_from_cbfs(media, name, handoff); - - ramstage = cbmem_entry_find(CBMEM_ID_RAMSTAGE); - - if (ramstage == NULL) - return load_stage_from_cbfs(media, name, handoff); - - /* S3 resume path. Load a cached copy of the loaded ramstage. If - * return value is NULL load from cbfs. */ - entry = load_cached_ramstage(handoff, ramstage); - if (entry == NULL) - return load_stage_from_cbfs(media, name, handoff); - - return entry; -} - -#else - void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) @@ -211,7 +159,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ #if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc new file mode 100644 index 0000000..eceaa00 --- /dev/null +++ b/src/lib/loaders/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += cbfs_ramstage_loader.c +romstage-y += load_and_run_ramstage.c diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c new file mode 100644 index 0000000..6e5fe8e --- /dev/null +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <cbfs.h> +#include <arch/stages.h> +#include <ramstage_loader.h> +#include <timestamp.h> + +#if CONFIG_RELOCATABLE_RAMSTAGE +#include <rmodule.h> + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **entry) +{ + struct rmod_stage_load rmod_ram = { + .cbmem_id = cbmem_id, + .name = name, + }; + + if (rmodule_stage_load_from_cbfs(&rmod_ram)) { + printk(BIOS_DEBUG, "Could not load ramstage.\n"); + return NULL; + } + + *cbmem_entry = rmod_ram.cbmem_entry; + + return rmod_ram.entry; +} + +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name); + + if ((void *)entry == (void *) -1) + entry = NULL; + + return entry; +} + +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ + +const struct ramstage_loader_ops cbfs_ramstage_loader = { + .name = "CBFS", + .load = cbfs_load_ramstage, +}; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c new file mode 100644 index 0000000..a4c400a --- /dev/null +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 20l4 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <cbmem.h> +#include <ramstage_loader.h> +#include <romstage_handoff.h> +#include <timestamp.h> + +extern const struct ramstage_loader_ops cbfs_ramstage_loader; +extern const struct ramstage_loader_ops vboot_ramstage_loader; + +static const struct ramstage_loader_ops *loaders[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_ramstage_loader, +#endif + &cbfs_ramstage_loader, +}; + +static const char *ramstage_name = CONFIG_CBFS_PREFIX "/coreboot_ram"; +static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; + +static void +load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) +{ + const struct cbmem_entry *cbmem_entry; + void *entry_point; + + timestamp_add_now(TS_START_COPYRAM); + entry_point = ops->load(ramstage_id, ramstage_name, &cbmem_entry); + + if (entry_point == NULL) + return; + + cache_loaded_ramstage(handoff, cbmem_entry, entry_point); + + timestamp_add_now(TS_END_COPYRAM); + + stage_exit(entry_point); +} + +static void run_ramstage_from_resume(struct romstage_handoff *handoff) +{ + void *entry; + const struct cbmem_entry *cbmem_entry; + + if (handoff != NULL && handoff->s3_resume) { + cbmem_entry = cbmem_entry_find(ramstage_id); + + /* No place to load ramstage. */ + if (cbmem_entry == NULL) + return; + + /* Load the cached ramstage to runtime location. */ + entry = load_cached_ramstage(handoff, cbmem_entry); + + if (entry != NULL) { + print_debug("Jumping to image.\n"); + stage_exit(entry); + } + } +} + +void run_ramstage(void) +{ + struct romstage_handoff *handoff; + const struct ramstage_loader_ops *ops; + int i; + + handoff = romstage_handoff_find_or_add(); + + run_ramstage_from_resume(handoff); + + for (i = 0; i < ARRAY_SIZE(loaders); i++) { + ops = loaders[i]; + printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); + load_ramstage(ops, handoff); + } + + die("Ramstage was not loaded!\n"); +} diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 5493801..0359c91 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,14 +46,10 @@ int recovery_mode_enabled(void); /* functions implemented in vboot.c */ void init_chromeos(int bootmode); -struct romstage_handoff; #if CONFIG_VBOOT_VERIFY_FIRMWARE -void vboot_verify_firmware(struct romstage_handoff *handoff); void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); -#else -static inline void vboot_verify_firmware(struct romstage_handoff *h) {} #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index cc7c25d..2094657 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -141,27 +141,52 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) vboot_run_stub(&context); } -static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, - struct romstage_handoff *handoff) +static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **entry) { + struct vboot_handoff *vboot_handoff; struct cbfs_stage *stage; const struct firmware_component *fwc; struct rmod_stage_load rmod_load = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = CONFIG_CBFS_PREFIX "/coreboot_ram", + .cbmem_id = cbmem_id, + .name = name, }; + timestamp_add_now(TS_START_VBOOT); + + vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, + sizeof(*vboot_handoff)); + + if (vboot_handoff == NULL) { + printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); + return NULL; + } + + memset(vboot_handoff, 0, sizeof(*vboot_handoff)); + + vboot_invoke_wrapper(vboot_handoff); + + timestamp_add_now(TS_END_VBOOT); + + /* Take RO firmware path since no RW area was selected. */ + if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && + vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { + printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", + vboot_handoff->selected_firmware); + return NULL; + } + if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) { printk(BIOS_ERR, "Invalid ramstage index: %d\n", CONFIG_VBOOT_RAMSTAGE_INDEX); - return; + return NULL; } /* Check for invalid address. */ fwc = &vboot_handoff->components[CONFIG_VBOOT_RAMSTAGE_INDEX]; if (fwc->address == 0) { printk(BIOS_DEBUG, "RW ramstage image address invalid.\n"); - return; + return NULL; } printk(BIOS_DEBUG, "RW ramstage image at 0x%08x, 0x%08x bytes.\n", @@ -169,53 +194,18 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, stage = (void *)fwc->address; - timestamp_add_now(TS_START_COPYRAM); - if (rmodule_stage_load(&rmod_load, stage)) { vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; printk(BIOS_DEBUG, "Could not load ramstage region.\n"); - return; + return NULL; } - cache_loaded_ramstage(handoff, rmod_load.cbmem_entry, rmod_load.entry); - - timestamp_add_now(TS_END_COPYRAM); + *cbmem_entry = rmod_load.cbmem_entry; - stage_exit(rmod_load.entry); + return rmod_load.entry; } -void vboot_verify_firmware(struct romstage_handoff *handoff) -{ - struct vboot_handoff *vboot_handoff; - - /* Don't go down verified boot path on S3 resume. */ - if (handoff != NULL && handoff->s3_resume) - return; - - timestamp_add_now(TS_START_VBOOT); - - vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, - sizeof(*vboot_handoff)); - - if (vboot_handoff == NULL) { - printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); - return; - } - - memset(vboot_handoff, 0, sizeof(*vboot_handoff)); - - vboot_invoke_wrapper(vboot_handoff); - - timestamp_add_now(TS_END_VBOOT); - - /* Take RO firmware path since no RW area was selected. */ - if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && - vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { - printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", - vboot_handoff->selected_firmware); - return; - } - - /* Load ramstage from the vboot_handoff structure. */ - vboot_load_ramstage(vboot_handoff, handoff); -} +const struct ramstage_loader_ops vboot_ramstage_loader = { + .name = "VBOOT", + .vboot_load_ramstage, +};

1 0

Patch set updated for coreboot: 9828885 amd/cimx: fix sb(8|9)00 NULL type redefine
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5088 -gerrit commit 9828885d618392a08a7c1f7a101097dd0f4e547f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 22:20:01 2014 -0600 amd/cimx: fix sb(8|9)00 NULL type redefine It is inappropriate for chipset code to be redefining types -- especially NULL to a non-pointer type. There's only one non-straight forward change. A condition being checked was '!ptr_type == NULL' (0 as int). That check is actually 'ptr_type != NULL'. Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 6 +----- src/southbridge/amd/cimx/sb900/SbPlatform.h | 6 +----- src/southbridge/amd/cimx/sb900/cfg.c | 6 +++--- src/vendorcode/amd/cimx/sb800/AZALIA.c | 2 +- src/vendorcode/amd/cimx/sb800/GEC.c | 2 +- src/vendorcode/amd/cimx/sb800/SATA.c | 14 +++++++------- src/vendorcode/amd/cimx/sb800/SBCMN.c | 4 ++-- src/vendorcode/amd/cimx/sb800/SBPOR.c | 2 +- src/vendorcode/amd/cimx/sb800/USB.c | 6 +++--- src/vendorcode/amd/cimx/sb900/Azalia.c | 2 +- src/vendorcode/amd/cimx/sb900/Gec.c | 2 +- src/vendorcode/amd/cimx/sb900/Sata.c | 2 +- src/vendorcode/amd/cimx/sb900/SbCmn.c | 4 ++-- src/vendorcode/amd/cimx/sb900/Usb.c | 6 +++--- 14 files changed, 28 insertions(+), 36 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index fa7d196..ea3f719 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -24,11 +24,7 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -//#include "cbtypes.h" -#ifdef NULL - #undef NULL -#endif -#define NULL 0 +#include <stddef.h> typedef unsigned long long PLACEHOLDER; diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 5e41978..176ad87 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -24,11 +24,7 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -//#include "cbtypes.h" -#ifdef NULL - #undef NULL -#endif -#define NULL 0 +#include <stddef.h> typedef unsigned long long PLACEHOLDER; diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index 58c0abe..ac7e551 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -178,7 +178,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) // sb_config->HpetMsiDis = 0; // Field Retired // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired // sb_config->PcibAutoClkCtr = 0; // Field Retired - sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used @@ -213,7 +213,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->TempMMIO = NULL; // CIMx Internal Used + sb_config->TempMMIO = (typeof(sb_config->TempMMIO))NULL; // CIMx Internal Used // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option @@ -296,7 +296,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_config) sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option sb_config->NbSbGen2 = NB_SB_GEN2; // External Option sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option - sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level sb_config->sdbEnable = 0; // CIMx Internal Used sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c index edd335f..f3eeb23 100644 --- a/src/vendorcode/amd/cimx/sb800/AZALIA.c +++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c @@ -284,7 +284,7 @@ azaliaInitAfterPciEnum ( if ( pConfig->AzaliaController != 1 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); - if ( pConfig->BuildParameters.AzaliaSsid != NULL ) { + if ( pConfig->BuildParameters.AzaliaSsid ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); } ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c index 6ee142f..582181b 100644 --- a/src/vendorcode/amd/cimx/sb800/GEC.c +++ b/src/vendorcode/amd/cimx/sb800/GEC.c @@ -113,7 +113,7 @@ gecInitAfterPciEnum ( ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); dbTemp = 0x07; WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp); - if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) { + if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) { GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 5966ec8..a301208 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -258,7 +258,7 @@ sataInitBeforePciEnum ( UINT16 i; SATAPHYSETTING *pPhyTable; - ddTempVar = NULL; + ddTempVar = 0; // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h // BIT4: Disable fast boot RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4); @@ -292,17 +292,17 @@ sataInitBeforePciEnum ( //Set PATA controller to native mode RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); } - if (pConfig->BuildParameters.IdeSsid != NULL ) { + if (pConfig->BuildParameters.IdeSsid != 0 ) { RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); } // SATA Controller Class ID & SSID pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); - if ( pConfig->BuildParameters.SataIDESsid != NULL ) { + if ( pConfig->BuildParameters.SataIDESsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataIDESsid; } dwDeviceId = pDeviceIdptr[dbValue]; if ( pConfig->SataClass == RAID_MODE) { - if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) { + if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) { ddTempVar = pConfig->BuildParameters.SataRAID5Ssid; } dwDeviceId = V_SB_SATA_RAID5_DID; @@ -310,19 +310,19 @@ sataInitBeforePciEnum ( getEfuseStatus (&pValue); if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) { dwDeviceId = V_SB_SATA_RAID_DID; - if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) { + if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataRAIDSsid; } } } if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) || ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) { - if ( pConfig->BuildParameters.SataAHCISsid != NULL ) { + if ( pConfig->BuildParameters.SataAHCISsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataAHCISsid; } } RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); - if ( ddTempVar != NULL ) { + if ( ddTempVar != 0 ) { RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); } // SATA IRQ Resource diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index ea1c029..07adf56 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -378,7 +378,7 @@ commonInitEarlyBoot ( RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); //Early post initialization of pci config space programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); - if ( pConfig->BuildParameters.SmbusSsid != NULL ) { + if ( pConfig->BuildParameters.SmbusSsid != 0 ) { RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); } //Make BAR registers of smbus invisible. @@ -388,7 +388,7 @@ commonInitEarlyBoot ( // LPC CFG programming // // SSID for LPC Controller - if (pConfig->BuildParameters.LpcSsid != NULL ) { + if (pConfig->BuildParameters.LpcSsid != 0 ) { RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); } // LPC MSI diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c index daf13c7..752c64e 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPOR.c +++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c @@ -150,7 +150,7 @@ sbPowerOnInit ( cimNbSbGen2 = pConfig->NbSbGen2; cimSataMode = pConfig->SATAMODE.SataModeReg; // Adding Fast Read Function support - if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) { + if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) { cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; } else { cimSpiFastReadEnable = cimSpiFastReadEnableDefault; diff --git a/src/vendorcode/amd/cimx/sb800/USB.c b/src/vendorcode/amd/cimx/sb800/USB.c index 0918e3a..c9e1b24 100644 --- a/src/vendorcode/amd/cimx/sb800/USB.c +++ b/src/vendorcode/amd/cimx/sb800/USB.c @@ -196,7 +196,7 @@ EhciInitAfterPciInit ( if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { //Enable Memory access RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - if (pConfig->BuildParameters.EhciSsid != NULL ) { + if (pConfig->BuildParameters.EhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); } //USB Common PHY CAL & Control Register setting @@ -308,7 +308,7 @@ usb4OhciInitAfterPciInit ( UINT32 ddDeviceId; ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); OhciInitAfterPciInit (ddDeviceId, pConfig); - if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + if (pConfig->BuildParameters.Ohci4Ssid != 0 ) { RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); } } @@ -327,7 +327,7 @@ OhciInitAfterPciInit ( // SB02186 RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00); if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { - if ( pConfig->BuildParameters.OhciSsid != NULL ) { + if ( pConfig->BuildParameters.OhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); } } diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c index 3fe4647..7a1277c 100644 --- a/src/vendorcode/amd/cimx/sb900/Azalia.c +++ b/src/vendorcode/amd/cimx/sb900/Azalia.c @@ -282,7 +282,7 @@ azaliaInitAfterPciEnum ( if ( pConfig->AzaliaController != 1 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); - if ( pConfig->BuildParameters.AzaliaSsid != NULL ) { + if ( pConfig->BuildParameters.AzaliaSsid != 0 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); } ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); diff --git a/src/vendorcode/amd/cimx/sb900/Gec.c b/src/vendorcode/amd/cimx/sb900/Gec.c index cfd830d..4afd6e9 100644 --- a/src/vendorcode/amd/cimx/sb900/Gec.c +++ b/src/vendorcode/amd/cimx/sb900/Gec.c @@ -109,7 +109,7 @@ gecInitAfterPciEnum ( VOID* GecRomAddress; VOID* GecShadowRomAddress; UINT32 ddTemp; - if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) { + if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) { GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c index fca8005..5c3a621 100644 --- a/src/vendorcode/amd/cimx/sb900/Sata.c +++ b/src/vendorcode/amd/cimx/sb900/Sata.c @@ -458,7 +458,7 @@ sataInitBeforePciEnum ( //Set PATA controller to native mode RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); } - if (pConfig->BuildParameters.IdeSsid != NULL ) { + if (pConfig->BuildParameters.IdeSsid != 0 ) { RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); } // SATA Controller Class ID & SSID diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c index 29f6fd1..bd50dde 100644 --- a/src/vendorcode/amd/cimx/sb900/SbCmn.c +++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c @@ -398,7 +398,7 @@ commonInitEarlyBoot ( RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); //Early post initialization of pci config space programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); - if ( pConfig->BuildParameters.SmbusSsid != NULL ) { + if ( pConfig->BuildParameters.SmbusSsid != 0 ) { RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); } //Make BAR registers of smbus invisible. @@ -408,7 +408,7 @@ commonInitEarlyBoot ( // LPC CFG programming // // SSID for LPC Controller - if (pConfig->BuildParameters.LpcSsid != NULL ) { + if (pConfig->BuildParameters.LpcSsid != 0 ) { RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); } // LPC MSI diff --git a/src/vendorcode/amd/cimx/sb900/Usb.c b/src/vendorcode/amd/cimx/sb900/Usb.c index 2ae03b3..2d635ec 100644 --- a/src/vendorcode/amd/cimx/sb900/Usb.c +++ b/src/vendorcode/amd/cimx/sb900/Usb.c @@ -357,7 +357,7 @@ EhciInitAfterPciInit ( if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { //Enable Memory access RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - if (pConfig->BuildParameters.EhciSsid != NULL ) { + if (pConfig->BuildParameters.EhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); } //USB Common PHY CAL & Control Register setting @@ -571,7 +571,7 @@ usb4OhciInitAfterPciInit ( UINT32 ddDeviceId; ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); OhciInitAfterPciInit (ddDeviceId, pConfig); - if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + if (pConfig->BuildParameters.Ohci4Ssid != 0 ) { RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); } } @@ -595,7 +595,7 @@ OhciInitAfterPciInit ( // RPR USB SMI Handshake RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00); if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { - if ( pConfig->BuildParameters.OhciSsid != NULL ) { + if ( pConfig->BuildParameters.OhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); } }

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coreboot-gerrit January 2014