Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4908
-gerrit
commit a6e6bbf7fbf08c5947efb704634f511bd758b4ec
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Oct 29 10:43:53 2013 -0500
rambi: don't mark graphics as write-combining
We are currently running out of MTRRs with this CPU when
marking the graphics memory as write-combining. The reason
is that the graphics stolen memory was bumped to 64MiB which
changes the address space enough that the MTRRs are exhausted.
BUG=None
BRANCH=None
TEST=Built and analyzed MTRR usage. Also noted clearing upper
2GiB of memory in depthcharge does not take forever.
Change-Id: I2eb0168990a5c585605f958e1cbc9ec1a2322d1d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174653
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/rambi/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig
index 1e2cc33..4c3b43b 100644
--- a/src/mainboard/google/rambi/Kconfig
+++ b/src/mainboard/google/rambi/Kconfig
@@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select MAINBOARD_HAS_CHROMEOS
select CHROMEOS
- select MARK_GRAPHICS_MEM_WRCOMB
config VBOOT_RAMSTAGE_INDEX
hex
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4915
-gerrit
commit 06f7535264b57560e4d8f0f3c89597960c6b7b01
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Oct 31 10:10:20 2013 -0700
rambi: Enable internal keyboard
The EC LPC init function needs to run to enable the internal keyboard.
I needed this to confirm that it is just USB keyboards that are causing
all sorts of issues.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=boot to recovery screen and hit tab
Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175207
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 10 +++++++++-
src/soc/intel/baytrail/southcluster.c | 2 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index e7f86ce..66d98ed 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -38,7 +38,15 @@ chip soc/intel/baytrail
device pci 1e.3 off end # HSUART1
device pci 1e.4 on end # HSUART2
device pci 1e.5 on end # SPI
- device pci 1f.0 on end # LPC Bridge
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index b16a9cf..a3a1a22 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -321,7 +321,7 @@ static struct device_operations device_ops = {
.enable_resources = NULL,
.init = NULL,
.enable = southcluster_enable_dev,
- .scan_bus = NULL,
+ .scan_bus = scan_static_bus,
.ops_pci = &soc_pci_ops,
};
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4914
-gerrit
commit 0bdb80ee9fa524e107ec33a2f3a79202476f0681
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Mon Oct 28 16:43:17 2013 -0700
rambi: Enable SATA port
Enable first SATA port in Rambi device tree.
BUG=chrome-os-partner:23643
TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is
detected, and kernel is found + booted.
Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174916
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 3086ebf..e7f86ce 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -1,4 +1,10 @@
chip soc/intel/baytrail
+
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+
device cpu_cluster 0 on
device lapic 0 on end
end