Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4846
-gerrit
commit 288c0dc0b84d477de9bcdd55f66e11d8c77c8b6b
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 27 16:39:17 2014 -0600
x86/mtrr: don't assume size of ROM cached during CAR mode
Romstage and ramstage can use 2 different values for the
amount of ROM to cache just under 4GiB in the address
space. Don't assume a cpu's romstage caching policy
for the ROM.
Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/include/cpu/x86/mtrr.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index bbcde8a..9414687 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -134,10 +134,6 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type);
#define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12)
-#if ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) * 1UL > CACHE_ROM_BASE * 1UL)
-# error "CAR region (WB) and flash (WP) regions overlap."
-#endif
-
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
#endif
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5022
-gerrit
commit 3fb6caa5149edfaf0c903e1b6855bf87573f5ff0
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Dec 13 13:02:46 2013 -0800
chromeos: add VBOOT_REFCODE_INDEX option
Certain platforms need to have reference code
packaged and verified through vboot. Therefore,
add this option.
BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built.
Change-Id: Iea4b96bcf334289edbc872a253614bb1bebe196a
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180025
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/vendorcode/google/chromeos/Kconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index a564608..2f17b7e 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -110,6 +110,14 @@ config VBOOT_RAMSTAGE_INDEX
This is the index of the ramstage component in the verified
firmware block.
+config VBOOT_REFCODE_INDEX
+ hex "Reference code firmware index"
+ default 1
+ depends on VBOOT_VERIFY_FIRMWARE
+ help
+ This is the index of the reference code component in the verified
+ firmware block.
+
config NO_TPM_RESUME
bool
default n
the following patch was just integrated into master:
commit 0b7aa722e85aee19c612103c51a7bbcc73012091
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 27 15:08:27 2014 -0600
chromeos: include stddef to fix compilation error
As some of the standard definitions were shuffled around
chromeos started failing to build. Correct this.
Change-Id: I9927441ccb2d646e8b3395e6e9f8e8166de74ab0
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/4844 for details.
-gerrit
the following patch was just integrated into master:
commit 11e496b6c605e8b292f1b8179500551ba2db84a2
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Jan 27 15:07:26 2014 -0600
x86: include header to define types in use
The tsc header is using u32 w/o including the file
with defines it.
Change-Id: I9fcad882d25e93b4c0032b32abd2432b0169a068
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/4843 for details.
-gerrit
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4961
-gerrit
commit 495aa093992866b7ab0aa8dbc4eb07711d50454d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Nov 11 15:01:39 2013 -0600
rambi: disable HDA device
For some reason HDA can now be disabled. It's unclear what changes
in the baytrail code allowed this to happen, sadly.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Noted hda is not in lspci.
Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176394
---
src/mainboard/google/rambi/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index a5fe37e..88785c0 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -44,7 +44,7 @@ chip soc/intel/baytrail
device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7
device pci 1a.0 on end # TXE
- device pci 1b.0 on end # HDA
+ device pci 1b.0 off end # HDA
device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3