WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4300
-gerrit
commit b4bd65daac691408b7298d7d6ea9e6ed0f3f8251
Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Date: Mon Dec 2 10:18:04 2013 +0800
AMD hudson and yangtze: add IMC fan control support
imc_reg_init: init fan control related registers.
enable_imc_thermal_zone: AGESA does not enable thermal zone. We enable
it here.
Change-Id: I93c729982d78b6d2c7c20bcb1a3e27a7dd0eba91
Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
---
src/southbridge/amd/agesa/hudson/Makefile.inc | 3 +
src/southbridge/amd/agesa/hudson/imc.c | 89 +++++++++++++++++++++++++++
src/southbridge/amd/agesa/hudson/imc.h | 26 ++++++++
3 files changed, 118 insertions(+)
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index 6a097fc..54a93d2 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -19,6 +19,9 @@ romstage-y += early_setup.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c
+romstage-y += imc.c
+ramstage-y += imc.c
+
# ROMSIG At ROMBASE + 0x20000:
# +-----------+---------------+----------------+------------+
# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
new file mode 100644
index 0000000..af9e865
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "imc.h"
+#include <arch/io.h>
+#include <delay.h>
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Fch.h"
+#include "FchCommonCfg.h"
+#include "FchPlatform.h"
+
+void imc_reg_init(void)
+{
+ /* Init Power Management Block 2 (PM2) Registers.
+ * Check BKDG for AMD Family 16h for details. */
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff);
+
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff);
+#endif
+
+#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ UINT8 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 0x3, 0x1E4);
+ LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
+ PciData &= (UINT8)0x8F;
+ PciData |= 0x10;
+ LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
+#endif
+}
+
+#ifndef __PRE_RAM__
+void enable_imc_thermal_zone(void)
+{
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT8 FunNum;
+ UINT8 regs[9];
+ int i;
+
+ regs[0] = 0;
+ regs[1] = 0;
+ FunNum = Fun_80;
+ for (i=0; i<=1; i++)
+ WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader);
+ WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number
+ WaitForEcLDN9MailboxCmdAck(&StdHeader);
+
+ for (i=2; i<=9; i++)
+ ReadECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader);
+
+ /* enable thermal zone 0 */
+ regs[2] |= 1;
+ regs[0] = 0;
+ regs[1] = 0;
+ FunNum = Fun_81;
+ for (i=0; i<=9; i++)
+ WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader);
+ WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number
+ WaitForEcLDN9MailboxCmdAck(&StdHeader);
+}
+#endif
diff --git a/src/southbridge/amd/agesa/hudson/imc.h b/src/southbridge/amd/agesa/hudson/imc.h
new file mode 100644
index 0000000..d348319
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/imc.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef HUDSON_IMC_H
+#define HUDSON_IMC_H
+
+void imc_reg_init(void);
+void enable_imc_thermal_zone(void);
+
+#endif
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4709
-gerrit
commit b12461e1127f3002d3f53911a22d6b38bf44c7e7
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sat Jan 18 12:26:13 2014 +0200
usbdebug: Remove duplicate port claim
This claim is useless when done before EHCI controller reset. Code in
usbdebug_init_() already sets this properly after reset, see use of
DBGP_OWNER.
Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/southbridge/intel/common/usb_debug.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index 9fe22cd..fdfe6a2 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -64,8 +64,6 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
- u32 dbgctl;
-
/* Bail out. No console to complain in. */
if (!dev)
return;
@@ -75,9 +73,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
-
- /* Force ownership of the Debug Port to the EHCI controller. */
- dbgctl = read32(base + CONFIG_EHCI_DEBUG_OFFSET);
- dbgctl |= (1 << 30);
- write32(base + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
}
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4708
-gerrit
commit 72c89db13faaf76df6470962636eef8157759f52
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Sat Jan 18 02:05:17 2014 +0100
nehalem: Move mrc.cache to 0xfffe0000.
On nehalem there is no MRC.bin. To avoid excessively fragment the CBFS,
put MRC.bin as high as possible.
Change-Id: Ia3f7aef5a1e62a42c9fa9ea0f6eec2b29eb6722d
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/northbridge/intel/nehalem/Makefile.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index 6c53f49..0115501 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -37,7 +37,7 @@ $(obj)/mrc.cache:
cbfs-files-y += mrc.cache
mrc.cache-file := $(obj)/mrc.cache
-mrc.cache-position := 0xfff80000
+mrc.cache-position := 0xfffe0000
mrc.cache-type := 0xac
$(obj)/northbridge/intel/nehalem/acpi.ramstage.o : $(obj)/build.h
Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4704
-gerrit
commit 7d665bf696d4d4f07f72ab103401db026745ae2e
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Jan 17 21:56:26 2014 +0100
boardstatus: Fix board_info.txt for Nokia IP530
Change-Id: I64cd4a75d7b0c2a2ad1a98d7160524a9571534a0
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
---
src/mainboard/nokia/ip530/board_info.txt | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/nokia/ip530/board_info.txt b/src/mainboard/nokia/ip530/board_info.txt
index bcf70fd..af50885 100644
--- a/src/mainboard/nokia/ip530/board_info.txt
+++ b/src/mainboard/nokia/ip530/board_info.txt
@@ -1,7 +1,6 @@
-Board name: IP530IP530
+Board name: IP530
Category: server
-Board URL: [Nokia
-Board page: Nokia IP530
+Board page: Nokia_IP530
ROM package: TSOP48
ROM protocol: Parallel
ROM socketed: n