coreboot-gerrit January 2014

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Patch set updated for coreboot: 1050d73 coreboot: infrastructure for different ramstage loaders
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5087 -gerrit commit 1050d73a7ad6080329fdad9cf8787f796b5ccda9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 17:19:46 2014 -0600 coreboot: infrastructure for different ramstage loaders There are 2 methods currently available in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset to support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/lib/cbfs_and_run.c | 21 +----- src/cpu/intel/haswell/romstage.c | 2 - src/include/cbfs.h | 22 +++++- src/include/cbmem.h | 5 ++ src/include/ramstage_loader.h | 34 +++++++++ src/include/romstage_handoff.h | 10 ++- src/lib/Makefile.inc | 1 + src/lib/cbfs.c | 53 -------------- src/lib/loaders/Makefile.inc | 21 ++++++ src/lib/loaders/cbfs_ramstage_loader.c | 67 +++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 100 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/chromeos.h | 4 -- src/vendorcode/google/chromeos/vboot_loader.c | 87 ++++++++++------------ 13 files changed, 297 insertions(+), 130 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 3d56e19..ca8d61b 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -17,27 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <cbfs.h> #include <arch/stages.h> -#include <timestamp.h> - -static void cbfs_and_run_core(const char *filename) -{ - u8 *dst; - - timestamp_add_now(TS_START_COPYRAM); - print_debug("Loading image.\n"); - dst = cbfs_load_stage(CBFS_DEFAULT_MEDIA, filename); - if ((void *)dst == (void *) -1) - die("FATAL: Essential component is missing.\n"); - - timestamp_add_now(TS_END_COPYRAM); - print_debug("Jumping to image.\n"); - stage_exit(dst); -} +#include <ramstage_loader.h> void asmlinkage copy_and_run(void) { - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram"); + run_ramstage(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 60a1c3a..9e27668 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -309,8 +309,6 @@ void romstage_after_car(void) prepare_for_resume(handoff); - vboot_verify_firmware(handoff); - /* Load the ramstage. */ copy_and_run(); } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index c05566d..9ce862b 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -83,6 +83,10 @@ void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); +#if defined(__PRE_RAM__) +struct romstage_handoff; +struct cbmem_entry; + #if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) /* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined * to be weak so that board and chipset code may override them. Their job is to @@ -90,9 +94,6 @@ int init_default_cbfs_media(struct cbfs_media *media); * relocated ramstage is saved using the cbmem infrastructure. These * functions are only valid during romstage. */ -struct romstage_handoff; -struct cbmem_entry; - /* The implementer of cache_loaded_ramstage() may use the romstage_handoff * structure to store information, but note that the handoff variable can be * NULL. The ramstage cbmem_entry represents the region occupied by the loaded @@ -105,7 +106,22 @@ cache_loaded_ramstage(struct romstage_handoff *handoff, void * __attribute__((weak)) load_cached_ramstage(struct romstage_handoff *handoff, const struct cbmem_entry *ramstage); +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static inline void cache_loaded_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage, void *entry_point) +{ +} + +static inline void * +load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage) +{ + return NULL; +} + #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ +#endif /* defined(__PRE_RAM__) */ #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9e68ba9..b47a847 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -66,6 +66,7 @@ #define CBMEM_ID_HOB_POINTER 0x484f4221 #ifndef __ASSEMBLER__ +#include <stddef.h> #include <stdint.h> struct cbmem_entry; @@ -150,6 +151,10 @@ void cbmem_late_set_table(uint64_t base, uint64_t size); void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); +static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) +{ + return NULL; +} #endif /* CONFIG_DYNAMIC_CBMEM */ /* Common API between cbmem and dynamic cbmem. */ diff --git a/src/include/ramstage_loader.h b/src/include/ramstage_loader.h new file mode 100644 index 0000000..ad085c0 --- /dev/null +++ b/src/include/ramstage_loader.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef RAMSTAGE_LOADER_H +#define RAMSTAGE_LOADER_H + +#include <stdint.h> +struct cbmem_entry; + +/* Run ramstage from romstage. */ +void run_ramstage(void); + +struct ramstage_loader_ops { + const char *name; + void *(*load)(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry); +}; + +#endif /* RAMSTAGE_LOADER_H */ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 699838a..307babd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -41,6 +41,7 @@ struct romstage_handoff { }; #if defined(__PRE_RAM__) +#if CONFIG_EARLY_CBMEM_INIT /* The romstage_handoff_find_or_add() function provides the necessary logic * for initializing the romstage_handoff structure in cbmem. Different components * of the romstage may be responsible for setting up different fields. Therefore @@ -63,7 +64,14 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) return handoff; } -#endif +#else /* CONFIG_EARLY_CBMEM_INIT */ +static inline struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + return NULL; +} +#endif /* CONFIG_EARLY_CBMEM_INIT */ + +#endif /* defined(__PRE_RAM__) */ #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 18b30ef..55a946f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -16,6 +16,7 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-y += loaders bootblock-y += cbfs.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..f2a2587 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -123,58 +123,6 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -#if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) - -#include <rmodule.h> -#include <romstage_handoff.h> -static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, - struct romstage_handoff *handoff) -{ - struct rmod_stage_load rmod_ram = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = name, - }; - - if (rmodule_stage_load_from_cbfs(&rmod_ram)) { - printk(BIOS_DEBUG, "Could not load ramstage.\n"); - return (void *) -1; - } - - cache_loaded_ramstage(handoff, rmod_ram.cbmem_entry, rmod_ram.entry); - - return rmod_ram.entry; -} - -void * cbfs_load_stage(struct cbfs_media *media, const char *name) -{ - struct romstage_handoff *handoff; - const struct cbmem_entry *ramstage; - void *entry; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) { - LOG("Couldn't find or allocate romstage handoff.\n"); - return load_stage_from_cbfs(media, name, handoff); - } else if (!handoff->s3_resume) - return load_stage_from_cbfs(media, name, handoff); - - ramstage = cbmem_entry_find(CBMEM_ID_RAMSTAGE); - - if (ramstage == NULL) - return load_stage_from_cbfs(media, name, handoff); - - /* S3 resume path. Load a cached copy of the loaded ramstage. If - * return value is NULL load from cbfs. */ - entry = load_cached_ramstage(handoff, ramstage); - if (entry == NULL) - return load_stage_from_cbfs(media, name, handoff); - - return entry; -} - -#else - void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) @@ -211,7 +159,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ #if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc new file mode 100644 index 0000000..eceaa00 --- /dev/null +++ b/src/lib/loaders/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += cbfs_ramstage_loader.c +romstage-y += load_and_run_ramstage.c diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c new file mode 100644 index 0000000..5d5cc0b --- /dev/null +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <cbfs.h> +#include <arch/stages.h> +#include <ramstage_loader.h> +#include <timestamp.h> + +#if CONFIG_RELOCATABLE_RAMSTAGE +#include <rmodule.h> + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + struct rmod_stage_load rmod_ram = { + .cbmem_id = cbmem_id, + .name = name, + }; + + if (rmodule_stage_load_from_cbfs(&rmod_ram)) { + printk(BIOS_DEBUG, "Could not load ramstage.\n"); + return NULL; + } + + *cbmem_entry = rmod_ram.cbmem_entry; + + return rmod_ram.entry; +} + +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name); + + if ((void *)entry == (void *) -1) + entry = NULL; + + return entry; +} + +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ + +const struct ramstage_loader_ops cbfs_ramstage_loader = { + .name = "CBFS", + .load = cbfs_load_ramstage, +}; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c new file mode 100644 index 0000000..be2be82 --- /dev/null +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <cbmem.h> +#include <ramstage_loader.h> +#include <romstage_handoff.h> +#include <timestamp.h> + +extern const struct ramstage_loader_ops cbfs_ramstage_loader; +extern const struct ramstage_loader_ops vboot_ramstage_loader; + +static const struct ramstage_loader_ops *loaders[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_ramstage_loader, +#endif + &cbfs_ramstage_loader, +}; + +static const char *ramstage_name = CONFIG_CBFS_PREFIX "/coreboot_ram"; +static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; + +static void +load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) +{ + const struct cbmem_entry *cbmem_entry; + void *entry_point; + + timestamp_add_now(TS_START_COPYRAM); + entry_point = ops->load(ramstage_id, ramstage_name, &cbmem_entry); + + if (entry_point == NULL) + return; + + cache_loaded_ramstage(handoff, cbmem_entry, entry_point); + + timestamp_add_now(TS_END_COPYRAM); + + stage_exit(entry_point); +} + +static void run_ramstage_from_resume(struct romstage_handoff *handoff) +{ + void *entry; + const struct cbmem_entry *cbmem_entry; + + if (handoff != NULL && handoff->s3_resume) { + cbmem_entry = cbmem_entry_find(ramstage_id); + + /* No place to load ramstage. */ + if (cbmem_entry == NULL) + return; + + /* Load the cached ramstage to runtime location. */ + entry = load_cached_ramstage(handoff, cbmem_entry); + + if (entry != NULL) { + print_debug("Jumping to image.\n"); + stage_exit(entry); + } + } +} + +void run_ramstage(void) +{ + struct romstage_handoff *handoff; + const struct ramstage_loader_ops *ops; + int i; + + handoff = romstage_handoff_find_or_add(); + + run_ramstage_from_resume(handoff); + + for (i = 0; i < ARRAY_SIZE(loaders); i++) { + ops = loaders[i]; + printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); + load_ramstage(ops, handoff); + } + + die("Ramstage was not loaded!\n"); +} diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 5493801..0359c91 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,14 +46,10 @@ int recovery_mode_enabled(void); /* functions implemented in vboot.c */ void init_chromeos(int bootmode); -struct romstage_handoff; #if CONFIG_VBOOT_VERIFY_FIRMWARE -void vboot_verify_firmware(struct romstage_handoff *handoff); void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); -#else -static inline void vboot_verify_firmware(struct romstage_handoff *h) {} #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index cc7c25d..0c5220a 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -26,6 +26,7 @@ #include <console/vtxprintf.h> #include <pc80/tpm.h> #include <reset.h> +#include <ramstage_loader.h> #include <romstage_handoff.h> #include <rmodule.h> #include <string.h> @@ -141,27 +142,52 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) vboot_run_stub(&context); } -static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, - struct romstage_handoff *handoff) +static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) { + struct vboot_handoff *vboot_handoff; struct cbfs_stage *stage; const struct firmware_component *fwc; struct rmod_stage_load rmod_load = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = CONFIG_CBFS_PREFIX "/coreboot_ram", + .cbmem_id = cbmem_id, + .name = name, }; + timestamp_add_now(TS_START_VBOOT); + + vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, + sizeof(*vboot_handoff)); + + if (vboot_handoff == NULL) { + printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); + return NULL; + } + + memset(vboot_handoff, 0, sizeof(*vboot_handoff)); + + vboot_invoke_wrapper(vboot_handoff); + + timestamp_add_now(TS_END_VBOOT); + + /* Take RO firmware path since no RW area was selected. */ + if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && + vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { + printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", + vboot_handoff->selected_firmware); + return NULL; + } + if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) { printk(BIOS_ERR, "Invalid ramstage index: %d\n", CONFIG_VBOOT_RAMSTAGE_INDEX); - return; + return NULL; } /* Check for invalid address. */ fwc = &vboot_handoff->components[CONFIG_VBOOT_RAMSTAGE_INDEX]; if (fwc->address == 0) { printk(BIOS_DEBUG, "RW ramstage image address invalid.\n"); - return; + return NULL; } printk(BIOS_DEBUG, "RW ramstage image at 0x%08x, 0x%08x bytes.\n", @@ -169,53 +195,18 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, stage = (void *)fwc->address; - timestamp_add_now(TS_START_COPYRAM); - if (rmodule_stage_load(&rmod_load, stage)) { vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; printk(BIOS_DEBUG, "Could not load ramstage region.\n"); - return; + return NULL; } - cache_loaded_ramstage(handoff, rmod_load.cbmem_entry, rmod_load.entry); - - timestamp_add_now(TS_END_COPYRAM); + *cbmem_entry = rmod_load.cbmem_entry; - stage_exit(rmod_load.entry); + return rmod_load.entry; } -void vboot_verify_firmware(struct romstage_handoff *handoff) -{ - struct vboot_handoff *vboot_handoff; - - /* Don't go down verified boot path on S3 resume. */ - if (handoff != NULL && handoff->s3_resume) - return; - - timestamp_add_now(TS_START_VBOOT); - - vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, - sizeof(*vboot_handoff)); - - if (vboot_handoff == NULL) { - printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); - return; - } - - memset(vboot_handoff, 0, sizeof(*vboot_handoff)); - - vboot_invoke_wrapper(vboot_handoff); - - timestamp_add_now(TS_END_VBOOT); - - /* Take RO firmware path since no RW area was selected. */ - if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && - vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { - printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", - vboot_handoff->selected_firmware); - return; - } - - /* Load ramstage from the vboot_handoff structure. */ - vboot_load_ramstage(vboot_handoff, handoff); -} +const struct ramstage_loader_ops vboot_ramstage_loader = { + .name = "VBOOT", + .load = vboot_load_ramstage, +};

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Patch set updated for coreboot: d780f59 amd/cimx: fix sb(8|9)00 NULL type redefine
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5088 -gerrit commit d780f5905df20f1c0c336a90eae56b2ee5611818 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 22:20:01 2014 -0600 amd/cimx: fix sb(8|9)00 NULL type redefine It is inappropriate for chipset code to be redefining types -- especially NULL to a non-pointer type. There's only one non-straight forward change. A condition being checked was '!ptr_type == NULL' (0 as int). That check is actually 'ptr_type != NULL'. Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 6 +----- src/southbridge/amd/cimx/sb900/SbPlatform.h | 6 +----- src/southbridge/amd/cimx/sb900/cfg.c | 6 +++--- src/vendorcode/amd/cimx/sb800/AZALIA.c | 2 +- src/vendorcode/amd/cimx/sb800/GEC.c | 2 +- src/vendorcode/amd/cimx/sb800/SATA.c | 14 +++++++------- src/vendorcode/amd/cimx/sb800/SBCMN.c | 4 ++-- src/vendorcode/amd/cimx/sb800/SBPOR.c | 2 +- src/vendorcode/amd/cimx/sb800/USB.c | 6 +++--- src/vendorcode/amd/cimx/sb900/Azalia.c | 2 +- src/vendorcode/amd/cimx/sb900/Gec.c | 2 +- src/vendorcode/amd/cimx/sb900/Sata.c | 2 +- src/vendorcode/amd/cimx/sb900/SbCmn.c | 4 ++-- src/vendorcode/amd/cimx/sb900/Usb.c | 6 +++--- 14 files changed, 28 insertions(+), 36 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index fa7d196..ea3f719 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -24,11 +24,7 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -//#include "cbtypes.h" -#ifdef NULL - #undef NULL -#endif -#define NULL 0 +#include <stddef.h> typedef unsigned long long PLACEHOLDER; diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 5e41978..176ad87 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -24,11 +24,7 @@ #ifndef _AMD_SBPLATFORM_H_ #define _AMD_SBPLATFORM_H_ -//#include "cbtypes.h" -#ifdef NULL - #undef NULL -#endif -#define NULL 0 +#include <stddef.h> typedef unsigned long long PLACEHOLDER; diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index 58c0abe..ac7e551 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -178,7 +178,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) // sb_config->HpetMsiDis = 0; // Field Retired // sb_config->ResetCpuOnSyncFlood = 0; // Field Retired // sb_config->PcibAutoClkCtr = 0; // Field Retired - sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level sb_config->PORTCONFIG[0].PortCfg.PortPresent = SB_GPP_PORT0; // Board Level sb_config->PORTCONFIG[0].PortCfg.PortDetected = 0; // CIMx Internal Used sb_config->PORTCONFIG[0].PortCfg.PortIsGen2 = 0; // CIMx Internal Used @@ -213,7 +213,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->TempMMIO = NULL; // CIMx Internal Used + sb_config->TempMMIO = (typeof(sb_config->TempMMIO))NULL; // CIMx Internal Used // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option @@ -296,7 +296,7 @@ void SbPowerOnInit_Config(AMDSBCFG *sb_config) sb_config->SATAMODE.SataMode.SataClkMode = SATA_CLK_RESERVED; // Internal Option sb_config->NbSbGen2 = NB_SB_GEN2; // External Option sb_config->SataInternal100Spread = INCHIP_SATA_INTERNAL_100_SPREAD; // External Option - sb_config->OEMPROGTBL.OemProgrammingTablePtr = NULL; // Board Level + sb_config->OEMPROGTBL.OemProgrammingTablePtr = (uintptr_t)NULL; // Board Level sb_config->sdbEnable = 0; // CIMx Internal Used sb_config->Cg2Pll = INCHIP_CG2_PLL; // Internal Option diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c index edd335f..e402ae8 100644 --- a/src/vendorcode/amd/cimx/sb800/AZALIA.c +++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c @@ -284,7 +284,7 @@ azaliaInitAfterPciEnum ( if ( pConfig->AzaliaController != 1 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); - if ( pConfig->BuildParameters.AzaliaSsid != NULL ) { + if ( pConfig->BuildParameters.AzaliaSsid != 0 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); } ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c index 6ee142f..582181b 100644 --- a/src/vendorcode/amd/cimx/sb800/GEC.c +++ b/src/vendorcode/amd/cimx/sb800/GEC.c @@ -113,7 +113,7 @@ gecInitAfterPciEnum ( ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); dbTemp = 0x07; WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp); - if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) { + if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) { GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 5966ec8..a301208 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -258,7 +258,7 @@ sataInitBeforePciEnum ( UINT16 i; SATAPHYSETTING *pPhyTable; - ddTempVar = NULL; + ddTempVar = 0; // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h // BIT4: Disable fast boot RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4); @@ -292,17 +292,17 @@ sataInitBeforePciEnum ( //Set PATA controller to native mode RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); } - if (pConfig->BuildParameters.IdeSsid != NULL ) { + if (pConfig->BuildParameters.IdeSsid != 0 ) { RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); } // SATA Controller Class ID & SSID pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); - if ( pConfig->BuildParameters.SataIDESsid != NULL ) { + if ( pConfig->BuildParameters.SataIDESsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataIDESsid; } dwDeviceId = pDeviceIdptr[dbValue]; if ( pConfig->SataClass == RAID_MODE) { - if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) { + if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) { ddTempVar = pConfig->BuildParameters.SataRAID5Ssid; } dwDeviceId = V_SB_SATA_RAID5_DID; @@ -310,19 +310,19 @@ sataInitBeforePciEnum ( getEfuseStatus (&pValue); if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) { dwDeviceId = V_SB_SATA_RAID_DID; - if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) { + if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataRAIDSsid; } } } if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) || ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) { - if ( pConfig->BuildParameters.SataAHCISsid != NULL ) { + if ( pConfig->BuildParameters.SataAHCISsid != 0 ) { ddTempVar = pConfig->BuildParameters.SataAHCISsid; } } RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); - if ( ddTempVar != NULL ) { + if ( ddTempVar != 0 ) { RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); } // SATA IRQ Resource diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index ea1c029..07adf56 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -378,7 +378,7 @@ commonInitEarlyBoot ( RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); //Early post initialization of pci config space programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); - if ( pConfig->BuildParameters.SmbusSsid != NULL ) { + if ( pConfig->BuildParameters.SmbusSsid != 0 ) { RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); } //Make BAR registers of smbus invisible. @@ -388,7 +388,7 @@ commonInitEarlyBoot ( // LPC CFG programming // // SSID for LPC Controller - if (pConfig->BuildParameters.LpcSsid != NULL ) { + if (pConfig->BuildParameters.LpcSsid != 0 ) { RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); } // LPC MSI diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c index daf13c7..752c64e 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPOR.c +++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c @@ -150,7 +150,7 @@ sbPowerOnInit ( cimNbSbGen2 = pConfig->NbSbGen2; cimSataMode = pConfig->SATAMODE.SataModeReg; // Adding Fast Read Function support - if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) { + if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) { cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; } else { cimSpiFastReadEnable = cimSpiFastReadEnableDefault; diff --git a/src/vendorcode/amd/cimx/sb800/USB.c b/src/vendorcode/amd/cimx/sb800/USB.c index 0918e3a..c9e1b24 100644 --- a/src/vendorcode/amd/cimx/sb800/USB.c +++ b/src/vendorcode/amd/cimx/sb800/USB.c @@ -196,7 +196,7 @@ EhciInitAfterPciInit ( if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { //Enable Memory access RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - if (pConfig->BuildParameters.EhciSsid != NULL ) { + if (pConfig->BuildParameters.EhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); } //USB Common PHY CAL & Control Register setting @@ -308,7 +308,7 @@ usb4OhciInitAfterPciInit ( UINT32 ddDeviceId; ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); OhciInitAfterPciInit (ddDeviceId, pConfig); - if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + if (pConfig->BuildParameters.Ohci4Ssid != 0 ) { RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); } } @@ -327,7 +327,7 @@ OhciInitAfterPciInit ( // SB02186 RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00); if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { - if ( pConfig->BuildParameters.OhciSsid != NULL ) { + if ( pConfig->BuildParameters.OhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); } } diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c index 3fe4647..7a1277c 100644 --- a/src/vendorcode/amd/cimx/sb900/Azalia.c +++ b/src/vendorcode/amd/cimx/sb900/Azalia.c @@ -282,7 +282,7 @@ azaliaInitAfterPciEnum ( if ( pConfig->AzaliaController != 1 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); - if ( pConfig->BuildParameters.AzaliaSsid != NULL ) { + if ( pConfig->BuildParameters.AzaliaSsid != 0 ) { RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); } ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); diff --git a/src/vendorcode/amd/cimx/sb900/Gec.c b/src/vendorcode/amd/cimx/sb900/Gec.c index cfd830d..4afd6e9 100644 --- a/src/vendorcode/amd/cimx/sb900/Gec.c +++ b/src/vendorcode/amd/cimx/sb900/Gec.c @@ -109,7 +109,7 @@ gecInitAfterPciEnum ( VOID* GecRomAddress; VOID* GecShadowRomAddress; UINT32 ddTemp; - if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) { + if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) { GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c index fca8005..5c3a621 100644 --- a/src/vendorcode/amd/cimx/sb900/Sata.c +++ b/src/vendorcode/amd/cimx/sb900/Sata.c @@ -458,7 +458,7 @@ sataInitBeforePciEnum ( //Set PATA controller to native mode RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); } - if (pConfig->BuildParameters.IdeSsid != NULL ) { + if (pConfig->BuildParameters.IdeSsid != 0 ) { RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); } // SATA Controller Class ID & SSID diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c index 29f6fd1..bd50dde 100644 --- a/src/vendorcode/amd/cimx/sb900/SbCmn.c +++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c @@ -398,7 +398,7 @@ commonInitEarlyBoot ( RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); //Early post initialization of pci config space programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); - if ( pConfig->BuildParameters.SmbusSsid != NULL ) { + if ( pConfig->BuildParameters.SmbusSsid != 0 ) { RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); } //Make BAR registers of smbus invisible. @@ -408,7 +408,7 @@ commonInitEarlyBoot ( // LPC CFG programming // // SSID for LPC Controller - if (pConfig->BuildParameters.LpcSsid != NULL ) { + if (pConfig->BuildParameters.LpcSsid != 0 ) { RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); } // LPC MSI diff --git a/src/vendorcode/amd/cimx/sb900/Usb.c b/src/vendorcode/amd/cimx/sb900/Usb.c index 2ae03b3..2d635ec 100644 --- a/src/vendorcode/amd/cimx/sb900/Usb.c +++ b/src/vendorcode/amd/cimx/sb900/Usb.c @@ -357,7 +357,7 @@ EhciInitAfterPciInit ( if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { //Enable Memory access RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - if (pConfig->BuildParameters.EhciSsid != NULL ) { + if (pConfig->BuildParameters.EhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); } //USB Common PHY CAL & Control Register setting @@ -571,7 +571,7 @@ usb4OhciInitAfterPciInit ( UINT32 ddDeviceId; ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); OhciInitAfterPciInit (ddDeviceId, pConfig); - if (pConfig->BuildParameters.Ohci4Ssid != NULL ) { + if (pConfig->BuildParameters.Ohci4Ssid != 0 ) { RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); } } @@ -595,7 +595,7 @@ OhciInitAfterPciInit ( // RPR USB SMI Handshake RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00); if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { - if ( pConfig->BuildParameters.OhciSsid != NULL ) { + if ( pConfig->BuildParameters.OhciSsid != 0 ) { RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); } }

1 0

Patch set updated for coreboot: 9101cec x86: provide stage_exit() like arm
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5086 -gerrit commit 9101cecb3fc971083a457c63721c2b5fe9d592d3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 15:48:29 2014 -0600 x86: provide stage_exit() like arm The arm architectures have a stage_exit() function which takes a void * pointer as an entry point. Provide the same API for x86. This can make the booting paths less architecture-specific. Change-Id: I4ecfbf32f38f2e3817381b63e1f97e92654c5f97 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/stages.h | 8 ++++++++ src/arch/x86/lib/cbfs_and_run.c | 5 +---- src/vendorcode/google/chromeos/vboot_loader.c | 7 ++----- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 8cbf5da..91d0db6 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -24,4 +24,12 @@ void asmlinkage copy_and_run(void); void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); + +static inline void stage_exit(void *entry) +{ + __asm__ volatile ( + "jmp *%%edi\n" + :: "D"(entry) + ); +} #endif diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 6379842..3d56e19 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -34,10 +34,7 @@ static void cbfs_and_run_core(const char *filename) timestamp_add_now(TS_END_COPYRAM); print_debug("Jumping to image.\n"); - __asm__ volatile ( - "jmp *%%edi\n" - :: "D"(dst) - ); + stage_exit(dst); } void asmlinkage copy_and_run(void) diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index badff27..cc7c25d 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/stages.h> #include <stdint.h> #include <stddef.h> #include <cbfs.h> @@ -180,11 +181,7 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, timestamp_add_now(TS_END_COPYRAM); - __asm__ volatile ( - "movl $0, %%ebp\n" - "jmp *%%edi\n" - :: "D"(rmod_load.entry) - ); + stage_exit(rmod_load.entry); } void vboot_verify_firmware(struct romstage_handoff *handoff)

1 0

Patch set updated for coreboot: c0d7d29 coreboot: infrastructure for different ramstage loaders
by Aaron Durbin 31 Jan '14

31 Jan '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5087 -gerrit commit c0d7d29e12674467212fca242da8de0b321920a2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 17:19:46 2014 -0600 coreboot: infrastructure for different ramstage loaders There are 2 methods currently avaiable in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/lib/cbfs_and_run.c | 21 +----- src/cpu/intel/haswell/romstage.c | 2 - src/include/cbfs.h | 22 +++++- src/include/cbmem.h | 5 ++ src/include/ramstage_loader.h | 34 +++++++++ src/include/romstage_handoff.h | 10 ++- src/lib/Makefile.inc | 1 + src/lib/cbfs.c | 53 -------------- src/lib/loaders/Makefile.inc | 21 ++++++ src/lib/loaders/cbfs_ramstage_loader.c | 67 +++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 100 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/chromeos.h | 4 -- src/vendorcode/google/chromeos/vboot_loader.c | 87 ++++++++++------------ 13 files changed, 297 insertions(+), 130 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 3d56e19..ca8d61b 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -17,27 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <cbfs.h> #include <arch/stages.h> -#include <timestamp.h> - -static void cbfs_and_run_core(const char *filename) -{ - u8 *dst; - - timestamp_add_now(TS_START_COPYRAM); - print_debug("Loading image.\n"); - dst = cbfs_load_stage(CBFS_DEFAULT_MEDIA, filename); - if ((void *)dst == (void *) -1) - die("FATAL: Essential component is missing.\n"); - - timestamp_add_now(TS_END_COPYRAM); - print_debug("Jumping to image.\n"); - stage_exit(dst); -} +#include <ramstage_loader.h> void asmlinkage copy_and_run(void) { - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram"); + run_ramstage(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 60a1c3a..9e27668 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -309,8 +309,6 @@ void romstage_after_car(void) prepare_for_resume(handoff); - vboot_verify_firmware(handoff); - /* Load the ramstage. */ copy_and_run(); } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index c05566d..9ce862b 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -83,6 +83,10 @@ void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); +#if defined(__PRE_RAM__) +struct romstage_handoff; +struct cbmem_entry; + #if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) /* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined * to be weak so that board and chipset code may override them. Their job is to @@ -90,9 +94,6 @@ int init_default_cbfs_media(struct cbfs_media *media); * relocated ramstage is saved using the cbmem infrastructure. These * functions are only valid during romstage. */ -struct romstage_handoff; -struct cbmem_entry; - /* The implementer of cache_loaded_ramstage() may use the romstage_handoff * structure to store information, but note that the handoff variable can be * NULL. The ramstage cbmem_entry represents the region occupied by the loaded @@ -105,7 +106,22 @@ cache_loaded_ramstage(struct romstage_handoff *handoff, void * __attribute__((weak)) load_cached_ramstage(struct romstage_handoff *handoff, const struct cbmem_entry *ramstage); +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static inline void cache_loaded_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage, void *entry_point) +{ +} + +static inline void * +load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage) +{ + return NULL; +} + #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ +#endif /* defined(__PRE_RAM__) */ #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9e68ba9..0b6031e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -66,6 +66,7 @@ #define CBMEM_ID_HOB_POINTER 0x484f4221 #ifndef __ASSEMBLER__ +#include <stddef.h> #include <stdint.h> struct cbmem_entry; @@ -150,6 +151,10 @@ void cbmem_late_set_table(uint64_t base, uint64_t size); void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); +static inline const struct cbmem_entry *cbmem_entry_find(u32 id) +{ + return NULL; +} #endif /* CONFIG_DYNAMIC_CBMEM */ /* Common API between cbmem and dynamic cbmem. */ diff --git a/src/include/ramstage_loader.h b/src/include/ramstage_loader.h new file mode 100644 index 0000000..67003d4 --- /dev/null +++ b/src/include/ramstage_loader.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 20l4 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef RAMSTAGE_LOADER_H +#define RAMSTAGE_LOADER_H + +#include <stdint.h> +struct cbmem_entry; + +/* Run ramstage from romstage. */ +void run_ramstage(void); + +struct ramstage_loader_ops { + const char *name; + void *(*load)(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry); +}; + +#endif /* RAMSTAGE_LOADER_H */ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 699838a..307babd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -41,6 +41,7 @@ struct romstage_handoff { }; #if defined(__PRE_RAM__) +#if CONFIG_EARLY_CBMEM_INIT /* The romstage_handoff_find_or_add() function provides the necessary logic * for initializing the romstage_handoff structure in cbmem. Different components * of the romstage may be responsible for setting up different fields. Therefore @@ -63,7 +64,14 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) return handoff; } -#endif +#else /* CONFIG_EARLY_CBMEM_INIT */ +static inline struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + return NULL; +} +#endif /* CONFIG_EARLY_CBMEM_INIT */ + +#endif /* defined(__PRE_RAM__) */ #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 18b30ef..55a946f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -16,6 +16,7 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-y += loaders bootblock-y += cbfs.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..f2a2587 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -123,58 +123,6 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -#if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) - -#include <rmodule.h> -#include <romstage_handoff.h> -static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, - struct romstage_handoff *handoff) -{ - struct rmod_stage_load rmod_ram = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = name, - }; - - if (rmodule_stage_load_from_cbfs(&rmod_ram)) { - printk(BIOS_DEBUG, "Could not load ramstage.\n"); - return (void *) -1; - } - - cache_loaded_ramstage(handoff, rmod_ram.cbmem_entry, rmod_ram.entry); - - return rmod_ram.entry; -} - -void * cbfs_load_stage(struct cbfs_media *media, const char *name) -{ - struct romstage_handoff *handoff; - const struct cbmem_entry *ramstage; - void *entry; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) { - LOG("Couldn't find or allocate romstage handoff.\n"); - return load_stage_from_cbfs(media, name, handoff); - } else if (!handoff->s3_resume) - return load_stage_from_cbfs(media, name, handoff); - - ramstage = cbmem_entry_find(CBMEM_ID_RAMSTAGE); - - if (ramstage == NULL) - return load_stage_from_cbfs(media, name, handoff); - - /* S3 resume path. Load a cached copy of the loaded ramstage. If - * return value is NULL load from cbfs. */ - entry = load_cached_ramstage(handoff, ramstage); - if (entry == NULL) - return load_stage_from_cbfs(media, name, handoff); - - return entry; -} - -#else - void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) @@ -211,7 +159,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ #if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc new file mode 100644 index 0000000..eceaa00 --- /dev/null +++ b/src/lib/loaders/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += cbfs_ramstage_loader.c +romstage-y += load_and_run_ramstage.c diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c new file mode 100644 index 0000000..5d5cc0b --- /dev/null +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <cbfs.h> +#include <arch/stages.h> +#include <ramstage_loader.h> +#include <timestamp.h> + +#if CONFIG_RELOCATABLE_RAMSTAGE +#include <rmodule.h> + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + struct rmod_stage_load rmod_ram = { + .cbmem_id = cbmem_id, + .name = name, + }; + + if (rmodule_stage_load_from_cbfs(&rmod_ram)) { + printk(BIOS_DEBUG, "Could not load ramstage.\n"); + return NULL; + } + + *cbmem_entry = rmod_ram.cbmem_entry; + + return rmod_ram.entry; +} + +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name); + + if ((void *)entry == (void *) -1) + entry = NULL; + + return entry; +} + +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ + +const struct ramstage_loader_ops cbfs_ramstage_loader = { + .name = "CBFS", + .load = cbfs_load_ramstage, +}; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c new file mode 100644 index 0000000..a4c400a --- /dev/null +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 20l4 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <cbmem.h> +#include <ramstage_loader.h> +#include <romstage_handoff.h> +#include <timestamp.h> + +extern const struct ramstage_loader_ops cbfs_ramstage_loader; +extern const struct ramstage_loader_ops vboot_ramstage_loader; + +static const struct ramstage_loader_ops *loaders[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_ramstage_loader, +#endif + &cbfs_ramstage_loader, +}; + +static const char *ramstage_name = CONFIG_CBFS_PREFIX "/coreboot_ram"; +static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; + +static void +load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) +{ + const struct cbmem_entry *cbmem_entry; + void *entry_point; + + timestamp_add_now(TS_START_COPYRAM); + entry_point = ops->load(ramstage_id, ramstage_name, &cbmem_entry); + + if (entry_point == NULL) + return; + + cache_loaded_ramstage(handoff, cbmem_entry, entry_point); + + timestamp_add_now(TS_END_COPYRAM); + + stage_exit(entry_point); +} + +static void run_ramstage_from_resume(struct romstage_handoff *handoff) +{ + void *entry; + const struct cbmem_entry *cbmem_entry; + + if (handoff != NULL && handoff->s3_resume) { + cbmem_entry = cbmem_entry_find(ramstage_id); + + /* No place to load ramstage. */ + if (cbmem_entry == NULL) + return; + + /* Load the cached ramstage to runtime location. */ + entry = load_cached_ramstage(handoff, cbmem_entry); + + if (entry != NULL) { + print_debug("Jumping to image.\n"); + stage_exit(entry); + } + } +} + +void run_ramstage(void) +{ + struct romstage_handoff *handoff; + const struct ramstage_loader_ops *ops; + int i; + + handoff = romstage_handoff_find_or_add(); + + run_ramstage_from_resume(handoff); + + for (i = 0; i < ARRAY_SIZE(loaders); i++) { + ops = loaders[i]; + printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); + load_ramstage(ops, handoff); + } + + die("Ramstage was not loaded!\n"); +} diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 5493801..0359c91 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,14 +46,10 @@ int recovery_mode_enabled(void); /* functions implemented in vboot.c */ void init_chromeos(int bootmode); -struct romstage_handoff; #if CONFIG_VBOOT_VERIFY_FIRMWARE -void vboot_verify_firmware(struct romstage_handoff *handoff); void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); -#else -static inline void vboot_verify_firmware(struct romstage_handoff *h) {} #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index cc7c25d..0c5220a 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -26,6 +26,7 @@ #include <console/vtxprintf.h> #include <pc80/tpm.h> #include <reset.h> +#include <ramstage_loader.h> #include <romstage_handoff.h> #include <rmodule.h> #include <string.h> @@ -141,27 +142,52 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) vboot_run_stub(&context); } -static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, - struct romstage_handoff *handoff) +static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) { + struct vboot_handoff *vboot_handoff; struct cbfs_stage *stage; const struct firmware_component *fwc; struct rmod_stage_load rmod_load = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = CONFIG_CBFS_PREFIX "/coreboot_ram", + .cbmem_id = cbmem_id, + .name = name, }; + timestamp_add_now(TS_START_VBOOT); + + vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, + sizeof(*vboot_handoff)); + + if (vboot_handoff == NULL) { + printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); + return NULL; + } + + memset(vboot_handoff, 0, sizeof(*vboot_handoff)); + + vboot_invoke_wrapper(vboot_handoff); + + timestamp_add_now(TS_END_VBOOT); + + /* Take RO firmware path since no RW area was selected. */ + if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && + vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { + printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", + vboot_handoff->selected_firmware); + return NULL; + } + if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) { printk(BIOS_ERR, "Invalid ramstage index: %d\n", CONFIG_VBOOT_RAMSTAGE_INDEX); - return; + return NULL; } /* Check for invalid address. */ fwc = &vboot_handoff->components[CONFIG_VBOOT_RAMSTAGE_INDEX]; if (fwc->address == 0) { printk(BIOS_DEBUG, "RW ramstage image address invalid.\n"); - return; + return NULL; } printk(BIOS_DEBUG, "RW ramstage image at 0x%08x, 0x%08x bytes.\n", @@ -169,53 +195,18 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, stage = (void *)fwc->address; - timestamp_add_now(TS_START_COPYRAM); - if (rmodule_stage_load(&rmod_load, stage)) { vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; printk(BIOS_DEBUG, "Could not load ramstage region.\n"); - return; + return NULL; } - cache_loaded_ramstage(handoff, rmod_load.cbmem_entry, rmod_load.entry); - - timestamp_add_now(TS_END_COPYRAM); + *cbmem_entry = rmod_load.cbmem_entry; - stage_exit(rmod_load.entry); + return rmod_load.entry; } -void vboot_verify_firmware(struct romstage_handoff *handoff) -{ - struct vboot_handoff *vboot_handoff; - - /* Don't go down verified boot path on S3 resume. */ - if (handoff != NULL && handoff->s3_resume) - return; - - timestamp_add_now(TS_START_VBOOT); - - vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, - sizeof(*vboot_handoff)); - - if (vboot_handoff == NULL) { - printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); - return; - } - - memset(vboot_handoff, 0, sizeof(*vboot_handoff)); - - vboot_invoke_wrapper(vboot_handoff); - - timestamp_add_now(TS_END_VBOOT); - - /* Take RO firmware path since no RW area was selected. */ - if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && - vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { - printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", - vboot_handoff->selected_firmware); - return; - } - - /* Load ramstage from the vboot_handoff structure. */ - vboot_load_ramstage(vboot_handoff, handoff); -} +const struct ramstage_loader_ops vboot_ramstage_loader = { + .name = "VBOOT", + .load = vboot_load_ramstage, +};

1 0

Patch merged into coreboot/master: d22d8cf baytrail: introduce pattrs
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit d22d8cf5e792bd151f0e30d197f2c6a600a3c261 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 24 16:47:49 2013 -0500 baytrail: introduce pattrs The pattrs structure is intended for the supporting coreboot code to reference instead of going back to the source of the values (msrs, cpuid, etc). It essentially serves as a global structure for collecting attributes about the platform/processor. Additionally, the implementation provides a point during boot to hoook work before device enumeration/initialization by providing a init() function to soc_intel_baytrail_ops that is called before device work in the boot state machine. BUG=chrome-os-partner:22862 BUG=chrome-os-partner:22863 BRANCH=None TEST=Built and booted. Noted pattrs output. Change-Id: I073da8aca29635146fb0d4a2625b2b7564fd8414 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170403 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4854 for details. -gerrit

1 0

Patch merged into coreboot/master: 09d27dd baytrail: add dunit access and registers
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit 09d27ddaa60274e2ef7d81e9e170eadf55d52c1b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Sep 23 14:17:35 2013 -0500 baytrail: add dunit access and registers The dunit on baytrail is the dram unit. Provide a means to access the configuration registers there using the proper IOSF mechanisms. BUG=chrome-os-partner:22875 BRANCH=none TEST=Built and booted. Able to read dram registers. Change-Id: I4d5c019720a7883fe93f3e1860bcd57ce2ea6542 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170490 See http://review.coreboot.org/4853 for details. -gerrit

1 0

Patch merged into coreboot/master: fbbd3ae baytrail: set host memory map
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit fbbd3ae089409d1056d0f31a8401ff047ea039ec Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 24 12:41:08 2013 -0500 baytrail: set host memory map Prior to this commit the coreboot resource allocator was not using proper addresses. That's not surprising there wasn't any code to initialize the resources properly. This commit initializes the memory map accoring to the BUNIT registers. BUG=chrome-os-partner:22860 BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted. Noted output for resource assignments is sane. Change-Id: Ice8d067d8b993736de5c5b273a0f642fa034a024 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170429 See http://review.coreboot.org/4852 for details. -gerrit

1 0

Patch merged into coreboot/master: 37c9fbf baytrail: add common pci_operations
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit 37c9fbfcf8d1cd79d174484549f42bd436bc2454 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 24 12:29:57 2013 -0500 baytrail: add common pci_operations The coreboot device modeling for pci devices wants a pci_operations structure for all devices. This structure just sets the subsystem vendor and device id. Add a common one that all the other pci drivers can use for Bay Trail. BUG=chrome-os-partner:22860 BRANCH=None TEST=Built and booted while utilizing this new structure. Change-Id: I39949cbdb83b3acb93fe4034eb4278d45369e321 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170428 See http://review.coreboot.org/4851 for details. -gerrit

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Patch merged into coreboot/master: add0562 baytrail: initialize graphics before MRC
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit add056269d655226abc4a3ed5787bc31ba16d408 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Sep 24 12:36:14 2013 -0500 baytrail: initialize graphics before MRC The graphics device needs to have its resource contraints initialized before running the reference code. Right now just use a 256MiB aperture, 32MiB of stolen memory data, and 2MiB GTT memory. BUG=chrome-os-partner:22869 BRANCH=None TEST=Built and booted. Noted amount of stolen memory matches configuration as well as BAR size within the graphics device. Change-Id: I328bf858f288363187cf705d6340947393b5ff10 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170427 See http://review.coreboot.org/4850 for details. -gerrit

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Patch merged into coreboot/master: decc857 baytrail: cache ROM space early in bootblock
by gerrit＠coreboot.org 31 Jan '14

31 Jan '14

the following patch was just integrated into master: commit decc857c13047234ee5d44eeae9221ec9edc6eef Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Sep 23 14:15:42 2013 -0500 baytrail: cache ROM space early in bootblock Take advantage of the cache early in bootblock. The intent is to speed up cbfs walking when trying to locate romstage. BUG=chrome-os-partner:22857 BRANCH=None TEST=Built and booted. Change-Id: If03210103c9782390230915db3b4a9759d172dce Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170426 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4849 for details. -gerrit

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coreboot-gerrit January 2014