coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

1 participants
1030 discussions

Patch set updated for coreboot: d33b651 exynos5420: update I2C code, add HSI2C/USI support
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3681 -gerrit commit d33b651eb3a88022bc203c7b674be84acec9e9f4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jun 14 19:16:56 2013 -0700 exynos5420: update I2C code, add HSI2C/USI support This updates the low-level I2C code to handle the new high-speed HSI2C/USI inteface. It also outputs a bit more error information when things go wrong. Also adds some more error prints. Timeouts really need to be noted. In hsi2c_wait_for_irq, order the delay so that we do an initial sleep first to avoid an early-test that was kicking us out of the test too soon. We got to the test before the hardware was ready for us. Finally, test clearing the interrupt status register every time we wait for it on the write. Works. Change-Id: I69500eedad58ae0c6405164fbeee89b6a4c6ec6c Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/i2c.c | 656 ++++++++++++++++++++++++++++++--------- src/cpu/samsung/exynos5420/i2c.h | 39 ++- 2 files changed, 542 insertions(+), 153 deletions(-) diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index 43cc4d2..5ea1eef 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -20,13 +20,14 @@ #include <console/console.h> #include <delay.h> +#include <timer.h> #include <arch/io.h> #include <device/i2c.h> #include "clk.h" #include "i2c.h" #include "pinmux.h" -#define I2C_WRITE 0 +#define I2C_WRITE 0 #define I2C_READ 1 #define I2C_OK 0 @@ -35,6 +36,61 @@ #define I2C_NOK_LA 3 /* Lost arbitration */ #define I2C_NOK_TOUT 4 /* time out */ +/* HSI2C specific register description */ + +/* I2C_CTL Register bits */ +/* FIXME(dhendrix): do we really need to cast these as unsigned? */ +#define HSI2C_FUNC_MODE_I2C (1u << 0) +#define HSI2C_MASTER (1u << 3) +#define HSI2C_RXCHON (1u << 6) /* Write/Send */ +#define HSI2C_TXCHON (1u << 7) /* Read/Receive */ +#define HSI2C_SW_RST (1u << 31) + +/* I2C_FIFO_CTL Register bits */ +#define HSI2C_RXFIFO_EN (1u << 0) +#define HSI2C_TXFIFO_EN (1u << 1) +#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) +#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) + +/* I2C_TRAILING_CTL Register bits */ +#define HSI2C_TRAILING_COUNT (0xff) + +/* I2C_INT_EN Register bits */ +#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0) +#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1) +#define HSI2C_INT_TRAILING_EN (1u << 6) +#define HSI2C_INT_I2C_EN (1u << 9) + +/* I2C_CONF Register bits */ +#define HSI2C_AUTO_MODE (1u << 31) +#define HSI2C_10BIT_ADDR_MODE (1u << 30) +#define HSI2C_HS_MODE (1u << 29) + +/* I2C_AUTO_CONF Register bits */ +#define HSI2C_READ_WRITE (1u << 16) +#define HSI2C_STOP_AFTER_TRANS (1u << 17) +#define HSI2C_MASTER_RUN (1u << 31) + +/* I2C_TIMEOUT Register bits */ +#define HSI2C_TIMEOUT_EN (1u << 31) + +/* I2C_TRANS_STATUS register bits */ +#define HSI2C_MASTER_BUSY (1u << 17) +#define HSI2C_SLAVE_BUSY (1u << 16) +#define HSI2C_NO_DEV (1u << 3) +#define HSI2C_NO_DEV_ACK (1u << 2) +#define HSI2C_TRANS_ABORT (1u << 1) +#define HSI2C_TRANS_DONE (1u << 0) +#define HSI2C_TIMEOUT_AUTO (0u << 0) + +#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) + +/* Controller operating frequency, timing values for operation + * are calculated against this frequency + */ +#define HSI2C_FS_TX_CLOCK 1000000 + +/* S3C I2C Controller bits */ #define I2CSTAT_BSY 0x20 /* Busy bit */ #define I2CSTAT_NACK 0x01 /* Nack bit */ #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ @@ -44,6 +100,10 @@ #define I2C_START_STOP 0x20 /* START / STOP */ #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ +#define I2C_TIMEOUT_MS 1000 /* 1 second */ + +#define HSI2C_TIMEOUT 100 + /* The timeouts we live by */ enum { I2C_XFER_TIMEOUT_MS = 35, /* xfer to complete */ @@ -73,56 +133,118 @@ static struct s3c24x0_i2c_bus i2c_buses[] = { .regs = (struct s3c24x0_i2c *)0x12c90000, .periph_id = PERIPH_ID_I2C3, }, + /* I2C4-I2C10 are part of the USI block */ { .bus_num = 4, - .regs = (struct s3c24x0_i2c *)0x12ca0000, + .hsregs = (struct exynos5_hsi2c *)0x12ca0000, .periph_id = PERIPH_ID_I2C4, + .is_highspeed = 1, }, { .bus_num = 5, - .regs = (struct s3c24x0_i2c *)0x12cb0000, + .hsregs = (struct exynos5_hsi2c *)0x12cb0000, .periph_id = PERIPH_ID_I2C5, + .is_highspeed = 1, }, { .bus_num = 6, - .regs = (struct s3c24x0_i2c *)0x12cc0000, + .hsregs = (struct exynos5_hsi2c *)0x12cc0000, .periph_id = PERIPH_ID_I2C6, + .is_highspeed = 1, }, { .bus_num = 7, - .regs = (struct s3c24x0_i2c *)0x12cd0000, + .hsregs = (struct exynos5_hsi2c *)0x12cd0000, .periph_id = PERIPH_ID_I2C7, + .is_highspeed = 1, + }, + { + .bus_num = 8, + .hsregs = (struct exynos5_hsi2c *)0x12e00000, + .periph_id = PERIPH_ID_I2C8, + .is_highspeed = 1, + }, + { + .bus_num = 9, + .hsregs = (struct exynos5_hsi2c *)0x12e10000, + .periph_id = PERIPH_ID_I2C9, + .is_highspeed = 1, + }, + { + .bus_num = 10, + .hsregs = (struct exynos5_hsi2c *)0x12e20000, + .periph_id = PERIPH_ID_I2C10, + .is_highspeed = 1, }, }; +/* + * Wait til the byte transfer is completed. + * + * @param i2c- pointer to the appropriate i2c register bank. + * @return I2C_OK, if transmission was ACKED + * I2C_NACK, if transmission was NACKED + * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS + */ + static int WaitForXfer(struct s3c24x0_i2c *i2c) { - int i; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, I2C_TIMEOUT_MS * 1000); + do { + if (read32(&i2c->iiccon) & I2CCON_IRPND) + return (read32(&i2c->iicstat) & I2CSTAT_NACK) ? + I2C_NACK : I2C_OK; + timer_monotonic_get(&current); + } while (mono_time_before(&current, &end)); + + printk(BIOS_ERR, "%s timed out\n", __func__); + return I2C_NOK_TOUT; +} - i = I2C_XFER_TIMEOUT_MS * 20; - while (!(readl(&i2c->iiccon) & I2CCON_IRPND)) { - if (i == 0) { - printk(BIOS_ERR, "%s: i2c xfer timeout\n", __func__); - return I2C_NOK_TOUT; +static int hsi2c_wait_for_irq(struct exynos5_hsi2c *i2c) +{ + struct mono_time current, end; + int ret = I2C_NOK_TOUT; + + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000 * 10); + + while (mono_time_before(&current, &end)) { + udelay(20); + if (read32(&i2c->usi_int_stat) & + (HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN)) { + ret = I2C_OK; + break; } - udelay(50); - i--; + /* wait for a while and retry */ + timer_monotonic_get(&current); } - return I2C_OK; + if (ret == I2C_NOK_TOUT) + printk(BIOS_ERR, "%s timed out\n", __func__); + return ret; } -static int IsACK(struct s3c24x0_i2c *i2c) +static int hsi2c_isack(struct exynos5_hsi2c *i2c) { - return !(readl(&i2c->iicstat) & I2CSTAT_NACK); + return read32(&i2c->usi_trans_status) & + (HSI2C_NO_DEV | HSI2C_NO_DEV_ACK); } static void ReadWriteByte(struct s3c24x0_i2c *i2c) { - uint32_t x; + writel(read32(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); +} - x = readl(&i2c->iiccon); - writel(x & ~I2CCON_IRPND, &i2c->iiccon); +static void hsi2c_clear_irqpd(struct exynos5_hsi2c *i2c) +{ + u32 stat = read32(&i2c->usi_int_stat); + write32(stat, &i2c->usi_int_stat); } static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) @@ -137,74 +259,130 @@ static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) pres = 512; div = 0; - while ((freq / pres / (div + 1)) > speed) div++; /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ val = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); - writel(val, &bus->regs->iiccon); + write32(val, &bus->regs->iiccon); /* init to SLAVE RECEIVE mode and clear I2CADDn */ - writel(0, &bus->regs->iicstat); - writel(slaveadd, &bus->regs->iicadd); + write32(0, &bus->regs->iicstat); + write32(slaveadd, &bus->regs->iicadd); /* program Master Transmit (and implicit STOP) */ - writel(I2C_MODE_MT | I2C_TXRX_ENA, &bus->regs->iicstat); + write32(I2C_MODE_MT | I2C_TXRX_ENA, &bus->regs->iicstat); } -/* - * MULTI BUS I2C support - */ -static void i2c_bus_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) +static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) { - i2c_ch_init(bus, speed, slaveadd); + struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; + unsigned long clkin = clock_get_periph_rate(i2c_bus->periph_id); + unsigned int op_clk = HSI2C_FS_TX_CLOCK; + unsigned int i = 0, utemp0 = 0, utemp1 = 0; + unsigned int t_ftl_cycle; + + /* FPCLK / FI2C = + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE + * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + * uTemp1 = (TSCLK_L + TSCLK_H + 2) + * uTemp2 = TSCLK_L + TSCLK_H + */ + t_ftl_cycle = (read32(&hsregs->usi_conf) >> 16) & 0x7; + utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; + + /* CLK_DIV max is 256 */ + for (i = 0; i < 256; i++) { + utemp1 = utemp0 / (i + 1); + if ((utemp1 < 512) && (utemp1 > 4)) { + i2c_bus->clk_cycle = utemp1 - 2; + i2c_bus->clk_div = i; + return 0; + } + } + printk(BIOS_ERR, "%s: failed?\n", __func__); + return -1; } -/* - * Verify the whether I2C ACK was received or not - * - * @param i2c pointer to I2C register base - * @param buf array of data - * @param len length of data - * return I2C_OK when transmission done - * I2C_NACK otherwise - */ -static int i2c_send_verify(struct s3c24x0_i2c *i2c, unsigned char buf[], - unsigned char len) +static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) { - int i, result = I2C_OK; + struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; + unsigned int t_sr_release; + unsigned int n_clkdiv; + unsigned int t_start_su, t_start_hd; + unsigned int t_stop_su; + unsigned int t_data_su, t_data_hd; + unsigned int t_scl_l, t_scl_h; + u32 i2c_timing_s1; + u32 i2c_timing_s2; + u32 i2c_timing_s3; + u32 i2c_timing_sla; + + hsi2c_get_clk_details(i2c_bus); + + n_clkdiv = i2c_bus->clk_div; + t_scl_l = i2c_bus->clk_cycle / 2; + t_scl_h = i2c_bus->clk_cycle / 2; + t_start_su = t_scl_l; + t_start_hd = t_scl_l; + t_stop_su = t_scl_l; + t_data_su = t_scl_l / 2; + t_data_hd = t_scl_l / 2; + t_sr_release = i2c_bus->clk_cycle; + + i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; + i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; + i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; + i2c_timing_sla = t_data_hd << 0; + + write32(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); + + /* Clear to enable Timeout */ + clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); + + write32(read32(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); + + /* Currently operating in Fast speed mode. */ + write32(i2c_timing_s1, &hsregs->usi_timing_fs1); + write32(i2c_timing_s2, &hsregs->usi_timing_fs2); + write32(i2c_timing_s3, &hsregs->usi_timing_fs3); + write32(i2c_timing_sla, &hsregs->usi_timing_sla); +} - if (IsACK(i2c)) { - for (i = 0; (i < len) && (result == I2C_OK); i++) { - writel(buf[i], &i2c->iicds); - ReadWriteByte(i2c); - result = WaitForXfer(i2c); - if (result == I2C_OK && !IsACK(i2c)) - result = I2C_NACK; - } - } else { - result = I2C_NACK; - } +/* SW reset for the high speed bus */ +static void i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) +{ + struct exynos5_hsi2c *i2c = i2c_bus->hsregs; + u32 i2c_ctl; - return result; + /* Set and clear the bit for reset */ + i2c_ctl = read32(&i2c->usi_ctl); + i2c_ctl |= HSI2C_SW_RST; + write32(i2c_ctl, &i2c->usi_ctl); + + i2c_ctl = read32(&i2c->usi_ctl); + i2c_ctl &= ~HSI2C_SW_RST; + write32(i2c_ctl, &i2c->usi_ctl); + + /* Initialize the configure registers */ + hsi2c_ch_init(i2c_bus); } void i2c_init(unsigned bus_num, int speed, int slaveadd) { struct s3c24x0_i2c_bus *i2c; - int i; i2c = &i2c_buses[bus_num]; - i2c_bus_init(i2c, speed, slaveadd); - /* wait for some time to give previous transfer a chance to finish */ - i = I2C_INIT_TIMEOUT_MS * 20; - while ((readl(&i2c->regs->iicstat) & I2CSTAT_BSY) && (i > 0)) { - udelay(50); - i--; - } + i2c_reset(i2c); - i2c_ch_init(i2c, speed, slaveadd); + /* FIXME(dhendrix): hsi2c_ch_init doesn't take a speed or slaveadd + * parameter, so we should split it out and call it directly from + * romstage without the unneeded parameters. + */ + if (i2c->is_highspeed) + hsi2c_ch_init(i2c); + else + i2c_ch_init(i2c, speed, slaveadd); } /* @@ -213,22 +391,179 @@ void i2c_init(unsigned bus_num, int speed, int slaveadd) * @param mode If it is a master transmitter or receiver * @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise */ -static int i2c_send_stop(struct s3c24x0_i2c *i2c, int mode) +static int hsi2c_send_stop(struct exynos5_hsi2c *i2c, int result) { - int timeout; - + int ret = I2C_NOK_TOUT; + struct mono_time current, end; + + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000); + while (mono_time_before(&current, &end)) { + if (!(read32(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY)) { + ret = I2C_OK; + break; + } + udelay(5); + timer_monotonic_get(&current); + } + if (ret) + printk(BIOS_ERR, "%s timed out\n", __func__); /* Setting the STOP event to fire */ - writel(mode | I2C_TXRX_ENA, &i2c->iicstat); - ReadWriteByte(i2c); + write32(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); + write32(0x0, &i2c->usi_int_en); - /* Wait for the STOP to send and the bus to go idle */ - for (timeout = I2C_STOP_TIMEOUT_US; timeout > 0; timeout -= 5) { - if (!(readl(&i2c->iicstat) & I2CSTAT_BSY)) - return I2C_OK; - udelay(5); + return (result == I2C_OK) ? ret : result; +} + +static int hsi2c_write(struct exynos5_hsi2c *i2c, + unsigned char chip, + unsigned char addr[], + unsigned char alen, + unsigned char data[], + unsigned short len) +{ + int i = 0, result = I2C_OK; + u32 i2c_auto_conf; + u32 stat; + struct mono_time current, end; + + /* Check I2C bus idle */ + i = HSI2C_TIMEOUT * 20; + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000 * 20); + while (mono_time_before(&current, &end)) { + if (!(read32(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY)) + break; + udelay(50); + timer_monotonic_get(&current); } - return I2C_NOK_TOUT; + stat = read32(&i2c->usi_trans_status); + + if (stat & HSI2C_MASTER_BUSY) { + printk(BIOS_ERR, "%s: bus busy, timing out\n", __func__); + return I2C_NOK_TOUT; + } + /* Disable TXFIFO and RXFIFO */ + write32(0, &i2c->usi_fifo_ctl); + + /* chip address */ + write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); + + /* Enable interrupts */ + write32((HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN), + &i2c->usi_int_en); + + /* usi_ctl enable i2c func, master write configure */ + write32((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); + + /* i2c_conf configure */ + write32(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + + /* auto_conf for write length and stop configure */ + i2c_auto_conf = ((len + alen) | HSI2C_STOP_AFTER_TRANS); + i2c_auto_conf &= ~HSI2C_READ_WRITE; + write32(i2c_auto_conf, &i2c->usi_auto_conf); + + /* Master run, start xfer */ + write32(read32(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN, + &i2c->usi_auto_conf); + + result = hsi2c_wait_for_irq(i2c); + if ((result == I2C_OK) && hsi2c_isack(i2c)) { + printk(BIOS_ERR, "%s: NAK from device %04x\n", __func__, + HSI2C_SLV_ADDR_MAS(chip)); + result = I2C_NACK; + goto out; + } + + for (i = 0; i < alen && (result == I2C_OK); i++) { + write32(addr[i], &i2c->usi_txdata); + result = hsi2c_wait_for_irq(i2c); + hsi2c_clear_irqpd(i2c); + if (result) + printk(BIOS_ERR, "%s: timeout on sending address\n", + __func__); + } + + for (i = 0; i < len && (result == I2C_OK); i++) { + write32(data[i], &i2c->usi_txdata); + result = hsi2c_wait_for_irq(i2c); + hsi2c_clear_irqpd(i2c); + if (result) + printk(BIOS_ERR, "%s: timeout on sending data\n", + __func__); + } +out: + hsi2c_clear_irqpd(i2c); + return hsi2c_send_stop(i2c, result); +} + +static int hsi2c_read(struct exynos5_hsi2c *i2c, + unsigned char chip, + unsigned char addr[], + unsigned char alen, + unsigned char data[], + unsigned short len, + int check) +{ + int i, result; + u32 i2c_auto_conf; + + if (!check) { + result = hsi2c_write(i2c, chip, addr, alen, data, 0); + if (result != I2C_OK) { + printk(BIOS_ERR, "write failed Result: %d\n", result); + return result; + } + } + + /* start read */ + /* Disable TXFIFO and RXFIFO */ + write32(0, &i2c->usi_fifo_ctl); + + /* chip address */ + write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); + + /* Enable interrupts */ + write32(HSI2C_INT_I2C_EN, &i2c->usi_int_en); + + /* i2c_conf configure */ + write32(read32(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + + /* auto_conf, length and stop configure */ + i2c_auto_conf = (len | HSI2C_STOP_AFTER_TRANS | HSI2C_READ_WRITE); + write32(i2c_auto_conf, &i2c->usi_auto_conf); + + /* usi_ctl enable i2c func, master WRITE configure */ + write32((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); + + /* Master run, start xfer */ + write32(readl(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN, + &i2c->usi_auto_conf); + + result = hsi2c_wait_for_irq(i2c); + if ((result == I2C_OK) && hsi2c_isack(i2c)) { + result = I2C_NACK; + goto out; + } + + for (i = 0; i < len && (result == I2C_OK); i++) { + result = hsi2c_wait_for_irq(i2c); + data[i] = read32(&i2c->usi_rxdata); + udelay(100); + } + /*for(i = 0; i < len; i++) + printk(BIOS_SPEW, " %02x", data[i]); + printk(BIOS_SPEW, "\n");*/ +out: + /* Stop and quit */ + hsi2c_clear_irqpd(i2c); + return hsi2c_send_stop(i2c, result); } /* @@ -246,105 +581,105 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, unsigned char data[], unsigned short data_len) { - int i, result, stop_bit_result; - uint32_t x; + int i = 0, result; + struct mono_time current, end; if (data == 0 || data_len == 0) { - /* Don't support data transfer of no length or to address 0 */ printk(BIOS_ERR, "i2c_transfer: bad call\n"); return I2C_NOK; } - /* Check I2C bus idle */ - i = I2C_IDLE_TIMEOUT_MS * 20; - while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { - udelay(50); - i--; + timer_monotonic_get(&current); + end = current; + mono_time_add_usecs(&end, I2C_TIMEOUT_MS * 1000); + while (readl(&i2c->iicstat) & I2CSTAT_BSY) { + if (!mono_time_before(&current, &end)){ + printk(BIOS_ERR, "%s timed out\n", __func__); + return I2C_NOK_TOUT; + } + timer_monotonic_get(&current); } - if (readl(&i2c->iicstat) & I2CSTAT_BSY) { - printk(BIOS_ERR, "%s: bus busy\n", __func__); - return I2C_NOK_TOUT; - } + write32(read32(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); + + /* Get the slave chip address going */ + write32(chip, &i2c->iicds); + if ((cmd_type == I2C_WRITE) || (addr && addr_len)) + write32(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); + else + write32(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); - x = readl(&i2c->iiccon); - writel(x | I2CCON_ACKGEN, &i2c->iiccon); + /* Wait for chip address to transmit. */ + result = WaitForXfer(i2c); + if (result != I2C_OK) + goto bailout; + /* If register address needs to be transmitted - do it now. */ if (addr && addr_len) { - writel(chip, &i2c->iicds); - /* send START */ - writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); - if (WaitForXfer(i2c) == I2C_OK) - result = i2c_send_verify(i2c, addr, addr_len); - else - result = I2C_NACK; - } else - result = I2C_NACK; + while ((i < addr_len) && (result == I2C_OK)) { + write32(addr[i++], &i2c->iicds); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); + } + i = 0; + if (result != I2C_OK) + goto bailout; + } switch (cmd_type) { case I2C_WRITE: - if (result == I2C_OK) - result = i2c_send_verify(i2c, data, data_len); - else { - writel(chip, &i2c->iicds); - /* send START */ - writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, - &i2c->iicstat); - if (WaitForXfer(i2c) == I2C_OK) - result = i2c_send_verify(i2c, data, data_len); - } - - if (result == I2C_OK) + while ((i < data_len) && (result == I2C_OK)) { + write32(data[i++], &i2c->iicds); + ReadWriteByte(i2c); result = WaitForXfer(i2c); - - stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MT); + } break; case I2C_READ: - { - int was_ok = (result == I2C_OK); - - writel(chip, &i2c->iicds); - /* resend START */ - writel(I2C_MODE_MR | I2C_TXRX_ENA | - I2C_START_STOP, &i2c->iicstat); - ReadWriteByte(i2c); - result = WaitForXfer(i2c); - - if (was_ok || IsACK(i2c)) { - i = 0; - while ((i < data_len) && (result == I2C_OK)) { - /* disable ACK for final READ */ - if (i == data_len - 1) { - x = readl(&i2c->iiccon) & ~I2CCON_ACKGEN; - writel(x, &i2c->iiccon); - } - ReadWriteByte(i2c); - result = WaitForXfer(i2c); - data[i] = readl(&i2c->iicds); - i++; - } - } else { - result = I2C_NACK; + if (addr && addr_len) { + /* + * Register address has been sent, now send slave chip + * address again to start the actual read transaction. + */ + write32(chip, &i2c->iicds); + + /* Generate a re-START. */ + write32(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); + if (result != I2C_OK) + goto bailout; } - stop_bit_result = i2c_send_stop(i2c, I2C_MODE_MR); + while ((i < data_len) && (result == I2C_OK)) { + /* disable ACK for final READ */ + if (i == data_len - 1) + write32(readl(&i2c->iiccon) + & ~I2CCON_ACKGEN, + &i2c->iiccon); + ReadWriteByte(i2c); + result = WaitForXfer(i2c); + data[i++] = read32(&i2c->iicds); + } + if (result == I2C_NACK) + result = I2C_OK; /* Normal terminated read. */ break; - } default: printk(BIOS_ERR, "i2c_transfer: bad call\n"); - result = stop_bit_result = I2C_NOK; + result = I2C_NOK; break; } - /* - * If the transmission went fine, then only the stop bit was left to - * fail. Otherwise, the real failure we're interested in came before - * that, during the actual transmission. - */ - return (result == I2C_OK) ? stop_bit_result : result; +bailout: + /* Send STOP. */ + write32(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); + ReadWriteByte(i2c); + + return result; } int i2c_read(unsigned bus, unsigned chip, unsigned addr, @@ -367,10 +702,16 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr, } i2c = &i2c_buses[bus]; - ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, &xaddr[4 - alen], - alen, buf, len); + if (i2c->is_highspeed) + ret = hsi2c_read(i2c->hsregs, chip, &xaddr[4 - alen], + alen, buf, len, 0); + else + ret = i2c_transfer(i2c->regs, I2C_READ, chip << 1, + &xaddr[4 - alen], alen, buf, len); if (ret) { - printk(BIOS_ERR, "I2c read: failed %d\n", ret); + i2c_reset(i2c); + printk(BIOS_ERR, "I2C read (bus %02x, chip addr %02x) failed: " + "%d\n", bus, chip, ret); return 1; } return 0; @@ -397,8 +738,19 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr, } i2c = &i2c_buses[bus]; - ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, &xaddr[4 - alen], - alen, buf, len); - - return ret != 0; + if (i2c->is_highspeed) + ret = hsi2c_write(i2c->hsregs, chip, &xaddr[4 - alen], + alen, buf, len); + else + ret = i2c_transfer(i2c->regs, I2C_WRITE, chip << 1, + &xaddr[4 - alen], alen, buf, len); + + + if (ret != 0) { + i2c_reset(i2c); + printk(BIOS_ERR, "I2C write (bus %02x, chip addr %02x) failed: " + "%d\n", bus, chip, ret); + return 1; + } + return 0; } diff --git a/src/cpu/samsung/exynos5420/i2c.h b/src/cpu/samsung/exynos5420/i2c.h index b14aa79..e8fe820 100644 --- a/src/cpu/samsung/exynos5420/i2c.h +++ b/src/cpu/samsung/exynos5420/i2c.h @@ -28,12 +28,49 @@ struct s3c24x0_i2c { u32 iicadd; u32 iicds; u32 iiclc; -}; +} __attribute__ ((packed)); + +struct exynos5_hsi2c { + u32 usi_ctl; + u32 usi_fifo_ctl; + u32 usi_trailing_ctl; + u32 usi_clk_ctl; + u32 usi_clk_slot; + u32 spi_ctl; + u32 uart_ctl; + u32 res1; + u32 usi_int_en; + u32 usi_int_stat; + u32 usi_modem_stat; + u32 usi_error_stat; + u32 usi_fifo_stat; + u32 usi_txdata; + u32 usi_rxdata; + u32 res2; + u32 usi_conf; + u32 usi_auto_conf; + u32 usi_timeout; + u32 usi_manual_cmd; + u32 usi_trans_status; + u32 usi_timing_hs1; + u32 usi_timing_hs2; + u32 usi_timing_hs3; + u32 usi_timing_fs1; + u32 usi_timing_fs2; + u32 usi_timing_fs3; + u32 usi_timing_sla; + u32 i2c_addr; +} __attribute__ ((packed)); struct s3c24x0_i2c_bus { int bus_num; struct s3c24x0_i2c *regs; enum periph_id periph_id; + struct exynos5_hsi2c *hsregs; + int is_highspeed; /* High speed type, rather than I2C */ + int id; + unsigned clk_cycle; + unsigned clk_div; }; void i2c_init(unsigned bus, int speed, int slaveadd);

1 0

Patch set updated for coreboot: 72d019d pit: set up the PMIC correctly
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3680 -gerrit commit 72d019dc5e4e8d7d3a6268ec05149e05024e6cef Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jun 14 16:08:05 2013 -0700 pit: set up the PMIC correctly This updates the setup_power() function to actually set up the PMIC which is on this board (the MAX77802). Change-Id: I9c6f21f183dacc0bca71277e681e670834412d78 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/exynos5420.h | 1 + src/mainboard/google/pit/romstage.c | 92 ++++++++++++++++++++--------------- 2 files changed, 54 insertions(+), 39 deletions(-) diff --git a/src/mainboard/google/pit/exynos5420.h b/src/mainboard/google/pit/exynos5420.h index 98d36f9..562d9bc 100644 --- a/src/mainboard/google/pit/exynos5420.h +++ b/src/mainboard/google/pit/exynos5420.h @@ -19,6 +19,7 @@ /* I2C */ #define I2C_0_SPEED 100000 +#define I2C_4_SPEED 100000 #define I2C_SLAVE 0 /* Voltages */ diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 1ff8d51..001d8cf 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,6 +18,7 @@ */ #include <types.h> +#include <stdlib.h> #include <armv7.h> #include <cbfs.h> @@ -35,60 +36,73 @@ #include <console/console.h> #include <arch/stages.h> -#include <drivers/maxim/max77686/max77686.h> +#include <drivers/maxim/max77802/max77802.h> #include <device/i2c.h> #include "exynos5420.h" -#define PMIC_BUS 0 #define MMC0_GPIO_PIN (58) +struct pmic_write +{ + int or_orig; // Whether to or in the original value. + uint8_t reg; // Register to write. + uint8_t val; // Value to write. +}; + +/* + * Use read-modify-write for MAX77802 control registers and clobber the + * output voltage setting (BUCK?DVS?) registers. + */ +struct pmic_write pmic_writes[] = +{ + { 1, MAX77802_REG_PMIC_32KHZ, MAX77802_32KHCP_EN }, + { 0, MAX77802_REG_PMIC_BUCK1DVS1, MAX77802_BUCK1DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK1CTRL, MAX77802_BUCK_TYPE1_ON | + MAX77802_BUCK_TYPE1_IGNORE_PWRREQ }, + { 0, MAX77802_REG_PMIC_BUCK2DVS1, MAX77802_BUCK2DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK2CTRL1, MAX77802_BUCK_TYPE2_ON | + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + { 0, MAX77802_REG_PMIC_BUCK3DVS1, MAX77802_BUCK3DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK3CTRL1, MAX77802_BUCK_TYPE2_ON | + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + { 0, MAX77802_REG_PMIC_BUCK4DVS1, MAX77802_BUCK4DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK4CTRL1, MAX77802_BUCK_TYPE2_ON | + MAX77802_BUCK_TYPE2_IGNORE_PWRREQ }, + { 0, MAX77802_REG_PMIC_BUCK6DVS1, MAX77802_BUCK6DVS1_1V }, + { 1, MAX77802_REG_PMIC_BUCK6CTRL, MAX77802_BUCK_TYPE1_ON | + MAX77802_BUCK_TYPE1_IGNORE_PWRREQ } +}; + static void setup_power(void) { int error = 0; + int i; power_init(); /* Initialize I2C bus to configure PMIC. */ - exynos_pinmux_i2c0(); - i2c_init(0, I2C_0_SPEED, 0x00); + exynos_pinmux_i2c4(); + i2c_init(4, I2C_4_SPEED, 0x00); printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__); - /* - * We're using CR1616 coin cell battery that is non-rechargeable - * battery. But, BBCHOSTEN bit of the BBAT Charger Register in - * MAX77686 is enabled by default for charging coin cell. - * - * Also, we cannot meet the coin cell reverse current spec. in UL - * standard if BBCHOSTEN bit is enabled. - * - * Disable Coin BATT Charging - */ - error = max77686_disable_backup_batt(PMIC_BUS); - - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, VDD_INT_UV, - REG_ENABLE, MAX77686_UV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV, - REG_ENABLE, MAX77686_MV); - error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV, - REG_ENABLE, MAX77686_MV); - - error |= max77686_enable_32khz_cp(PMIC_BUS); - - if (error) { - printk(BIOS_CRIT, "%s: PMIC error: %#x\n", __func__, error); - die("Failed to intialize PMIC.\n"); + + for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { + uint8_t data = 0; + uint8_t reg = pmic_writes[i].reg; + + if (pmic_writes[i].or_orig) + error |= i2c_read(4, MAX77802_I2C_ADDR, + reg, sizeof(reg), + &data, sizeof(data)); + data |= pmic_writes[i].val; + error |= i2c_write(4, MAX77802_I2C_ADDR, + reg, sizeof(reg), + &data, sizeof(data)); } + + if (error) + die("Failed to intialize PMIC.\n"); } static void setup_storage(void)

1 0

Patch set updated for coreboot: e74e31f Samsung CPUs: Unify Kconfig
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3683 -gerrit commit e74e31f05dff7d98c1a7df3bfaec2529c58136a3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 12:02:47 2013 -0700 Samsung CPUs: Unify Kconfig For all other CPUs, we unconditionally include the CPU Kconfig files in the CPU directory, not in the vendor directory. Do the same thing for the Exynos CPUs. This allows us to make CPU dependent changes in the directory of that CPU alone. Also, drop some unused Kconfig variables from the Exynos Kconfig files. Change-Id: I4e4c22a0693988834e619dd33d121bf994ed57e8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/Kconfig | 22 ---------------------- src/cpu/samsung/exynos5250/Kconfig | 27 ++++++++++++--------------- src/cpu/samsung/exynos5420/Kconfig | 20 +++++++++++--------- 3 files changed, 23 insertions(+), 46 deletions(-) diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 54f4ed1..ae37403 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -1,24 +1,2 @@ -config CPU_SAMSUNG_EXYNOS5250 - depends on ARCH_ARMV7 - select HAVE_MONOTONIC_TIMER - select HAVE_UART_SPECIAL - select DEFAULT_BOOTBLOCK_CONSOLE - select DEFAULT_EARLY_CONSOLE - bool - default n - -config CPU_SAMSUNG_EXYNOS5420 - depends on ARCH_ARMV7 - select HAVE_MONOTONIC_TIMER - select HAVE_UART_SPECIAL - select DEFAULT_EARLY_CONSOLE - bool - default n - -if CPU_SAMSUNG_EXYNOS5250 source src/cpu/samsung/exynos5250/Kconfig -endif - -if CPU_SAMSUNG_EXYNOS5420 source src/cpu/samsung/exynos5420/Kconfig -endif diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 75d1178..d6c3f1e 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,3 +1,14 @@ +config CPU_SAMSUNG_EXYNOS5250 + depends on ARCH_ARMV7 + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select DEFAULT_BOOTBLOCK_CONSOLE + select DEFAULT_EARLY_CONSOLE + bool + default n + +if CPU_SAMSUNG_EXYNOS5250 + config BOOTBLOCK_CPU_INIT string default "cpu/samsung/exynos5250/bootblock.c" @@ -6,10 +17,6 @@ config BOOTBLOCK_CPU_INIT bootblock must load microcode or copy data from ROM before searching for the bootblock. -config EXYNOS_ACE_SHA - bool - default n - # ROM image layout. # # 0x0000: vendor-provided BL1 (8k). @@ -77,17 +84,6 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x000017000 -# FIXME: This is for copying SPI content into SRAM temporarily and -# will be removed when we have the SPI streaming driver implemented. -config SPI_IMAGE_HACK - hex - default 0x02060000 - -# FIXME: other magic numbers that should probably go away -config XIP_ROM_SIZE - hex - default ROMSTAGE_SIZE - config SYS_SDRAM_BASE hex default 0x40000000 @@ -137,3 +133,4 @@ config CONSOLE_SERIAL_UART_ADDRESS help Map the UART names to the respective MMIO address. +endif diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 406ffd2..efa0b21 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -1,3 +1,13 @@ +config CPU_SAMSUNG_EXYNOS5420 + depends on ARCH_ARMV7 + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select DEFAULT_EARLY_CONSOLE + bool + default n + +if CPU_SAMSUNG_EXYNOS5420 + config BOOTBLOCK_CPU_INIT string default "cpu/samsung/exynos5420/bootblock.c" @@ -6,10 +16,6 @@ config BOOTBLOCK_CPU_INIT bootblock must load microcode or copy data from ROM before searching for the bootblock. -config EXYNOS_ACE_SHA - bool - default n - # ROM image layout. # # 0x0000: vendor-provided BL1 (8k). @@ -79,11 +85,6 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x000013000 -# FIXME: other magic numbers that should probably go away -config XIP_ROM_SIZE - hex - default ROMSTAGE_SIZE - config SYS_SDRAM_BASE hex default 0x20000000 @@ -133,3 +134,4 @@ config CONSOLE_SERIAL_UART_ADDRESS help Map the UART names to the respective MMIO address. +endif

1 0

Patch set updated for coreboot: dfc364d arm: Fix memory barrier usage in IO operation
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3682 -gerrit commit dfc364d693d98434d8b6599ca8539a9885118d8f Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 12 15:01:56 2013 -0700 arm: Fix memory barrier usage in IO operation The dmb should be executed before reading operations, and before/after writing operations. Change-Id: I572136a2f9a07eb2c38a112f5deeb2de0c0fd46c Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/include/arch/io.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index b4932dc..be1da51 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -29,41 +29,41 @@ static inline uint8_t read8(const void *addr) { - uint8_t v = *(volatile uint8_t *)addr; dmb(); - return v; + return *(volatile uint8_t *)addr; } static inline uint16_t read16(const void *addr) { - uint16_t v = *(volatile uint16_t *)addr; dmb(); - return v; + return *(volatile uint16_t *)addr; } static inline uint32_t read32(const void *addr) { - uint32_t v = *(volatile uint32_t *)addr; dmb(); - return v; + return *(volatile uint32_t *)addr; } static inline void write8(uint8_t val, const void *addr) { dmb(); *(volatile uint8_t *)addr = val; + dmb(); } static inline void write16(uint16_t val, const void *addr) { dmb(); *(volatile uint16_t *)addr = val; + dmb(); } static inline void write32(uint32_t val, const void *addr) { dmb(); *(volatile uint32_t *)addr = val; + dmb(); } /*

1 0

Patch set updated for coreboot: 003ed03 Exynos5420: add code to make sure resume will work on DRAM.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3693 -gerrit commit 003ed036741df920f274e3b2fb5c81927c96a679 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Wed Jun 19 15:46:25 2013 -0700 Exynos5420: add code to make sure resume will work on DRAM. Found during a perusal of u-boot changes. It looks important. For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commi… Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/bootblock.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/cpu/samsung/exynos5420/bootblock.c b/src/cpu/samsung/exynos5420/bootblock.c index d3d737e..5cc9ef6 100644 --- a/src/cpu/samsung/exynos5420/bootblock.c +++ b/src/cpu/samsung/exynos5420/bootblock.c @@ -19,10 +19,28 @@ #include "clk.h" #include "wakeup.h" +#include "cpu.h" void bootblock_cpu_init(void); void bootblock_cpu_init(void) { + u32 ret; + /* + * During Suspend-Resume & S/W-Reset, as soon as PMU releases + * pad retention, CKE goes high. This causes memory contents + * not to be retained during DRAM initialization. Therfore, + * there is a new control register(0x100431e8[28]) which lets us + * release pad retention and retain the memory content until the + * initialization is complete. + */ + if (read32(((void *)INF_REG_BASE + INF_REG1_OFFSET)) == S5P_CHECK_SLEEP) { + write32(PAD_RETENTION_DRAM_COREBLK_VAL, + (void *)PAD_RETENTION_DRAM_COREBLK_OPTION); + do { + ret = read32((void *)PAD_RETENTION_DRAM_STATUS); + } while (ret != 0x1); + } + /* kick off the multi-core timer. * We want to do this as early as we can. */

1 0

Patch set updated for coreboot: f6a0d9b ARMv7: Drop duplicate call to bootblock_cpu_init()
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3692 -gerrit commit f6a0d9b4fea6eec9aa6a76077740884976649232 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 12 17:07:05 2013 -0700 ARMv7: Drop duplicate call to bootblock_cpu_init() This is already called in ARMv7 bootblock_simple.c so we don't want to do it twice Change-Id: I80cb41035b8a77787e04f2ea58a1cd372cea97d8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/include/bootblock_common.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/arch/armv7/include/bootblock_common.h b/src/arch/armv7/include/bootblock_common.h index 39af453..2fa705f 100644 --- a/src/arch/armv7/include/bootblock_common.h +++ b/src/arch/armv7/include/bootblock_common.h @@ -7,8 +7,5 @@ #else static void bootblock_mainboard_init(void) { -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif } #endif

1 0

Patch set updated for coreboot: 7d366ca Exynos: Only compile UART in if serial console is selected
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3695 -gerrit commit 7d366ca4279feb6683484cd68eb1fede956fcc92 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 15:51:04 2013 -0700 Exynos: Only compile UART in if serial console is selected Change-Id: I5cddffc2e524aae7a31a8f94f67e03a5b7e15c82 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5250/Makefile.inc | 4 ++++ src/cpu/samsung/exynos5420/Makefile.inc | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 663f532..e4e373c 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,7 +9,9 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +endif bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pwm.c @@ -24,7 +26,9 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +endif romstage-y += wakeup.c romstage-y += pwm.c # needed by timer.c romstage-y += gpio.c diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 1dddd21..6f9b91b 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -9,7 +9,9 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +endif bootblock-y += wakeup.c bootblock-y += gpio.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pwm.c @@ -24,7 +26,9 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c +endif romstage-y += wakeup.c romstage-y += pwm.c # needed by timer.c romstage-y += gpio.c

1 0

Patch set updated for coreboot: 608fc3e Don't try to use CBMEM console in bootblock
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3694 -gerrit commit 608fc3eb2a2dee63346ef64a298e4ef014139ead Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 15:44:36 2013 -0700 Don't try to use CBMEM console in bootblock Otherwise we have to worry about hand off between bootblock and romstage. Too much complexity Change-Id: I89bf8a229dba7e1330accadf9a732d831ebc4827 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/early_console.c | 2 +- src/console/console.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 68e81c6..84f97ba 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -41,7 +41,7 @@ void console_tx_byte(unsigned char byte) #if CONFIG_USBDEBUG usbdebug_tx_byte(0, byte); #endif -#if CONFIG_CONSOLE_CBMEM +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) cbmemc_tx_byte(byte); #endif } diff --git a/src/console/console.c b/src/console/console.c index c53adc6..a0e8f6d 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -117,7 +117,7 @@ void console_init(void) #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); #endif -#if CONFIG_CONSOLE_CBMEM +#if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) cbmemc_init(); #endif #if CONFIG_SPKMODEM

1 0

Patch set updated for coreboot: 19ae9db pit: Replace the snow GPIO indexes with ones for pit.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3689 -gerrit commit 19ae9dbeb3b39079007cc574d3287f2feac85018 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 03:29:45 2013 -0700 pit: Replace the snow GPIO indexes with ones for pit. The GPIOs used by vboot and setting up the display and backlight were still the ones for snow. This change updates them so they're correct for pit. Change-Id: I06ba773da3af249efec723bb90c2e9e8075a777a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/chromeos.c | 10 +++++----- src/mainboard/google/pit/mainboard.c | 12 +++++++----- src/mainboard/google/pit/romstage.c | 16 ++++++++-------- 3 files changed, 20 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c index 349ba1d..ae219bb 100644 --- a/src/mainboard/google/pit/chromeos.c +++ b/src/mainboard/google/pit/chromeos.c @@ -36,9 +36,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) int count = 0; /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPD1; + gpios->gpios[count].port = EXYNOS5_GPX3; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO + gpios->gpios[count].value = gpio_get_value(GPIO_X30); // WP_GPIO strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -54,7 +54,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = EXYNOS5_GPX3; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO + gpios->gpios[count].value = gpio_get_value(GPIO_X34); // LID_GPIO strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; @@ -62,7 +62,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->gpios[count].port = EXYNOS5_GPX1; gpios->gpios[count].polarity = ACTIVE_LOW; gpios->gpios[count].value = - gpio_get_value(GPIO_X13); // POWER_GPIO + gpio_get_value(GPIO_X12); // POWER_GPIO strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -91,7 +91,7 @@ int get_recovery_mode_switch(void) uint32_t ec_events; /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO + if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO return 1; ec_events = google_chromeec_get_events_b(); diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index f0df039..1608788 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -49,9 +49,11 @@ static struct edid edid = { }; /* TODO: transplanted DP stuff, clean up once we have something that works */ -static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ -static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ -static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ +static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */ +static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */ +static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */ +static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ +static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ static void exynos_dp_bridge_setup(void) { @@ -115,14 +117,14 @@ static void exynos_dp_reset(void) static void backlight_pwm(void) { /*Configure backlight PWM as a simple output high (100% brightness) */ - gpio_direction_output(GPIO_B20, 1); + gpio_direction_output(bl_pwm, 1); udelay(LCD_T6_DELAY_MS * 1000); } static void backlight_en(void) { /* Configure GPIO for LCD_BL_EN */ - gpio_direction_output(GPIO_X30, 1); + gpio_direction_output(bl_en, 1); } //static struct video_info smdk5420_dp_config = { diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 001d8cf..41b64b2 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -129,17 +129,17 @@ static void setup_graphics(void) static void setup_gpio(void) { - gpio_direction_input(GPIO_D16); // WP_GPIO - gpio_set_pull(GPIO_D16, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X30); // WP_GPIO + gpio_set_pull(GPIO_X30, GPIO_PULL_NONE); - gpio_direction_input(GPIO_Y10); // RECMODE_GPIO - gpio_set_pull(GPIO_Y10, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X07); // RECMODE_GPIO + gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); - gpio_direction_input(GPIO_X35); // LID_GPIO - gpio_set_pull(GPIO_X35, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X34); // LID_GPIO + gpio_set_pull(GPIO_X34, GPIO_PULL_NONE); - gpio_direction_input(GPIO_X13); // POWER_GPIO - gpio_set_pull(GPIO_X13, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X12); // POWER_GPIO + gpio_set_pull(GPIO_X12, GPIO_PULL_NONE); } static void setup_memory(struct mem_timings *mem, int is_resume)

1 0

Patch set updated for coreboot: e121569 pit: Remove the MAX_CPUS option.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3688 -gerrit commit e12156928f35c1cf983ff81fb9b071bb23d07d73 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 02:37:51 2013 -0700 pit: Remove the MAX_CPUS option. The MAX_CPUS option is only used on x86 currently, so there's no reason to have it in the pit config. Change-Id: I270bbfd3aff781d88304791b1d9735777643caab Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index d7409d3..4148101 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER string default "Pit" -config MAX_CPUS - int - default 2 - config DRAM_SIZE_MB int default 2048

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2013