Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3670
-gerrit
commit 7899dbcea734dd9c807169054452d517581957c9
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon May 20 12:51:02 2013 -0700
google/pit: Don't spew output with GPIO config
There are hundreds of GPIOs on the Exynos5420. Don't
always print all of them per default.
Change-Id: I2152ab760e31a335dbcd9d6ad32cd1eaae4b89bc
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/mainboard.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 77d48f9..dccb095 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -201,6 +201,8 @@ static void mainboard_init(device_t dev)
set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
lcd_vdd();
+
+ // FIXME: should timeout
do {
udelay(50);
} while (!exynos_dp_hotplug());
@@ -228,7 +230,8 @@ static void mainboard_init(device_t dev)
if (dp_tries > MAX_DP_TRIES)
printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);
- gpio_info();
+ // Uncomment to get excessive GPIO output:
+ // gpio_info();
}
static void mainboard_enable(device_t dev)
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3668
-gerrit
commit 85f4e699532987c00492beabd9bd93e574fd81c2
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon May 20 15:24:13 2013 -0700
exynos5420: Clear the framebuffer before making it uncacheable
If we clear the framebuffer and then flush it back to memory using cache
operations, the writes are going to be full cachelines at a time. If we
make it uncacheable first, the writes will be serialized writes of
whatever sized chunks memset uses, probably 4 bytes or less.
Change-Id: I960f87a370e97f9e91236ad796d931573bb3dbb8
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index 1d51174..6e360bf 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -97,6 +97,8 @@ static void exynos_displayport_init(device_t dev)
lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size);
printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase));
+ memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
+
/*
* We need to clean and invalidate the framebuffer region and disable
* caching as well. We assume that our dcache <--> memory address
@@ -114,7 +116,6 @@ static void exynos_displayport_init(device_t dev)
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
printk(BIOS_DEBUG,
"Initializing Exynos VGA, base %p\n", (void *)lcdbase);
- memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase);
}
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3667
-gerrit
commit 7f3ea94a440282990e29daec2edfd3323028b6af
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon May 20 15:21:48 2013 -0700
exynos5420: Don't disable and re-enable the MMU when uncaching the framebuffer
At one time it seemed to be necessary to disable and then re-enable the
MMU when setting the framebuffer to be uncache-able due to bugs in the
MMU management code. Since those bugs have been fixed, this is no longer
necessary.
Change-Id: I7ce825cf5eaaa95119364d780cba0935752e4632
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org>
---
src/cpu/samsung/exynos5420/cpu.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index e83c16a..1d51174 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -105,15 +105,11 @@ static void exynos_displayport_init(device_t dev)
* Note: We may want to do something clever to ensure the framebuffer
* region is aligned such that we don't change dcache policy for other
* stuff inadvertantly.
- *
- * FIXME: Is disabling/re-enabling the MMU entirely necessary?
*/
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
dcache_clean_invalidate_by_mva(lower, upper - lower);
- dcache_mmu_disable();
mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF);
- dcache_mmu_enable();
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
printk(BIOS_DEBUG,
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3664
-gerrit
commit 819b265f7145100f6f84b4e6ed381c1653bac996
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Tue Jun 11 21:55:58 2013 -0700
armv7: Reserve space BL1 and checksum header by specifying bootblock offset.
Not all ARM systems need "BL1", and the layout of BL* and bootblock may be
different (ex, Exynos 5250 may use a new BL1 with variable length checksum
header).
To support that better, define the real base address (and ROM offset) of boot
block, and then we can post-processing ROM image file by filling data / checksum
and any other information.
Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/Makefile.inc | 3 ++-
src/arch/armv7/bootblock.inc | 8 --------
src/arch/armv7/bootblock.lds | 3 +--
src/cpu/samsung/exynos5250/Kconfig | 34 +++++++++++++++++++-------------
src/cpu/samsung/exynos5420/Kconfig | 40 +++++++++++++++++++++++---------------
5 files changed, 47 insertions(+), 41 deletions(-)
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index 27a0df6..8474315 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -48,7 +48,8 @@ prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
# TODO Change -b to Kconfig variable.
$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $(objcbfs)/romstage.elf $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file)
$(CBFSTOOL) $@.tmp create -m armv7 -s $(CONFIG_COREBOOT_ROMSIZE_KB)K \
- -B $(objcbfs)/bootblock.bin -a 64 -b 0x0000 \
+ -B $(objcbfs)/bootblock.bin -a 64 \
+ -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) \
-H $(CONFIG_CBFS_HEADER_ROM_OFFSET) \
-o $(CONFIG_CBFS_ROM_OFFSET)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc
index bac32e2..b2c993a 100644
--- a/src/arch/armv7/bootblock.inc
+++ b/src/arch/armv7/bootblock.inc
@@ -29,14 +29,6 @@
* MA 02111-1307 USA
*/
-.section ".bl1", "a", %progbits
-_bl1:
- /* For now we have to live with a first stage boot loader
- * on ARM, which is 8KB in size and it is prepended to the
- * reset vector
- */
- .skip (CONFIG_BL1_SIZE_KB * 1024)
-
.section ".start", "a", %progbits
.globl _start
_start: b reset
diff --git a/src/arch/armv7/bootblock.lds b/src/arch/armv7/bootblock.lds
index 6f6040d..8370396 100644
--- a/src/arch/armv7/bootblock.lds
+++ b/src/arch/armv7/bootblock.lds
@@ -25,12 +25,11 @@ OUTPUT_ARCH(arm)
TARGET(binary)
SECTIONS
{
- ROMLOC = CONFIG_BOOTBLOCK_BASE - (CONFIG_BL1_SIZE_KB * 1024);
+ ROMLOC = CONFIG_BOOTBLOCK_BASE;
/* This section might be better named .setup */
.rom ROMLOC : {
_rom = .;
- *(.bl1);
*(.start);
*(.id);
*(.text);
diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index 5f5add4..75d1178 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -10,9 +10,26 @@ config EXYNOS_ACE_SHA
bool
default n
-config BL1_SIZE_KB
- int
- default 8
+# ROM image layout.
+#
+# 0x0000: vendor-provided BL1 (8k).
+# 0x2000: bootblock
+# 0x2010-0x2090: reserved for CBFS master header.
+# 0xA000: Free for CBFS data.
+
+config BOOTBLOCK_ROM_OFFSET
+ hex
+ default 0x2000
+
+config CBFS_HEADER_ROM_OFFSET
+ hex "offset of master CBFS header in ROM"
+ default 0x2010
+
+config CBFS_ROM_OFFSET
+ # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
+ hex "offset of CBFS data in ROM"
+ default 0x0A000
+
# Example SRAM/iRAM map for Exynos5250 platform:
#
@@ -50,17 +67,6 @@ config STACK_SIZE
hex
default 0x1000
-config CBFS_ROM_OFFSET
- # Calculated by BL1 + max bootblock size.
- hex "offset of CBFS data in ROM"
- default 0x0A000
-
-# TODO Change this to some better address not overlapping bootblock when
-# cbfstool supports creating header in arbitrary location.
-config CBFS_HEADER_ROM_OFFSET
- hex "offset of master CBFS header in ROM"
- default 0x2040
-
# TODO We may probably move this to board-specific implementation files instead
# of KConfig values.
config CBFS_CACHE_ADDRESS
diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig
index 93ece2e..406ffd2 100644
--- a/src/cpu/samsung/exynos5420/Kconfig
+++ b/src/cpu/samsung/exynos5420/Kconfig
@@ -10,20 +10,39 @@ config EXYNOS_ACE_SHA
bool
default n
-config BL1_SIZE_KB
- int
- default 8
+# ROM image layout.
+#
+# 0x0000: vendor-provided BL1 (8k).
+# 0x2000: variable length bootblock checksum header
+# 0x2010: bootblock
+# 0x2020-0x20A0: reserved for CBFS master header.
+# 0xA000: Free for CBFS data.
+
+config BOOTBLOCK_ROM_OFFSET
+ hex
+ default 0x2010
+
+config CBFS_HEADER_ROM_OFFSET
+ hex "offset of master CBFS header in ROM"
+ default 0x2020
+
+config CBFS_ROM_OFFSET
+ # Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
+ hex "offset of CBFS data in ROM"
+ default 0x0A000
+
# Example SRAM/iRAM map for Exynos5420 platform:
#
# 0x0202_0000: vendor-provided BL1
-# 0x0202_4400: bootblock, assume up to 32KB in size
+# 0x0202_4400: variable length bootblock checksum header.
+# 0x0202_4410: bootblock, assume up to 32KB in size
# 0x0203_0000: romstage, assume up to 128KB in size.
# 0x0207_4000: stack pointer
config BOOTBLOCK_BASE
hex
- default 0x02024400
+ default 0x02024410
config ROMSTAGE_BASE
hex
@@ -50,17 +69,6 @@ config STACK_SIZE
hex
default 0x1000
-config CBFS_ROM_OFFSET
- # Calculated by BL1 + max bootblock size.
- hex "offset of CBFS data in ROM"
- default 0x0A000
-
-# TODO Change this to some better address not overlapping bootblock when
-# cbfstool supports creating header in arbitrary location.
-config CBFS_HEADER_ROM_OFFSET
- hex "offset of master CBFS header in ROM"
- default 0x2040
-
# TODO We may probably move this to board-specific implementation files instead
# of KConfig values.
config CBFS_CACHE_ADDRESS
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3679
-gerrit
commit 45853504d25e690ff282a026c2975593595e9af6
Author: Ronald G. Minnich <rminnich(a)google.com>
Date: Tue Jun 18 13:02:23 2013 -0700
ARM: when setting a GPIO to put, set the value, then the direction
We saw a problem on x86 last year in which setting direction, then value,
glitched the output and caused problems. Change this code to set the output,
then the direction.
Change-Id: I3e1e17ffe82ae270eea539530368a58c6cfe0ebe
Signed-off-by: Ronald G. Minnich <rminnich(a)google.com>
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5250/gpio.c | 4 ++--
src/cpu/samsung/exynos5420/gpio.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/cpu/samsung/exynos5250/gpio.c b/src/cpu/samsung/exynos5250/gpio.c
index b8ebb0a..2a93328 100644
--- a/src/cpu/samsung/exynos5250/gpio.c
+++ b/src/cpu/samsung/exynos5250/gpio.c
@@ -170,14 +170,14 @@ int gpio_direction_output(unsigned gpio, int value)
unsigned int val;
struct gpio_bank *bank = gpio_get_bank(gpio);
- gpio_cfg_pin(gpio, GPIO_OUTPUT);
-
val = readl(&bank->dat);
val &= ~DAT_MASK(GPIO_BIT(gpio));
if (value)
val |= DAT_SET(GPIO_BIT(gpio));
writel(val, &bank->dat);
+ gpio_cfg_pin(gpio, GPIO_OUTPUT);
+
return 0;
}
diff --git a/src/cpu/samsung/exynos5420/gpio.c b/src/cpu/samsung/exynos5420/gpio.c
index b8ebb0a..2a93328 100644
--- a/src/cpu/samsung/exynos5420/gpio.c
+++ b/src/cpu/samsung/exynos5420/gpio.c
@@ -170,14 +170,14 @@ int gpio_direction_output(unsigned gpio, int value)
unsigned int val;
struct gpio_bank *bank = gpio_get_bank(gpio);
- gpio_cfg_pin(gpio, GPIO_OUTPUT);
-
val = readl(&bank->dat);
val &= ~DAT_MASK(GPIO_BIT(gpio));
if (value)
val |= DAT_SET(GPIO_BIT(gpio));
writel(val, &bank->dat);
+ gpio_cfg_pin(gpio, GPIO_OUTPUT);
+
return 0;
}