the following patch was just integrated into master:
commit 54d6abd276ac5c60e3846266050167cc1754dcf0
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Jun 19 23:05:00 2013 +0300
Drop some duplicates of PCI-e config functions
These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.
Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3502 for details.
-gerrit
the following patch was just integrated into master:
commit 872c9222965909dffdd091e644b03e676ca2754f
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Jul 3 09:44:28 2013 +0300
Fix MMCONF_SUPPORT_DEFAULT for ramstage
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.
The implementation of pci_default_config() always returned with
pci_cf8_conf1. This means any PCI configuration access that did
not target bus 0 used PCI IO config operations, if PCI MMIO config
was not explicitly requested.
Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/3606
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-by: Aaron Durbin <adurbin(a)google.com>
See http://review.coreboot.org/3606 for details.
-gerrit
the following patch was just integrated into master:
commit 20b6d91fd33f5d90d1c51e2fb813453349398b73
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Fri May 24 03:37:01 2013 +0200
southbridge/intel/i82801gx: Make compilation possible with CONFIG_SMM_TSEG
Without that fix, and with CONFIG_SMM_TSEG, we have:
src/southbridge/intel/i82801gx/smihandler.c: In function 'southbridge_smi_sleep':
src/southbridge/intel/i82801gx/smihandler.c:340:3: error: implicit declaration of function 'smi_release_lock' [-Werror=implicit-function-declaration]
cc1: all warnings being treated as errors
make: *** [build/southbridge/intel/i82801gx/smihandler.smm.o] Error 1
The fix is modelled after src/cpu/x86/smm/smihandler.c which
ifdefs smi_release_lock().
Change-Id: Icdc6d039b34a1d95d0e607419bba2484d21abc5e
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Reviewed-on: http://review.coreboot.org/3281
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3281 for details.
-gerrit
the following patch was just integrated into master:
commit 1b32a51e515ce25495f87a82d1575d26acd93228
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Sun May 26 18:24:41 2013 +0200
i82801gx: smihandle: sync with southbridge/intel/bd82x6x/smihandler.c
Change-Id: Ic725b169061bd426aa8206dc1d6d31e67cc639f2
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Reviewed-on: http://review.coreboot.org/3304
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3304 for details.
-gerrit
the following patch was just integrated into master:
commit b694f10c006168c8497d87d8f33da74724126d01
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Sun May 26 18:12:54 2013 +0200
southbridge: i82801gx: smihandler.c: Correct outl->outw mistake.
This mistake was spoted by comparison with the
src/southbridge/intel/bd82x6x/smihandler.c file.
Change-Id: I1516f0131d524bd7d001e6780e9a45402d1814d1
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Reviewed-on: http://review.coreboot.org/3303
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3303 for details.
-gerrit
the following patch was just integrated into master:
commit 048f9abb0fa5203ed9c44d19960dff41a25e40b6
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Wed Jul 3 15:12:50 2013 +0200
Add support for flash lock on Cougar / Panther Point
Add PCI IDs for Cougar Point and Panther Point PCHs and lock their
SPI interface like we do it in coreboot's resume path. We write a
valid opcode menu but set all flash regions to read only. The regions
are strapped from the flash descriptor.
Change-Id: Ie5735cff02564822139f45666c1f28b080a9c6d3
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Reviewed-on: http://review.coreboot.org/3597
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3597 for details.
-gerrit
the following patch was just integrated into master:
commit d1fb5641b6ae3710b7d6c444000a6cbbe0cb6f74
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon Jul 1 16:02:36 2013 +0200
sandybridge: Add option to lock SPI regions on resume
Add an option to mark all SPI regions write protected on each S3 resume.
We were used to lock the SPI interface in the payload which isn't run on
the resume path. So we have to do it here.
For the write protection to be effective, all write opcodes in the
opmenu have to be marked correctly (as write operations) and the whole
SPI interface has to be locked. Both is already done.
Change-Id: I5c268ae8850642f5e82f18c28c71cf1ae248dbff
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Reviewed-on: http://review.coreboot.org/3594
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/3594 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3602
-gerrit
commit 82445fc8bd749b00a7af9492f249aa0645715a70
Author: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
Date: Thu Jul 4 02:51:42 2013 +0200
w83627hf/acpi: Fix endianess error in floppy drive enumeration code
The enumeration results are stored as five DWORDs in one 20 byte buffer.
Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD.
ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices.
Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb
Signed-off-by: Christoph Grenz <christophg+cb(a)grenz-bonn.de>
---
src/superio/winbond/w83627hf/acpi/superio.asl | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl
index 03f72f7..05b570b 100644
--- a/src/superio/winbond/w83627hf/acpi/superio.asl
+++ b/src/superio/winbond/w83627hf/acpi/superio.asl
@@ -356,10 +356,10 @@ Device(SIO) {
SIFR, 8
}
- CreateByteField (_FDE, 3, FD1)
- CreateByteField (_FDE, 7, FD2)
- CreateByteField (_FDE, 11, FD3)
- CreateByteField (_FDE, 15, FD4)
+ CreateByteField (_FDE, 1, FD1)
+ CreateByteField (_FDE, 4, FD2)
+ CreateByteField (_FDE, 8, FD3)
+ CreateByteField (_FDE, 12, FD4)
Store(One, ACT1)
Store(0, SELE)
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3722
-gerrit
commit 2cfbb7f64b4cfc189e9ac548860f88014a880215
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Jun 30 06:09:12 2013 -0700
pit: Enable the ps8625 driver.
Change-Id: Id1277ceefc844a052627483e6c9d01bcb5da975f
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig
index 20e0084..89ffb5b 100644
--- a/src/mainboard/google/pit/Kconfig
+++ b/src/mainboard/google/pit/Kconfig
@@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_INIT_TIMER
+ select DRIVER_PARADE_PS8625
config MAINBOARD_DIR
string