Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3688
-gerrit
commit 38bbe2e18e4a6bb9900052fbcfcc924edf300062
Author: Gabe Black <gabeblack(a)google.com>
Date: Wed Jun 19 02:37:51 2013 -0700
pit: Remove the MAX_CPUS option.
The MAX_CPUS option is only used on x86 currently, so there's no reason to
have it in the pit config.
Change-Id: I270bbfd3aff781d88304791b1d9735777643caab
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/Kconfig | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig
index d7409d3..4148101 100644
--- a/src/mainboard/google/pit/Kconfig
+++ b/src/mainboard/google/pit/Kconfig
@@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER
string
default "Pit"
-config MAX_CPUS
- int
- default 2
-
config DRAM_SIZE_MB
int
default 2048
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3690
-gerrit
commit fe565c34daa85ee6902b942ce613b42d4e5766f0
Author: Gabe Black <gabeblack(a)google.com>
Date: Wed Jun 19 20:15:57 2013 -0700
ARM: Don't leave alignment checking on after the exception test.
Currently, the exception handling code on ARM turns on alignment checks as an
easy way to generate an exception for testing purposes. It was leaving it on
which disabled unaligned accesses for other, unlreated code running later.
This change adjusts the code so the original value of the alignment bit is
restored after the test exception.
Change-Id: Id8d035a05175f9fb13de547ab4aa5496d681d30c
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/arch/armv7/exception.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/arch/armv7/exception.c b/src/arch/armv7/exception.c
index 14f8216..1055cb5 100644
--- a/src/arch/armv7/exception.c
+++ b/src/arch/armv7/exception.c
@@ -143,9 +143,8 @@ void exception_init(void)
sctlr &= ~sctlr_te;
/* Set V=0 in SCTLR so VBAR points to the exception vector table. */
sctlr &= ~sctlr_v;
- /* Enforce alignment. */
- sctlr |= sctlr_a;
- set_sctlr(sctlr);
+ /* Enforce alignment temporarily. */
+ set_sctlr(sctlr | sctlr_a);
extern uint32_t exception_table[];
set_vbar((uintptr_t)exception_table);
@@ -155,4 +154,7 @@ void exception_init(void)
exception_test();
test_abort = 0;
printk(BIOS_ERR, "Testing exceptions: DONE\n");
+
+ /* Restore original alignment settings. */
+ set_sctlr(sctlr);
}
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3702
-gerrit
commit f78b822a90a8083e2c55c772f90900644778d36e
Author: Gabe Black <gabeblack(a)google.com>
Date: Sun Jun 23 03:16:46 2013 -0700
pit: Configure the pinmux for the i2c busses that are connected on pit.
Change-Id: I2dc4caa370473dd86fee2b5cc8b1b9eb154b970e
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/mainboard/google/pit/mainboard.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 1608788..64783ad 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -159,6 +159,17 @@ static void disable_usb30_pll(void)
gpio_direction_output(usb3_pll_l, 0);
}
+static void gpio_init(void)
+{
+ /* Set up the I2C busses. */
+ exynos_pinmux_i2c2();
+ exynos_pinmux_i2c4();
+ exynos_pinmux_i2c7();
+ exynos_pinmux_i2c8();
+ exynos_pinmux_i2c9();
+ exynos_pinmux_i2c10();
+}
+
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
@@ -169,6 +180,8 @@ static void mainboard_init(device_t dev)
};
void *fb_addr;
+ gpio_init();
+
tmu_init(&exynos5420_tmu_info);
/* Clock Gating all the unused IP's to save power */
Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3703
-gerrit
commit 4e7c0056cbaafb72bb5a791ba3209617004b8eb5
Author: Gabe Black <gabeblack(a)google.com>
Date: Mon Jun 24 03:14:41 2013 -0700
exynos5420: Clock the mmc blocks off of the mpll.
The exynos manual suggests hooking the mmc ip blocks to the mpll. They had
been set to use a different pll. This changes them over and modifies the
divider so that the frequency stays the same.
Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962
Signed-off-by: Gabe Black <gabeblack(a)chromium.org>
---
src/cpu/samsung/exynos5420/setup.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 7d63772..e89ed8e 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -222,7 +222,7 @@ struct exynos5_phy_control;
#define CLK_DIV_CPU0_VAL 0x01440020
/* CLK_SRC_TOP */
-#define CLK_SRC_TOP0_VAL 0x12221222
+#define CLK_SRC_TOP0_VAL 0x12222222
#define CLK_SRC_TOP1_VAL 0x00100200
#define CLK_SRC_TOP2_VAL 0x11101000
#define CLK_SRC_TOP3_VAL 0x11111111
@@ -231,7 +231,7 @@ struct exynos5_phy_control;
#define CLK_SRC_TOP7_VAL 0x00022200
/* CLK_DIV_TOP */
-#define CLK_DIV_TOP0_VAL 0x23712311
+#define CLK_DIV_TOP0_VAL 0x23713311
#define CLK_DIV_TOP1_VAL 0x13100B00
#define CLK_DIV_TOP2_VAL 0x11101100