coreboot-gerrit June 2013

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Patch merged into coreboot/master: f97ff3f dram: Add utilities for decoding DDR3 SPDs
by gerrit＠coreboot.org 03 Jun '13

03 Jun '13

the following patch was just integrated into master: commit f97ff3f72c038b711fd3c1e7b73abaa05add2094 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue May 21 14:43:45 2013 -0500 dram: Add utilities for decoding DDR3 SPDs Add convenience utilities for decoding DDR3 SPDs and printing the information to the console. These have proven invaluable when writing the VX900 memory initialization. These are used in the VX900 branch Information printed has the following format: > SPD Data for DIMM 51 > Revision: 10 > Type : b > Key : 2 > Banks : 8 > Capacity: 1 Gb > Supported voltages: 1.5V > SDRAM width : 8 > Bus extension : 0 bits > Bus width : 64 > Optional features : DLL-Off_mode RZQ/7 RZQ/6 > Thermal features : ASR ext_temp_range > Thermal sensor : no > Standard SDRAM : no > Row addr bits : 13 > Column addr bits : 10 > Number of ranks : 1 > DIMM Capacity : 1024 MB > CAS latencies : 6 7 8 9 > tCKmin : 1.500 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 36.000 ns > tRCmin : 49.125 ns > tRFCmin : 110.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns Change-Id: I30725a75caf74ac637db0a143344562bd9910466 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/3267 Tested-by: build bot (Jenkins) See http://review.coreboot.org/3267 for details. -gerrit

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Patch merged into coreboot/master: 3261046 spd.h: Add all known SPD_MEMORY_TYPE definitions.
by gerrit＠coreboot.org 03 Jun '13

03 Jun '13

the following patch was just integrated into master: commit 32610462d12bee4f901e7f5eefef63f200f22805 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue May 21 14:07:41 2013 -0500 spd.h: Add all known SPD_MEMORY_TYPE definitions. This file was missing some definitions, so add them. Also turn the defines into an enum. The reason for doing this is that functions can now explicitly take an spd_memory_type as a parameter: > int do_something_with_dram(enum spd_memory_type type, ...) Which is a lot more explicit and readable than: > int do_something_with_dram(u8 type, ...) These are used in the VX900 branch. Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/3266 Tested-by: build bot (Jenkins) See http://review.coreboot.org/3266 for details. -gerrit

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Patch merged into coreboot/master: 8e4bb92 util/cbmem: Fix format string in cbmem.c
by gerrit＠coreboot.org 03 Jun '13

03 Jun '13

the following patch was just integrated into master: commit 8e4bb92898992446b6264f06b4f20236a65ae962 Author: Nico Huber <nico.huber(a)secunet.com> Date: Sun May 26 18:17:54 2013 +0200 util/cbmem: Fix format string in cbmem.c Use PRIx64 to print a u64 instead of "llx". Fixes the following error: cbmem.c: In function 'parse_cbtable': cbmem.c:135:2: error: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'u64' [-Werror=format=] Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/3301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/3301 for details. -gerrit

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Patch set updated for coreboot: 2e70616 spd.h: Add all known SPD_MEMORY_TYPE definitions.
by Alexandru Gagniuc 03 Jun '13

03 Jun '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3266 -gerrit commit 2e70616c0249c26e99a6112a32fcb05b8fc5d2fa Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue May 21 14:07:41 2013 -0500 spd.h: Add all known SPD_MEMORY_TYPE definitions. This file was missing some definitions, so add them. Also turn the defines into an enum. The reason for doing this is that functions can now explicitly take an spd_memory_type as a parameter: > int do_something_with_dram(enum spd_memory_type type, ...) Which is a lot more explicit and readable than: > int do_something_with_dram(u8 type, ...) These are used in the VX900 branch. Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/include/spd.h | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/src/include/spd.h b/src/include/spd.h index e8d35cf..2b07fb1 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -108,15 +108,20 @@ /* SPD_MEMORY_TYPE values. */ -#define SPD_MEMORY_TYPE_FPM_DRAM 1 -#define SPD_MEMORY_TYPE_EDO 2 -#define SPD_MEMORY_TYPE_PIPELINED_NIBBLE 3 -#define SPD_MEMORY_TYPE_SDRAM 4 -#define SPD_MEMORY_TYPE_MULTIPLEXED_ROM 5 -#define SPD_MEMORY_TYPE_SGRAM_DDR 6 -#define SPD_MEMORY_TYPE_SDRAM_DDR 7 -#define SPD_MEMORY_TYPE_SDRAM_DDR2 8 -#define SPD_MEMORY_TYPE_SDRAM_DDR3 0xb +enum spd_memory_type { + SPD_MEMORY_TYPE_UNDEFINED = 0x00, + SPD_MEMORY_TYPE_FPM_DRAM = 0x01, + SPD_MEMORY_TYPE_EDO = 0x02, + SPD_MEMORY_TYPE_PIPELINED_NIBBLE = 0x03, + SPD_MEMORY_TYPE_SDRAM = 0x04, + SPD_MEMORY_TYPE_MULTIPLEXED_ROM = 0x05, + SPD_MEMORY_TYPE_SGRAM_DDR = 0x06, + SPD_MEMORY_TYPE_SDRAM_DDR = 0x07, + SPD_MEMORY_TYPE_SDRAM_DDR2 = 0x08, + SPD_MEMORY_TYPE_FBDIMM_DDR2 = 0x09, + SPD_MEMORY_TYPE_FB_PROBE_DDR2 = 0x0a, + SPD_MEMORY_TYPE_SDRAM_DDR3 = 0x0b, +}; /* SPD_MODULE_VOLTAGE values. */ #define SPD_VOLTAGE_TTL 0 /* 5.0 Volt/TTL */

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Patch set updated for coreboot: aeca86d dram: Add utilities for decoding DDR3 SPDs
by Alexandru Gagniuc 03 Jun '13

03 Jun '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3267 -gerrit commit aeca86d82e2de062ba1a70bbe1e2d7d6c40324bc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue May 21 14:43:45 2013 -0500 dram: Add utilities for decoding DDR3 SPDs Add convenience utilities for decoding DDR3 SPDs and printing the information to the console. These have proven invaluable when writing the VX900 memory initialization. These are used in the VX900 branch Information printed has the following format: > SPD Data for DIMM 51 > Revision: 10 > Type : b > Key : 2 > Banks : 8 > Capacity: 1 Gb > Supported voltages: 1.5V > SDRAM width : 8 > Bus extension : 0 bits > Bus width : 64 > Optional features : DLL-Off_mode RZQ/7 RZQ/6 > Thermal features : ASR ext_temp_range > Thermal sensor : no > Standard SDRAM : no > Row addr bits : 13 > Column addr bits : 10 > Number of ranks : 1 > DIMM Capacity : 1024 MB > CAS latencies : 6 7 8 9 > tCKmin : 1.500 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 36.000 ns > tRCmin : 49.125 ns > tRFCmin : 110.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns Change-Id: I30725a75caf74ac637db0a143344562bd9910466 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/device/dram/ddr3.c | 372 +++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr3.h | 189 +++++++++++++++++++++ 2 files changed, 561 insertions(+) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c new file mode 100644 index 0000000..c745bd7 --- /dev/null +++ b/src/device/dram/ddr3.c @@ -0,0 +1,372 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/** + * @file ddr3_util.h + * + * \brief Utilities for decoding DDR3 SPDs + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/dram/ddr3.h> + +/** + * \brief Checks if the DIMM is Registered based on byte[3] of the SPD + * + * Tells if the DIMM type is registered or not. + * + * @param type DIMM type. This is byte[3] of the SPD. + */ +int dimm_is_registered(enum spd_dimm_type type) +{ + if ((type == SPD_DIMM_TYPE_RDIMM) + | (type == SPD_DIMM_TYPE_MINI_RDIMM) + | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + return 1; + + return 0; +} + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR3 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr stucture where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD + * SPD_STATUS_CRC_ERROR -- CRC did not verify + * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was + * detected. + */ +int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) +{ + int nCRC, i, ret; + u16 crc, spd_crc; + u8 *ptr = spd; + u8 ftb_divisor, ftb_dividend, capacity_shift, bus_width, sdram_width; + u8 reg8; + u32 mtb; /* medium time base */ + unsigned int val, param; + + ret = SPD_STATUS_OK; + + /* Don't assume we memset 0 dimm struct. Clear all our flags */ + dimm->flags.raw = 0; + /* Make sure that the SPD dump is indeed from a DDR3 module */ + if (spd[2] != SPD_MEMORY_TYPE_SDRAM_DDR3) { + printram("Not a DDR3 SPD!\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; + + /* Find the number of bytes covered by CRC */ + if (spd[0] & 0x80) { + nCRC = 117; + } else { + nCRC = 126; + } + + /* Compute the CRC */ + crc = 0; + while (--nCRC >= 0) { + crc = crc ^ (int)*ptr++ << 8; + for (i = 0; i < 8; ++i) + if (crc & 0x8000) { + crc = crc << 1 ^ 0x1021; + } else { + crc = crc << 1; + } + } + /* Compare with the CRC in the SPD */ + spd_crc = (spd[127] << 8) + spd[126]; + /* Verify the CRC is correct */ + if (crc != spd_crc) { + printram("ERROR: SPD CRC failed!!!"); + ret = SPD_STATUS_CRC_ERROR; + }; + + printram(" Revision: %x\n", spd[1]); + printram(" Type : %x\n", spd[2]); + printram(" Key : %x\n", spd[3]); + + reg8 = spd[4]; + /* Number of memory banks */ + val = (reg8 >> 4) & 0x07; + if (val > 0x03) { + printram(" Invalid number of memory banks\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + param = 1 << (val + 3); + printram(" Banks : %u\n", param); + /* SDRAM capacity */ + capacity_shift = reg8 & 0x0f; + if (capacity_shift > 0x06) { + printram(" Invalid module capacity\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + if (capacity_shift < 0x02) { + printram(" Capacity: %u Mb\n", 256 << capacity_shift); + } else { + printram(" Capacity: %u Gb\n", 1 << (capacity_shift - 2)); + } + + reg8 = spd[5]; + /* Row address bits */ + val = (reg8 >> 3) & 0x07; + if (val > 0x04) { + printram(" Invalid row address bits\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + dimm->row_bits = val + 12; + /* Column address bits */ + val = reg8 & 0x07; + if (val > 0x03) { + printram(" Invalid column address bits\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + dimm->col_bits = val + 9; + + /* Module nominal voltage */ + reg8 = spd[6]; + printram(" Supported voltages:"); + if (reg8 & (1 << 2)) { + dimm->flags.operable_1_25V = 1; + printram(" 1.25V"); + } + if (reg8 & (1 << 1)) { + dimm->flags.operable_1_35V = 1; + printram(" 1.35V"); + } + if (!(reg8 & (1 << 0))) { + dimm->flags.operable_1_50V = 1; + printram(" 1.5V"); + } + printram("\n"); + + /* Module organization */ + reg8 = spd[7]; + /* Number of ranks */ + val = (reg8 >> 3) & 0x07; + if (val > 3) { + printram(" Invalid number of ranks\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + dimm->ranks = val + 1; + /* SDRAM device width */ + val = (reg8 & 0x07); + if (val > 3) { + printram(" Invalid SDRAM width\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + sdram_width = (4 << val); + printram(" SDRAM width : %u\n", sdram_width); + + /* Memory bus width */ + reg8 = spd[8]; + /* Bus extension */ + val = (reg8 >> 3) & 0x03; + if (val > 1) { + printram(" Invalid bus extension\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + dimm->flags.is_ecc = val ? 1 : 0; + printram(" Bus extension : %u bits\n", val ? 8 : 0); + /* Bus width */ + val = reg8 & 0x07; + if (val > 3) { + printram(" Invalid bus width\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + bus_width = 8 << val; + printram(" Bus width : %u\n", bus_width); + + /* We have all the info we need to compute the dimm size */ + /* Capacity is 256Mbit multiplied by the power of 2 specified in + * capacity_shift + * The rest is the JEDEC formula */ + dimm->size_mb = ((1 << (capacity_shift + (25 - 20))) * bus_width + * dimm->ranks) / sdram_width; + + /* Fine Timebase (FTB) Dividend/Divisor */ + /* Dividend */ + ftb_dividend = (spd[9] >> 4) & 0x0f; + /* Divisor */ + ftb_divisor = spd[9] & 0x0f; + + /* Medium Timebase = + * Medium Timebase (MTB) Dividend / + * Medium Timebase (MTB) Divisor */ + mtb = (((u32) spd[10]) << 8) / spd[11]; + + /* SDRAM Minimum Cycle Time (tCKmin) */ + dimm->tCK = spd[12] * mtb; + /* CAS Latencies Supported */ + dimm->cas_supported = (spd[15] << 8) + spd[14]; + /* Minimum CAS Latency Time (tAAmin) */ + dimm->tAA = spd[16] * mtb; + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = spd[17] * mtb; + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = spd[18] * mtb; + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = spd[19] * mtb; + /* Minimum Row Precharge Delay Time (tRPmin) */ + dimm->tRP = spd[20] * mtb; + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = (((spd[21] & 0x0f) << 8) + spd[22]) * mtb; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + dimm->tRC = (((spd[21] & 0xf0) << 4) + spd[23]) * mtb; + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + dimm->tRFC = ((spd[25] << 8) + spd[24]) * mtb; + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = spd[26] * mtb; + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = spd[27] * mtb; + /* Minimum Four Activate Window Delay Time (tFAWmin) */ + dimm->tFAW = (((spd[28] & 0x0f) << 8) + spd[29]) * mtb; + + /* SDRAM Optional Features */ + reg8 = spd[30]; + printram(" Optional features :"); + if (reg8 & 0x80) { + dimm->flags.dll_off_mode = 1; + printram(" DLL-Off_mode"); + } + if (reg8 & 0x02) { + dimm->flags.rzq7_supported = 1; + printram(" RZQ/7"); + } + if (reg8 & 0x01) { + dimm->flags.rzq6_supported = 1; + printram(" RZQ/6"); + } + printram("\n"); + + /* SDRAM Thermal and Refresh Options */ + reg8 = spd[31]; + printram(" Thermal features :"); + if (reg8 & 0x80) { + dimm->flags.pasr = 1; + printram(" PASR"); + } + if (reg8 & 0x08) { + dimm->flags.odts = 1; + printram(" ODTS"); + } + if (reg8 & 0x04) { + dimm->flags.asr = 1; + printram(" ASR"); + } + if (reg8 & 0x02) { + dimm->flags.ext_temp_range = 1; + printram(" ext_temp_refresh"); + } + if (reg8 & 0x01) { + dimm->flags.ext_temp_refresh = 1; + printram(" ext_temp_range"); + } + printram("\n"); + + /* Module Thermal Sensor */ + reg8 = spd[32]; + if (reg8 & 0x80) + dimm->flags.therm_sensor = 1; + printram(" Thermal sensor : %s\n", + dimm->flags.therm_sensor ? "yes" : "no"); + + /* SDRAM Device Type */ + reg8 = spd[33]; + printram(" Standard SDRAM : %s\n", (reg8 & 0x80) ? "no" : "yes"); + + if (spd[63] & 0x01) { + dimm->flags.pins_mirrored = 1; + printram(" DIMM Rank1 Address bits mirrorred!!!\n"); + } + + return ret; +} + +/* + * The information printed below has a more informational character, and is not + * necessarily tied in to RAM init debugging. Hence, we stop using printram(), + * and use the standard printk()'s below. + */ + +static void print_ns(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); +} + +/** +* \brief Print the info in DIMM +* +* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* selected, or for a purely informative output. +* +* @param dimm pointer to already decoded @ref dimm_attr stucture +*/ +void dram_print_spd_ddr3(const dimm_attr * dimm) +{ + u16 val16; + int i; + + printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); + printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); + printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); + printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); + + /* CAS Latencies Supported */ + val16 = dimm->cas_supported; + printk(BIOS_INFO, " CAS latencies :"); + i = 0; + do { + if (val16 & 1) + printk(BIOS_INFO, " %u", i + 4); + i++; + val16 >>= 1; + } while (val16); + printk(BIOS_INFO, "\n"); + + print_ns(" tCKmin : ", dimm->tCK); + print_ns(" tAAmin : ", dimm->tAA); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tFAWmin : ", dimm->tFAW); + +} diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h new file mode 100644 index 0000000..926f7b9 --- /dev/null +++ b/src/include/device/dram/ddr3.h @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef DEVICE_DRAM_DDR3L_H +#define DEVICE_DRAM_DDR3L_H + +/** + * @file ddr3.h + * + * \brief Utilities for decoding DDR3 SPDs + */ + +#include <stdint.h> +#include <spd.h> + +/** + * \brief Convenience definitions for TCK values + * + * Different values for tCK, representing standard DDR3 frequencies. + * These values are in 1/256 ns units. + * @{ + */ +#define TCK_1066MHZ 240 +#define TCK_800MHZ 320 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 +/** @} */ + +/** + * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * + * Use this macro instead of printk(); for verbose RAM initialization messages. + * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * disabled. + * @{ + */ +#if defined(CONFIG_DEBUG_RAM_SETUP) && (CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif +/** @} */ + +/* + * Module type (byte 3, bits 3:0) of SPD + * This definition is specific to DDR3. DDR2 SPDs have a diferent structure. + */ +enum spd_dimm_type { + SPD_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DIMM_TYPE_RDIMM = 0x01, + SPD_DIMM_TYPE_UDIMM = 0x02, + SPD_DIMM_TYPE_SO_DIMM = 0x03, + SPD_DIMM_TYPE_MICRO_DIMM = 0x04, + SPD_DIMM_TYPE_MINI_RDIMM = 0x05, + SPD_DIMM_TYPE_MINI_UDIMM = 0x06, + SPD_DIMM_TYPE_MINI_CDIMM = 0x07, + SPD_DIMM_TYPE_72B_SO_UDIMM = 0x08, + SPD_DIMM_TYPE_72B_SO_RDIMM = 0x09, + SPD_DIMM_TYPE_72B_SO_CDIMM = 0x0a, + SPD_DIMM_TYPE_LRDIMM = 0x0b, + SPD_DIMM_TYPE_16B_SO_DIMM = 0x0d, + SPD_DIMM_TYPE_32B_SO_DIMM = 0x0e, + /* Masks to bits 3:0 to give the dimm type */ + SPD_DIMM_TYPE_MASK = 0x0f, +}; + +/** + * \brief DIMM flags + * + * Characteristic flags for the DIMM, as presented by the SPD + */ +typedef union dimm_flags_st { + /* The whole point of the union/struct construct is to allow us to clear + * all the bits with one line: flags.raw = 0. + * We do not care how these bits are ordered */ + struct { + /* Indicates if rank 1 of DIMM uses a mirrored pin mapping. See: + * Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM */ + unsigned pins_mirrored:1; + /* Module can work at 1.50V - All DIMMS must be 1.5V operable */ + unsigned operable_1_50V:1; + /* Module can work at 1.35V */ + unsigned operable_1_35V:1; + /* Module can work at 1.20V */ + unsigned operable_1_25V:1; + /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ + unsigned is_ecc:1; + /* DLL-Off Mode Support */ + unsigned dll_off_mode:1; + /* Indicates a drive strength of RZQ/6 (40 Ohm) is supported */ + unsigned rzq6_supported:1; + /* Indicates a drive strength of RZQ/7 (35 Ohm) is supported */ + unsigned rzq7_supported:1; + /* Partial Array Self Refresh */ + unsigned pasr:1; + /* On-die Thermal Sensor Readout */ + unsigned odts:1; + /* Auto Self Refresh */ + unsigned asr:1; + /* Extended temperature range supported */ + unsigned ext_temp_range:1; + /* Operating at extended temperature requires 2X refresh rate */ + unsigned ext_temp_refresh:1; + /* Thermal sensor incorporated */ + unsigned therm_sensor:1; + }; + unsigned raw; +} dimm_flags_t; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + enum spd_memory_type dram_type; + u16 cas_supported; + /* Flags extracted from SPD */ + dimm_flags_t flags; + /* Number of ranks */ + u8 ranks; + /* Number or row address bits */ + u8 row_bits; + /* Number or column address bits */ + u8 col_bits; + /* Size of module in MiB */ + u32 size_mb; + /* Latencies are in units of 1/256 ns */ + u32 tCK; + u32 tAA; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tFAW; +} dimm_attr; + +/** Result of the SPD decoding process */ +enum spd_status { + SPD_STATUS_OK = 0, + SPD_STATUS_INVALID, + SPD_STATUS_CRC_ERROR, + SPD_STATUS_INVALID_FIELD, +}; + +typedef u8 spd_raw_data[256]; + +int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd_data); +int dimm_is_registered(enum spd_dimm_type type); +void dram_print_spd_ddr3(const dimm_attr * dimm); + +/** + * \brief Read double word from specified address + * + * Should be useful when doing an MRS to the DIMM + */ +static inline u32 volatile_read(volatile u32 addr) +{ + volatile u32 result; + result = *(volatile u32 *)addr; + return result; +} + +#endif /* DEVICE_DRAM_DDR3_H */

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Patch set updated for coreboot: 59f6234 PC Engines ALIX.1C: Add CMOS defaults.
by Denis Carikli 03 Jun '13

03 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3323 -gerrit commit 59f6234e62ee4880b34d28774c54dbd8aa474cd9 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 23:35:18 2013 +0200 PC Engines ALIX.1C: Add CMOS defaults. After Booting the BIOS, flashing coreboot and booting coreboot with that patch we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0x7f nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/pcengines/alix1c/Kconfig | 2 ++ src/mainboard/pcengines/alix1c/cmos.default | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/mainboard/pcengines/alix1c/Kconfig b/src/mainboard/pcengines/alix1c/Kconfig index 315b7ed..fab8710 100644 --- a/src/mainboard/pcengines/alix1c/Kconfig +++ b/src/mainboard/pcengines/alix1c/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select POWER_BUTTON_DEFAULT_DISABLE + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/alix1c/cmos.default b/src/mainboard/pcengines/alix1c/cmos.default new file mode 100644 index 0000000..189c691 --- /dev/null +++ b/src/mainboard/pcengines/alix1c/cmos.default @@ -0,0 +1,11 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Disable +baud_rate=115200 +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0x7f

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Patch set updated for coreboot: 54a24fb Lenovo X60: Add CMOS defaults.
by Denis Carikli 03 Jun '13

03 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3335 -gerrit commit 54a24fb7f65d2a707b92f945d7ababa7d211f5a1 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed May 29 21:25:05 2013 +0200 Lenovo X60: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback baud_rate = 115200 debug_level = Spew hyper_threading = Enable nmi = Enable boot_devices = '' boot_default = 0x40 cmos_defaults_loaded = Yes lpt = Enable volume = 0xff tft_brightness = 0xbf first_battery = Primary bluetooth = Enable The code for handling the invalid CMOS space in mainboard.c is now useless and so it was removed. Change-Id: Ic57a14eeeea861aa034cb0884795b0152757bf5b Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/cmos.default | 14 ++++++++++++++ src/mainboard/lenovo/x60/mainboard.c | 17 ----------------- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1431a2f..5ecad2f 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_LENOVO_H8 select DRIVERS_ICS_954309 select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select MMCONF_SUPPORT diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default new file mode 100644 index 0000000..5d82ff0 --- /dev/null +++ b/src/mainboard/lenovo/x60/cmos.default @@ -0,0 +1,14 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +hyper_threading=Enable +nmi=Enable +boot_devices='' +boot_default=0x40 +cmos_defaults_loaded=Yes +lpt=Enable +volume=0x3 +tft_brightness=0xff +first_battery=Primary +bluetooth=Enable diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 3cb28ff..032d641 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -54,7 +54,6 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_enable(device_t dev) { device_t dev0, idedev, sdhci_dev; - u8 defaults_loaded = 0; ec_clr_bit(0x03, 2); @@ -92,22 +91,6 @@ static void mainboard_enable(device_t dev) pci_write_config8(sdhci_dev, 0xf9, 0x00); } } - - if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) { - printk(BIOS_INFO, "failed to get cmos_defaults_loaded"); - defaults_loaded = 0; - } - - if (!defaults_loaded) { - printk(BIOS_INFO, "Restoring CMOS defaults\n"); - set_option("tft_brightness", &(u8[]){ 0xff }); - set_option("volume", &(u8[]){ 0x03 }); - /* set baudrate to 115200 baud */ - set_option("baud_rate", &(u8[]){ 0x00 }); - /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */ - set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 }); - set_option("cmos_defaults_loaded", &(u8[]){ 0x01 }); - } } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: 0526b14 Asus M4A785T-M: Add CMOS defaults.
by Denis Carikli 03 Jun '13

03 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3324 -gerrit commit 0526b1493fb5ac06ef01cc4af5449faed48666bf Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu May 9 16:14:59 2013 +0200 Asus M4A785T-M: Add CMOS defaults. After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Enable baud_rate = 115200 hw_scrubber = Enable interleave_chip_selects = Enable max_mem_clock = 400Mhz multi_core = Enable power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0xc slow_cpu = off nmi = Enable iommu = Enable nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide. nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/Kconfig | 1 + src/mainboard/asus/m4a785t-m/cmos.default | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 10f6838..6816d58 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default new file mode 100644 index 0000000..da086de --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +ECC_memory=Enable +baud_rate=115200 +hw_scrubber=Enable +interleave_chip_selects=Enable +max_mem_clock=400Mhz +multi_core=Enable +power_on_after_fail=Disable +debug_level=Spew +boot_first=HDD +boot_second=Fallback_Floppy +boot_third=Fallback_Network +boot_index=0xf +boot_countdown=0xc +slow_cpu=off +nmi=Enable +iommu=Enable

1 0

Patch set updated for coreboot: bf8a4aa util/cbmem: Fix format string in cbmem.c
by Nico Huber 03 Jun '13

03 Jun '13

Nico Huber (nico.huber(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3301 -gerrit commit bf8a4aa59118a14720ecacc475e0a54ce048f79a Author: Nico Huber <nico.huber(a)secunet.com> Date: Sun May 26 18:17:54 2013 +0200 util/cbmem: Fix format string in cbmem.c Use PRIx64 to print a u64 instead of "llx". Fixes the following error: cbmem.c: In function 'parse_cbtable': cbmem.c:135:2: error: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'u64' [-Werror=format=] Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/cbmem/cbmem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1ff9a08..74e0fd4 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <inttypes.h> #include <stdio.h> #include <stdlib.h> #include <string.h> @@ -132,7 +133,7 @@ static int parse_cbtable(u64 address) int i, found = 0; void *buf; - debug("Looking for coreboot table at %llx\n", address); + debug("Looking for coreboot table at %" PRIx64 "\n", address); buf = map_memory(address); /* look at every 16 bytes within 4K of the base */

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New patch to review for coreboot: 59c72d4 DDR3: Add utilities for creating MRS commands
by Alexandru Gagniuc 03 Jun '13

03 Jun '13

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3354 -gerrit commit 59c72d4663a483700080529f7f9f4a0491beeb82 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Jun 3 13:58:10 2013 -0500 DDR3: Add utilities for creating MRS commands MRS commands are used to tell the DRAM chip what timing and what termination and drive strength to use, along with other parameters. The MRS commands are defined by the DDR3 specification [1]. This makes MRS commands hardware-independent. MRS command creation is duplicated in various shapes and forms in any chipset that does DDR3. This is an effort to create a generic MRS API that can be used with any chipset. This is used in the VX900 branch. [1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/device/dram/ddr3.c | 195 +++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr3.h | 119 +++++++++++++++++++++++++ 2 files changed, 314 insertions(+) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index c745bd7..5318d64 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -27,6 +27,10 @@ #include <device/device.h> #include <device/dram/ddr3.h> +/*============================================================================== + * = DDR3 SPD decoding helpers + *----------------------------------------------------------------------------*/ + /** * \brief Checks if the DIMM is Registered based on byte[3] of the SPD * @@ -368,5 +372,196 @@ void dram_print_spd_ddr3(const dimm_attr * dimm) print_ns(" tWTRmin : ", dimm->tWTR); print_ns(" tRTPmin : ", dimm->tRTP); print_ns(" tFAWmin : ", dimm->tFAW); +} + +/*============================================================================== + *= DDR3 MRS helpers + *----------------------------------------------------------------------------*/ + +/* + * MRS command structure: + * cmd[15:0] = Address pins MA[15:0] + * cmd[18:16] = Bank address BA[2:0] + */ + +static u16 ddr3_twr_to_mr0_map(u8 twr) +{ + if ((twr >= 5) && (twr <= 8)) + return (twr - 4) << 9; + + if ((twr >= 9) && (twr <= 14)) + return (twr >> 1) << 9; + + /* tWR == 16T is [000] */ + return 0; +} + +/* Map the cas latency to a bitmask for the MR0 cycle */ +static u16 ddr3_cas_to_mr0_map(u8 cas) +{ + u16 mask = 0; + /* A[6:4] are bits [2:0] of (CAS - 4) */ + mask = ((cas - 4) & 0x07) << 4; + + /* A2 is the MSB of (CAS - 4) */ + if ((cas - 4) & (1 << 4)) + mask |= (1 << 2); + + return mask; +} + +/** + * \brief Get command address for a DDR3 MR0 command + */ +mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, + u8 write_recovery, + enum ddr3_mr0_dll_reset dll_reset, + enum ddr3_mr0_mode mode, + u8 cas, + enum ddr3_mr0_burst_type burst_type, + enum ddr3_mr0_burst_length burst_lenght) +{ + mrs_cmd_t cmd = 0 << 16; + + if (precharge_pd == DDR3_MR0_PRECHARGE_FAST) + cmd |= (1 << 12); + + cmd |= ddr3_twr_to_mr0_map(write_recovery); + + if (dll_reset == DDR3_MR0_DLL_RESET_YES) + cmd |= (1 << 8); + + if (mode == DDR3_MR0_MODE_TEST) + cmd |= (1 << 7); + + cmd |= ddr3_cas_to_mr0_map(cas); + + if (burst_type == DDR3_MR0_BURST_TYPE_INTERLEAVED) + cmd |= (1 << 3); + + cmd |= (burst_lenght & 0x03) << 0; + + return cmd; +} + +static u16 ddr3_rtt_nom_to_mr1_map(enum ddr3_mr1_rtt_nom rtt_nom) +{ + u16 mask = 0; + /* A9 <-> rtt_nom[2] */ + if (rtt_nom & (1 << 2)) + mask |= (1 << 9); + /* A6 <-> rtt_nom[1] */ + if (rtt_nom & (1 << 1)) + mask |= (1 << 6); + /* A2 <-> rtt_nom[0] */ + if (rtt_nom & (1 << 0)) + mask |= (1 << 2); + + return mask; +} + +static u16 ddr3_ods_to_mr1_map(enum ddr3_mr1_ods ods) +{ + u16 mask = 0; + /* A5 <-> ods[1] */ + if (ods & (1 << 1)) + mask |= (1 << 5); + /* A1 <-> ods[0] */ + if (ods & (1 << 0)) + mask |= (1 << 1); + + return mask; +} +/** + * \brief Get command address for a DDR3 MR1 command + */ +mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, + enum ddr3_mr1_tqds tqds, + enum ddr3_mr1_rtt_nom rtt_nom, + enum ddr3_mr1_write_leveling write_leveling, + enum ddr3_mr1_ods ods, + enum ddr3_mr1_additive_latency additive_latency, + enum ddr3_mr1_dll dll_disable) +{ + mrs_cmd_t cmd = 1 << 16; + + if (qoff == DDR3_MR1_QOFF_DISABLE) + cmd |= (1 << 12); + + if (tqds == DDR3_MR1_TQDS_ENABLE) + cmd |= (1 << 11); + + cmd |= ddr3_rtt_nom_to_mr1_map(rtt_nom); + + if (write_leveling == DDR3_MR1_WRLVL_ENABLE) + cmd |= (1 << 7); + + cmd |= ddr3_ods_to_mr1_map(ods); + + cmd |= (additive_latency & 0x03) << 3; + + if (dll_disable == DDR3_MR1_DLL_DISABLE) + cmd |= (1 << 0); + + return cmd; +} + +/** + * \brief Get command address for a DDR3 MR2 command + */ +mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, + enum ddr3_mr2_srt_range extended_temp, + enum ddr3_mr2_asr self_refresh, u8 cas_cwl) +{ + mrs_cmd_t cmd = 2 << 16; + + cmd |= (rtt_wr & 0x03) << 9; + + if (extended_temp == DDR3_MR2_SRT_EXTENDED) + cmd |= (1 << 7); + + if (self_refresh == DDR3_MR2_ASR_AUTO) + cmd |= (1 << 6); + + cmd |= ((cas_cwl - 5) & 0x07) << 3; + + return cmd; +} + +/** + * \brief Get command address for a DDR3 MR3 command + */ +mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr) +{ + mrs_cmd_t cmd = 3 << 16; + + if (dataflow_from_mpr) + cmd |= (1 << 2); + + return cmd; +} + +mrs_cmd_t ddr3_mrs_swap_pins(mrs_cmd_t cmd); + +/** + * \brief Mirror the address bits for this MRS command + * + * Swap the following bits in the MRS command: + * - MA3 <-> MA4 + * - MA5 <-> MA6 + * - MA7 <-> MA8 + * - BA0 <-> BA1 + */ +mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd) +{ + u32 downshift, upshift; + /* High bits= A4 | A6 | A8 | BA1 */ + /* Low bits = A3 | A5 | A7 | BA0 */ + u32 lowbits = (1 << 3) | (1 << 5) | (1 << 7) | (1 << 16); + downshift = (cmd & (lowbits << 1)); + upshift = (cmd & lowbits); + cmd &= ~(lowbits | (lowbits << 1)); + cmd |= (downshift >> 1) | (upshift << 1); + return cmd; } diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 926f7b9..fb50808 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -186,4 +186,123 @@ static inline u32 volatile_read(volatile u32 addr) return result; } +/** + * \brief Representation of an MRS command + * + * This represents an MRS command as seen by the DIMM. This is not a memory + * address that can be read to generate an MRS command. The mapping of CPU + * to memory pins is hardware-dependent. + * \n + * The idea is to generalize the MRS code, and only need a hardware-specific + * function to map the MRS bits to CPU address bits. An MRS command can be + * sent like: + * @code{.c} + * u32 addr; + * mrs_cmd_t mrs; + * chipset_enable_mrs_command_mode(); + * mrs = ddr3_get_mr2(rtt_wr, srt, asr, cwl) + * if (rank_has_mirrorred_pins) + * mrs = ddr3_mrs_mirror_pins(mrs); + * addr = chipset_specific_get_mrs_addr(mrs); + * volatile_read(addr); + * @endcode + * + * The MRS representation has the following structure: + * - cmd[15:0] = Address pins MA[15:0] + * - cmd[18:16] = Bank address BA[2:0] + */ +typedef u32 mrs_cmd_t; + +enum ddr3_mr0_precharge { + DDR3_MR0_PRECHARGE_SLOW = 0, + DDR3_MR0_PRECHARGE_FAST = 1, +}; +enum ddr3_mr0_mode { + DDR3_MR0_MODE_NORMAL = 0, + DDR3_MR0_MODE_TEST = 1, +}; +enum ddr3_mr0_dll_reset { + DDR3_MR0_DLL_RESET_NO = 0, + DDR3_MR0_DLL_RESET_YES = 1, +}; +enum ddr3_mr0_burst_type { + DDR3_MR0_BURST_TYPE_SEQUENTIAL = 0, + DDR3_MR0_BURST_TYPE_INTERLEAVED = 1, +}; +enum ddr3_mr0_burst_length { + DDR3_MR0_BURST_LENGTH_8 = 0, + DDR3_MR0_BURST_LENGTH_CHOP = 1, + DDR3_MR0_BURST_LENGTH_4 = 2, +}; +mrs_cmd_t ddr3_get_mr0(enum ddr3_mr0_precharge precharge_pd, + u8 write_recovery, + enum ddr3_mr0_dll_reset dll_reset, + enum ddr3_mr0_mode mode, + u8 cas, + enum ddr3_mr0_burst_type interleaved_burst, + enum ddr3_mr0_burst_length burst_lenght); + +enum ddr3_mr1_qoff { + DDR3_MR1_QOFF_ENABLE = 0, + DDR3_MR1_QOFF_DISABLE = 1, +}; +enum ddr3_mr1_tqds { + DDR3_MR1_TQDS_DISABLE = 0, + DDR3_MR1_TQDS_ENABLE = 1, +}; +enum ddr3_mr1_write_leveling { + DDR3_MR1_WRLVL_DISABLE = 0, + DDR3_MR1_WRLVL_ENABLE = 1, +}; +enum ddr3_mr1_rtt_nom { + DDR3_MR1_RTT_NOM_OFF = 0, + DDR3_MR1_RTT_NOM_RZQ4 = 1, + DDR3_MR1_RTT_NOM_RZQ2 = 2, + DDR3_MR1_RTT_NOM_RZQ6 = 3, + DDR3_MR1_RTT_NOM_RZQ12 = 4, + DDR3_MR1_RTT_NOM_RZQ8 = 5, +}; +enum ddr3_mr1_additive_latency { + DDR3_MR1_AL_DISABLE = 0, + DDR3_MR1_AL_CL_MINUS_1 = 1, + DDR3_MR1_AL_CL_MINUS_2 = 2, +}; +enum ddr3_mr1_ods { + DDR3_MR1_ODS_RZQ6 = 0, + DDR3_MR1_ODS_RZQ7 = 1, +}; +enum ddr3_mr1_dll { + DDR3_MR1_DLL_ENABLE = 0, + DDR3_MR1_DLL_DISABLE = 1, +}; + +mrs_cmd_t ddr3_get_mr1(enum ddr3_mr1_qoff qoff, + enum ddr3_mr1_tqds tqds, + enum ddr3_mr1_rtt_nom rtt_nom, + enum ddr3_mr1_write_leveling write_leveling, + enum ddr3_mr1_ods output_drive_strenght, + enum ddr3_mr1_additive_latency additive_latency, + enum ddr3_mr1_dll dll_disable); + +enum ddr3_mr2_rttwr { + DDR3_MR2_RTTWR_OFF = 0, + DDR3_MR2_RTTWR_RZQ4 = 1, + DDR3_MR2_RTTWR_RZQ2 = 2, +}; +enum ddr3_mr2_srt_range { + DDR3_MR2_SRT_NORMAL = 0, + DDR3_MR2_SRT_EXTENDED = 1, +}; +enum ddr3_mr2_asr { + DDR3_MR2_ASR_MANUAL = 0, + DDR3_MR2_ASR_AUTO = 1, +}; + +mrs_cmd_t ddr3_get_mr2(enum ddr3_mr2_rttwr rtt_wr, + enum ddr3_mr2_srt_range extended_temp, + enum ddr3_mr2_asr self_refresh, u8 cas_cwl); + +mrs_cmd_t ddr3_get_mr3(char dataflow_from_mpr); +mrs_cmd_t ddr3_mrs_mirror_pins(mrs_cmd_t cmd); + #endif /* DEVICE_DRAM_DDR3_H */

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coreboot-gerrit June 2013