coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 9c50e6a Intel BD82x6x: LPC: Unify I/O APIC setup
by gerrit＠coreboot.org 03 Jun '13

03 Jun '13

the following patch was just integrated into master: commit 9c50e6a4a071a03c4dedd8eb87022644e9ee74c3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri May 3 12:23:39 2013 +0200 Intel BD82x6x: LPC: Unify I/O APIC setup Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3183 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/3183 for details. -gerrit

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Patch merged into coreboot/master: 42409e8 northbridge/amd/amdmct: Use `static const` instead of `const static`
by gerrit＠coreboot.org 03 Jun '13

03 Jun '13

the following patch was just integrated into master: commit 42409e87322e974e81db9e0ac8b454e205fe8d3b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat May 4 18:07:13 2013 +0200 northbridge/amd/amdmct: Use `static const` instead of `const static` From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. The following command was used to make the change. $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/' As asked by Bruce Griffith, the changes in `src/vendorcode` were reverted as that is what AMD prefers. The same change was done already for AMD Persimmon in the following commit. commit 824e192809e021b3cdee947a44b3a18d276bdb35 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` Reviewed-on: http://review.coreboot.org/2474 Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3197 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/3197 for details. -gerrit

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New patch to review for coreboot: 1078f10 Intel Atom cpu support to msrtool
by Olivier Langlois 03 Jun '13

03 Jun '13

Olivier Langlois (olivier(a)olivierlanglois.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3351 -gerrit commit 1078f105681158bde3acc63c0e9013675b861b5a Author: Olivier Langlois <olivier(a)olivierlanglois.net> Date: Mon Jun 3 01:30:25 2013 -0400 Intel Atom cpu support to msrtool Added support for Intel Atom cpu to msrtool Fixed a cut&paste error in nehalem msr bits definition It has been tested with a N455 cpu and msrtool output can be review at: http://www.trillion01.com/coreboot/msrtool_atom.txt Change-Id: I0ecf455b559185e2d16fa1a655bf021efc2ef537 Signed-off-by: Olivier Langlois <olivier(a)olivierlanglois.net> --- util/msrtool/Makefile.in | 2 +- util/msrtool/intel_atom.c | 1148 ++++++++++++++++++++++++++++++++++++++++++ util/msrtool/intel_nehalem.c | 2 +- util/msrtool/msrtool.c | 1 + util/msrtool/msrtool.h | 4 + 5 files changed, 1155 insertions(+), 2 deletions(-) diff --git a/util/msrtool/Makefile.in b/util/msrtool/Makefile.in index 89fe6ca..f876da8 100644 --- a/util/msrtool/Makefile.in +++ b/util/msrtool/Makefile.in @@ -26,7 +26,7 @@ PREFIX = @PREFIX@ CFLAGS = @CFLAGS@ -fno-pic LDFLAGS = @LDFLAGS@ -TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o +TARGETS = geodegx2.o geodelx.o cs5536.o k8.o intel_pentium3_early.o intel_pentium3.o intel_pentium4_early.o intel_pentium4_later.o intel_core1.o intel_core2_early.o intel_core2_later.o intel_nehalem.o intel_atom.o SYSTEMS = linux.o darwin.o freebsd.o OBJS = $(PROGRAM).o msrutils.o sys.o $(SYSTEMS) $(TARGETS) diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c new file mode 100644 index 0000000..b53da6a --- /dev/null +++ b/util/msrtool/intel_atom.c @@ -0,0 +1,1148 @@ +/* + * This file is part of msrtool. + * + * Copyright (C) 2013 Olivier Langlois <olivier(a)olivierlanglois.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "msrtool.h" + +int intel_atom_probe(const struct targetdef *target, const struct cpuid_t *id) { + return (0x6 == id->family) && + (0x1c == id->model); +} + +const struct msrdef intel_atom_msrs[] = { + {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ + Machine-Check Exception Address", { + { BITS_EOT } + }}, + {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ + Machine-Check Exception Type", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { + { BITS_EOT } + }}, + {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + { BITS_EOT } + }}, + {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", { + { BITS_EOT } + }}, + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { + { BITS_EOT } + }}, + {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + { BITS_EOT } + }}, + {0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { + { BITS_EOT } + }}, + {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + { 63, 19, RESERVED }, + { 44, 5, "Maximum Bus Ratio", "R/O", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 39, 24, RESERVED }, + { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + { BITS_EOT } + }}, + {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { + { BITS_EOT } + }}, + {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { + { BITS_EOT } + }}, + {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { + { BITS_EOT } + }}, + {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { + { BITS_EOT } + }}, + {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { + { BITS_EOT } + }}, + {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { + { BITS_EOT } + }}, + {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { + { BITS_EOT } + }}, + {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { + { BITS_EOT } + }}, + {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { + { BITS_EOT } + }}, + {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { + { BITS_EOT } + }}, + {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { + { BITS_EOT } + }}, + {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { + { BITS_EOT } + }}, + {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { + { BITS_EOT } + }}, + {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { + { BITS_EOT } + }}, +#if 0 + {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { + { BITS_EOT } + }}, + {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { + { BITS_EOT } + }}, +#endif + {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + { BITS_EOT } + }}, + {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + { BITS_EOT } + }}, + {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + { BITS_EOT } + }}, + {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + { BITS_EOT } + }}, + {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + { BITS_EOT } + }}, + {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + { BITS_EOT } + }}, + {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + { BITS_EOT } + }}, + {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + { BITS_EOT } + }}, + {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + { BITS_EOT } + }}, + {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + { BITS_EOT } + }}, + {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + { BITS_EOT } + }}, + /* if CPUID.01H: ECX[15] = 1 */ + {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { + /* Additional info available at Section 17.4.1 of + * Intel 64 and IA-32 Architecures Software Developer's + * Manual, Volume 3. + */ + { 63, 50, RESERVED }, + { 13, 1, "Counter width", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Full width of counter writable via IA32_A_PMCx" }, + { BITVAL_EOT } + }}, + { 12, 1, "SMM_FREEZE", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Freeze while SMM is supported" }, + { BITVAL_EOT } + }}, + { 11, 4, "PEBS_REC_FORMAT", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 5, 6, "LBR Format", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { + { BITS_EOT } + }}, + {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { + { BITS_EOT } + }}, + {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { + { BITS_EOT } + }}, + {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + { BITS_EOT } + }}, + {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + { BITS_EOT } + }}, + {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + { BITS_EOT } + }}, + {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + { BITS_EOT } + }}, + {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + { BITS_EOT } + }}, + {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + { BITS_EOT } + }}, + {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + { BITS_EOT } + }}, + {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + { BITS_EOT } + }}, + {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + { BITS_EOT } + }}, + {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + { BITS_EOT } + }}, + {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + { BITS_EOT } + }}, + +/* ========================================================================== + * Per core MSRs + * ========================================================================== + */ + + {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { + { BITS_EOT } + }}, + {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { + { BITS_EOT } + }}, + {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", { + /* In Intel's manual there is MAXPHYWID, + * which determine index of highest bit of + * APIC Base itself, so marking it as + * 'RESERVED'. + */ + { 63, 52, RESERVED }, + { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 10, 1, "x2APIC mode", "R/W", PRESENT_BIN, { + { MSR1(0), "x2APIC mode is disabled" }, + { MSR1(1), "x2APIC mode is enabled" }, + { BITVAL_EOT } + }}, + { 9, 1, RESERVED }, + { 8, 1, "BSP Flag", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 7, 8, RESERVED }, + { BITS_EOT } + }}, + /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */ + {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", + "Control features in Intel 64Processor", { + { 63, 48, RESERVED }, + /* if CPUID.01H: ECX[6] = 1 */ + { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, { + { MSR1(0), "SENTER leaf functions are disabled" }, + { MSR1(1), "SENTER leaf functions are enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.01H: ECX[6] = 1 */ + { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 7, 5, RESERVED }, + /* if CPUID.01H: ECX[5 or 6] = 1 */ + { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, { + /* This bit enables VMX for system executive + * that do not require SMX. + */ + { MSR1(0), "VMX outside of SMX operation disabled" }, + { MSR1(1), "VMX outside of SMX operation enabled" }, + { BITVAL_EOT } + }}, + { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { + /* This bit enables a system executive to use + * VMX in conjuction with SMX to support Intel + * Trusted Execution Technology. + */ + { MSR1(0), "VMX inside of SMX operation disabled" }, + { MSR1(1), "VMX inside of SMX operation enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.01H: ECX[5 or 6] = 1 */ + { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, { + /* Once the Lock bit is set, the contents + * of this register cannot be modified. + * Therefore the lock bit must be set after + * configuring support for Intel Virtualization + * Technology and prior transferring control + * to an Option ROM or bootloader. Hence, once + * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR + * contents are preserved across RESET when + * PWRGOOD it not deasserted. + */ + { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" }, + { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { + { BITS_EOT } + }}, + {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { + { BITS_EOT } + }}, + {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { + { BITS_EOT } + }}, + {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { + { BITS_EOT } + }}, + {0x44, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "", { + { BITS_EOT } + }}, + {0x45, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_FROM_IP", "", { + { BITS_EOT } + }}, + {0x46, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "", { + { BITS_EOT } + }}, + {0x47, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_FROM_IP", "", { + { BITS_EOT } + }}, + {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { + { BITS_EOT } + }}, + {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { + { BITS_EOT } + }}, + {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { + { BITS_EOT } + }}, + {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { + { BITS_EOT } + }}, + {0x64, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_LIP", "", { + { BITS_EOT } + }}, + {0x65, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_TO_LIP", "", { + { BITS_EOT } + }}, + {0x66, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_LIP", "", { + { BITS_EOT } + }}, + {0x67, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_TO_LIP", "", { + { BITS_EOT } + }}, + {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", + "BIOS Update Signature ID (RO)", { + { BITS_EOT } + }}, + {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", + "Performance counter register", { + { BITS_EOT } + }}, + {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", + "Performance counter register", { + { BITS_EOT } + }}, + {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + { BITS_EOT } + }}, + {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + { BITS_EOT } + }}, + {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + { BITS_EOT } + }}, + {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + { BITS_EOT } + }}, + {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + { BITS_EOT } + }}, + {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + { 63, 61, RESERVED }, + { 2, 1, "MCIP", "R/W", PRESENT_BIN, { + /* When set, bit indicates that a machine check has been + * generated. If a second machine check is detected while + * this bit is still set, the processor enters a shutdown state. + * Software should write this bit to 0 after processing + * a machine check exception. + */ + { MSR1(0), "Nothing" }, + { MSR1(1), "Machine check has been generated" }, + { BITVAL_EOT } + }}, + { 1, 1, "EPIV", "R/W", PRESENT_BIN, { + /* When set, bit indicates that the instruction addressed + * by the instruction pointer pushed on the stack (when + * the machine check was generated) is directly associated + * with the error + */ + { MSR1(0), "Nothing" }, + { MSR1(1), "Instruction addressed directly associated with the error" }, + { BITVAL_EOT } + }}, + { 0, 1, "RIPV", "R/W", PRESENT_BIN, { + /* When set, bit indicates that the instruction addressed + * by the instruction pointer pushed on the stack (when + * the machine check was generated) can be used to restart + * the program. If cleared, the program cannot be reliably restarted + */ + { MSR1(0), "Program cannot be reliably restarted" }, + { MSR1(1), "Instruction addressed can be used to restart the program" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[15:8] > 0 */ + {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", + "Performance Event Select Register 0", { + { 63, 32, RESERVED }, + { 31, 8, "CMASK", "R/W", PRESENT_HEX, { + /* When CMASK is not zero, the corresponding performance + * counter 0 increments each cycle if the event count + * is greater than or equal to the CMASK. + */ + { BITVAL_EOT } + }}, + { 23, 1, "INV", "R/W", PRESENT_BIN, { + { MSR1(0), "CMASK using as is" }, + { MSR1(1), "CMASK inerting" }, + { BITVAL_EOT } + }}, + { 22, 1, "EN", "R/W", PRESENT_BIN, { + { MSR1(0), "No commence counting" }, + { MSR1(1), "Commence counting" }, + { BITVAL_EOT } + }}, + { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "INT", "R/W", PRESENT_BIN, { + { MSR1(0), "Interrupt on counter overflow is disabled" }, + { MSR1(1), "Interrupt on counter overflow is enabled" }, + { BITVAL_EOT } + }}, + { 19, 1, "PC", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled pin control" }, + { MSR1(1), "Enabled pin control" }, + { BITVAL_EOT } + }}, + { 18, 1, "Edge", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled edge detection" }, + { MSR1(1), "Enabled edge detection" }, + { BITVAL_EOT } + }}, + { 17, 1, "OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is ring 0" }, + { BITVAL_EOT } + }}, + { 16, 1, "USR", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is not ring 0" }, + { BITVAL_EOT } + }}, + { 15, 8, "UMask", "R/W", PRESENT_HEX, { + /* Qualifies the microarchitectural condition + * to detect on the selected event logic. */ + { BITVAL_EOT } + }}, + { 7, 8, "Event Select", "R/W", PRESENT_HEX, { + /* Selects a performance event logic unit. */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[15:8] > 0 */ + {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", + "Performance Event Select Register 1", { + { 63, 32, RESERVED }, + { 31, 8, "CMASK", "R/W", PRESENT_HEX, { + /* When CMASK is not zero, the corresponding performance + * counter 1 increments each cycle if the event count + * is greater than or equal to the CMASK. + */ + { BITVAL_EOT } + }}, + { 23, 1, "INV", "R/W", PRESENT_BIN, { + { MSR1(0), "CMASK using as is" }, + { MSR1(1), "CMASK inerting" }, + { BITVAL_EOT } + }}, + { 22, 1, "EN", "R/W", PRESENT_BIN, { + { MSR1(0), "No commence counting" }, + { MSR1(1), "Commence counting" }, + { BITVAL_EOT } + }}, + { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 20, 1, "INT", "R/W", PRESENT_BIN, { + { MSR1(0), "Interrupt on counter overflow is disabled" }, + { MSR1(1), "Interrupt on counter overflow is enabled" }, + { BITVAL_EOT } + }}, + { 19, 1, "PC", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled pin control" }, + { MSR1(1), "Enabled pin control" }, + { BITVAL_EOT } + }}, + { 18, 1, "Edge", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled edge detection" }, + { MSR1(1), "Enabled edge detection" }, + { BITVAL_EOT } + }}, + { 17, 1, "OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is ring 0" }, + { BITVAL_EOT } + }}, + { 16, 1, "USR", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Counts while in privilege level is not ring 0" }, + { BITVAL_EOT } + }}, + { 15, 8, "UMask", "R/W", PRESENT_HEX, { + /* Qualifies the microarchitectural condition + * to detect on the selected event logic. */ + { BITVAL_EOT } + }}, + { 7, 8, "Event Select", "R/W", PRESENT_HEX, { + /* Selects a performance event logic unit. */ + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + { BITS_EOT } + }}, + {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", + "Clock Modulation", { + { 63, 59, RESERVED }, + { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { + { MSR1(0), "On demand Clock Modulation is disabled" }, + { MSR1(1), "On demand Clock Modulation is enabled" }, + { BITVAL_EOT } + }}, + { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 0, 1, RESERVED }, + { BITS_EOT } + }}, + {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", + "Thermal Interrupt Control", { + { BITS_EOT } + }}, + {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", + "Thermal Monitor Status", { + { BITS_EOT } + }}, + {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", + "Enable miscellaneous processor features", { + { 63, 25, RESERVED }, + /* Note: [38] bit using for whole package, + * while some other bits can be Core or Thread + * specific. + */ + { 38, 1, "Turbo Mode", "R/W", PRESENT_BIN, { + /* When set to a 0 on processors that support IDA, + * CPUID.06H: EAX[1] reports the processor's + * support of turbo mode is enabled. + */ + { MSR1(0), "Turbo Mode enabled" }, + /* When set 1 on processors that support Intel Turbo Boost + * technology, the turbo mode feature is disabled and + * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). + */ + { MSR1(1), "Turbo Mode disabled" }, + { BITVAL_EOT } + /* Note: the power-on default value is used by BIOS to detect + * hardware support of turbo mode. If power-on default value is 1, + * turbo mode is available in the processor. If power-on default + * value is 0, turbo mode not available. + */ + }}, + { 37, 3, RESERVED }, + { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 33, 10, RESERVED }, + { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 21, 3, RESERVED }, + { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* Note: [16] bit using for whole package, + * while some other bits can be Core or Thread + * specific. + */ + { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W", + PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 15, 3, RESERVED }, + { 12, 1, "Precise Event Based Sampling Unavailable", "R/O", + PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 10, 3, RESERVED }, + { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 6, 3, RESERVED }, + { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W" + , PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 2, 2, RESERVED }, + { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1c9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LASTBRANCH_TOS", + "Last Branch Record Stack TOS", { + /* Contains an index (bits 0-3) that points to the MSR containing + * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680). + */ + { BITS_EOT } + }}, + {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", + "Debug/Trace/Profile Resource Control", { + /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */ + { 63, 49, RESERVED }, + /* Only if IA32_PERF_CAPABILITIES[12] = 1 */ + { 14, 1, "FREEZE_WHILE_SMM", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Freeze perfmon and trace messages while in SMM" }, + { BITVAL_EOT } + }}, + { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Logical processor can receive and generate PMI \ + on behalf of the uncore" }, + { BITVAL_EOT } + }}, + /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ + { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Each ENABLE bit of the global counter control MSR \ + are frozen (address 0x3bf) on PMI request" }, + { BITVAL_EOT } + }}, + /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ + { 11, 1, "FREEZE_LBRS_ON_PMI", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "LBR stack is frozen on PMI request" }, + { BITVAL_EOT } + }}, + { 10, 1, "BTS_OFF_USR", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "BTS or BTM is skipped if CPL > 0" }, + { BITVAL_EOT } + }}, + { 9, 1, "BTS_OFF_OS", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "BTS or BTM is skipped if CPL = 0" }, + { BITVAL_EOT } + }}, + { 8, 1, "BTINT", "R/O", PRESENT_BIN, { + { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, + { MSR1(1), "An interrupt is generated by the BTS facility \ + when the BTS buffer is full" }, + { BITVAL_EOT } + }}, + { 7, 1, "BTS", "R/O", PRESENT_BIN, { + { MSR1(0), "Logging of BTMs (branch trace messages) \ + in BTS buffer is disabled" }, + { MSR1(1), "Logging of BTMs (branch trace messages) \ + in BTS buffer is enabled" }, + { BITVAL_EOT } + }}, + { 6, 1, "TR", "R/O", PRESENT_BIN, { + { MSR1(0), "Branch trace messages are disabled" }, + { MSR1(1), "Branch trace messages are enabled" }, + { BITVAL_EOT } + }}, + { 5, 4, RESERVED }, + { 1, 1, "BTF", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ + branches instead of single-step on instructions" }, + { BITVAL_EOT } + }}, + { 0, 1, "LBR", "R/O", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Enabled recording a running trace of the most \ + recent branches taken by the processor in the LBR stack" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x1dd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_FROM_LIP", + "Last Exception Record From Linear IP", { + /* Contains a pointer to the last branch instruction + * that the processor executed prior to the last exception + * that was generated or the last interrupt that was handled. + */ + { BITS_EOT } + }}, + {0x1de, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_TO_LIP", + "Last Exception Record To Linear IP", { + /* This area contains a pointer to the target of the + * last branch instruction that the processor executed + * prior to the last exception that was generated or + * the last interrupt that was handled + */ + { BITS_EOT } + }}, + {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { + { 63, 5, RESERVED }, + { 58, 3, "PA7", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 55, 5, RESERVED }, + { 40, 3, "PA6", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 47, 5, RESERVED }, + { 42, 3, "PA5", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 39, 5, RESERVED }, + { 34, 3, "PA4", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 31, 5, RESERVED }, + { 26, 3, "PA3", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 23, 5, RESERVED }, + { 18, 3, "PA2", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 15, 5, RESERVED }, + { 10, 3, "PA1", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 7, 5, RESERVED }, + { 2, 3, "PA0", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EDX[4:0] > 0 */ + {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ + Performance Counter Register 0: Counts Instr_Retired.Any", { + /* Also known as MSR_PERF_FIXED_CTR0 */ + { BITS_EOT } + }}, + /* if CPUID.0AH: EDX[4:0] > 1 */ + {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ + Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { + /* Also known as MSR_PERF_FIXED_CTR1 */ + { BITS_EOT } + }}, + /* if CPUID.0AH: EDX[4:0] > 2 */ + {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ + Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { + /* Also known as MSR_PERF_FIXED_CTR2 */ + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1*/ + {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", + "Fixed-Function-Counter Control Register", { + /* Also known as MSR_PERF_FIXED_CTR_CTRL. + * Counter increments while the results of ANDing respective enable bit + * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits + * in this MSR is true. */ + { 63, 52, RESERVED }, + { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "PMI when fixed counter 2 overflows is enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.0AH EAX[7:0] > 2 */ + { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { + { MSR1(0), "Counter only increments the associated event \ + conditions occuring in the logical processor which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions \ + occuring across all logical processors sharing a processor core" }, + { BITVAL_EOT } + }}, + { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" }, + { BITVAL_EOT } + }}, + { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" }, + { BITVAL_EOT } + }}, + { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "PMI when fixed counter 1 overflows is enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 2 */ + { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { + { MSR1(0), "Counter only increments the associated event \ + conditions occuring in the logical processor which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions \ + occuring across all logical processors sharing a processor core" }, + { BITVAL_EOT } + }}, + { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" }, + { BITVAL_EOT } + }}, + { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" }, + { BITVAL_EOT } + }}, + { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "PMI when fixed counter 0 overflows is enabled" }, + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 2 */ + { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { + { MSR1(0), "Counter only increments the associated event \ + conditions occuring in the logical processor which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions \ + occuring across all logical processors sharing a processor core" }, + { BITVAL_EOT } + }}, + { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" }, + { BITVAL_EOT } + }}, + { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, { + { MSR1(0), "Nothing" }, + { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", + "Global Performance Counter Status", { + /* Also known as MSR_PERF_GLOBAL_STATUS */ + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 63, 1, "CondChg: Status bits of this register has changed", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 2 */ + { 61, 1, "Ovf_Uncore: Uncore counter overflow status", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 60, 26, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 31, 28, RESERVED }, + /* presented only in 06_2EH Nehalem model */ + { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* presented only in 06_2EH Nehalem model */ + { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", + "Global Performance Counter Control", { + /* Counter increments while the result of ANDing respective + * enable bit in this MSR with corresponding OS or USR bits + * in general-purpose or fixed counter control MSR is true. + */ + { 63, 29, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 31, 30, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", + "Global Performance Counter Overflow Control", { + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* Presented only in 06_2EH Nehalem model */ + { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 60, 26, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 1 */ + { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 31, 30, RESERVED }, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + /* if CPUID.0AH: EAX[7:0] > 0 */ + { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures + * Software Developer's Manual, Volume 3, + * "Precise Event Based Sampling (PEBS)". + */ + {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { + { 63, 28, RESERVED }, + { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 31, 28, RESERVED }, + { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, { + { MSR1(0), "Disabled" }, + { MSR1(1), "Enabled" }, + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, +#if 0 + {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", + "Reporting Register of Basic VMX Capabilities", { + /* Additional info available at + * Appendix A.1, "Basic VMX Information" */ + { 63, 10, RESERVED }, + { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { 49, 1, "Support of dual-treatment of system-management functions", + "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, { + { BITVAL_EOT } + }}, + { 47, 3, RESERVED }, + { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, { + { BITVAL_EOT } + }}, + { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", + "Capability Reporting Register of \ + Pin-based VM-execution Controls", { + /* Additional info available at Appendix A.3, + * "VM-Execution Controls" */ + { BITS_EOT } + }}, + {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", + "Capability Reporting Register of \ + Primary Processor-based VM-execution Controls", { + /* Additional info available at Appendix A.3, + * "VM-Execution Controls" */ + { BITS_EOT } + }}, + {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", + "Capability Reporting Register of VM-exit Controls", { + /* Additional info available at Appendix A.4, + * "VM-Exit Controls" */ + { BITS_EOT } + }}, + {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", + "Capability Reporting Register of VM-entry Controls", { + /* Additional info available at Appendix A.5, + * "VM-Entry Controls" */ + { BITS_EOT } + }}, + {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", + "Reporting Register of Miscellaneous VMX Capabilities", { + /* Additional info available at Appendix A.6, + * "Miscellaneous Data" */ + { BITS_EOT } + }}, + {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", + "Capability Reporting Register of CR0 Bits Fixed to 0", { + /* Additional info available at Appendix A.7, + * "VMX-Fixed Bits in CR0" */ + { BITS_EOT } + }}, + {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", + "Capability Reporting Register of CR0 Bits Fixed to 1", { + /* Additional info available at Appendix A.7, + * "VMX-Fixed Bits in CR0" */ + { BITS_EOT } + }}, + {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", + "Capability Reporting Register of CR4 Bits Fixed to 0", { + /* Additional info available at Appendix A.8, + * "VMX-Fixed Bits in CR4" */ + { BITS_EOT } + }}, + {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", + "Capability Reporting Register of CR4 Bits Fixed to 1", { + /* Additional info available at Appendix A.8, + * "VMX-Fixed Bits in CR4" */ + { BITS_EOT } + }}, + {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", + "Capability Reporting Register of VMCS Field Enumeration", { + /* Additional info available at Appendix A.9, + * "VMCS Enumeration" */ + { BITS_EOT } + }}, + {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", + "Capability Reporting Register of Secondary \ + Processor-based VM-execution Controls", { + /* Additional info available at Appendix A.3, + * "VM-Execution Controls" */ + { BITS_EOT } + }}, +#endif + {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { + /* Additional info available at Section 18.10.4 of Intel 64 + * and IA-32 Architectures Software Developer's Manual, + * "Debug Store (DS) Mechanism". + */ + { 63, 32, RESERVED }, // reserved if not in IA-32e mode + { 31, 32, "Linear address of DS buffer management area", + "R/W", PRESENT_HEX, { + { BITVAL_EOT } + }}, + { BITS_EOT } + }}, + { MSR_EOT } +}; + diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index f71c318..3c2cbf8 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -311,7 +311,7 @@ const struct msrdef intel_nehalem_msrs[] = { * Trusted Execution Technology. */ { MSR1(0), "VMX inside of SMX operation disabled" }, - { MSR1(1), "VMX outside of SMX operation enabled" }, + { MSR1(1), "VMX inside of SMX operation enabled" }, { BITVAL_EOT } }}, /* if CPUID.01H: ECX[5 or 6] = 1 */ diff --git a/util/msrtool/msrtool.c b/util/msrtool/msrtool.c index 3e1a555..5329eb1 100644 --- a/util/msrtool/msrtool.c +++ b/util/msrtool/msrtool.c @@ -52,6 +52,7 @@ static struct targetdef alltargets[] = { { "intel_pentium4_early", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4 processors", intel_pentium4_early_probe, intel_pentium4_early_msrs }, { "intel_pentium4_later", "Intel Xeon Processor, Intel Xeon Processor MP, Intel Pentium 4, Pentium D processors", intel_pentium4_later_probe, intel_pentium4_later_msrs }, { "intel_nehalem", "Intel Core i5, i7 Processors, Intel Xeon Processor 3400, 3500, 5500, based on Nehalem architecture", intel_nehalem_probe, intel_nehalem_msrs }, + { "intel_atom", "Intel Atom Processors, N450", intel_atom_probe, intel_atom_msrs }, { TARGET_EOT } }; diff --git a/util/msrtool/msrtool.h b/util/msrtool/msrtool.h index 39b1cac..e99921a 100644 --- a/util/msrtool/msrtool.h +++ b/util/msrtool/msrtool.h @@ -250,4 +250,8 @@ extern const struct msrdef intel_pentium4_later_msrs[]; extern int intel_nehalem_probe(const struct targetdef *t, const struct cpuid_t *id); extern const struct msrdef intel_nehalem_msrs[]; +/* intel_atom.c */ +extern int intel_atom_probe(const struct targetdef *t, const struct cpuid_t *id); +extern const struct msrdef intel_atom_msrs[]; + #endif /* MSRTOOL_H */

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Patch set updated for coreboot: 2aa0565 am335x: Add struct `am335x_uart` for uart registers
by David Hendricks 03 Jun '13

03 Jun '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3319 -gerrit commit 2aa0565ea5697a66556c3fa120304b86535fb0f3 Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon May 27 10:32:57 2013 -0700 am335x: Add struct `am335x_uart` for uart registers Add a struct for referencing UART registers. The layout is quite strange on this chip, as the entire register space can take on three different meanings depending on the line control settings (in the LCR register) And to make things more confusing, some offsets reference different registers depending on if a read or a write operation is used. Change-Id: Ie62af9c0e0edafd01b81686a0fe5c5c1d4fa06c4 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/ti/am335x/uart.h | 157 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 151 insertions(+), 6 deletions(-) diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index b642e9c..356f12b 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -1,8 +1,5 @@ /* * (C) Copyright 2012 The ChromiumOS Authors - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * Heungjun Kim <riverful.kim(a)samsung.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -23,8 +20,8 @@ * from u-boot. */ -#ifndef __AM335X_UART_H_ -#define __AM335X_UART_H +#ifndef AM335X_UART_H +#define AM335X_UART_H #define AM335X_UART0_BASE 0x44e09000 #define AM335X_UART1_BASE 0x48020000 @@ -33,4 +30,152 @@ #define AM335X_UART4_BASE 0x481A8000 #define AM335X_UART5_BASE 0x481AA000 -#endif +/* + * The meaning of some AM335x UART register offsets changes depending on read + * or write operation as well as various modes. See section 19.3.7.1.2 for + * register access submode description and 19.5.1 for register descriptions. + */ +struct am335x_uart { + union { + /* operational mode */ + uint16_t rhr; /* receiver holding (read) */ + uint16_t thr; /* transmit holding (write) */ + /* config mode A and B */ + uint16_t dll; /* divisor latches low */ + }; + uint8_t rsvd_0x02[2]; + union { + /* operational mode */ + uint16_t ier; /* interrupt enable */ + /* config mode A and B */ + uint16_t dlh; /* divisor latches high */ + }; + uint8_t rsvd_0x06[2]; + union { + /* operational mode, config mode A */ + uint16_t iir; /* interrupt ID (read) */ + uint16_t fcr; /* FIFO control (write) */ + /* config mode B */ + uint16_t efr; + }; + uint8_t rsvd_0x0a[2]; + uint16_t lcr; /* line control */ + uint8_t rsvd_0x0e[2]; + + /* 0x10 */ + union { + /* operational mode, config mode A */ + uint16_t mcr; /* modem control */ + /* config mode B */ + uint16_t xon1; /* XON1 character (UART mode) */ + uint16_t addr1; /* address 1 (IrDA mode) */ + }; + uint8_t rsvd_0x12[2]; + union { + /* operational mode, config mode A */ + uint16_t lsr; /* line status, read-only */ + /* config mode B */ + uint16_t xon2; /* XON2 character (UART mode) */ + uint16_t addr2; /* IrDA mode (IrDA mode) */ + }; + uint8_t rsvd_0x16[2]; + + /* + * Bytes 0x18 and 0x1c depend on submode TCR_TLR. When EFR[4] = 1 and + * MCR[6] = 1, transmission control register and trigger level register + * will be read/written. If not, the modem status register and the + * scratchpad register will be affected by read/write. + */ + union { + /* operational mode and config mode A */ + uint16_t msr; /* modem status */ + /* config mode B */ + uint16_t xoff1; /* xoff1 character (UART MODE) */ + /* submode TCR_TLR */ + uint16_t tcr; /* transmission control */ + }; + uint8_t rsvd_0x1a[2]; + union { + uint16_t spr; /* scratchpad */ + /* config mode B */ + uint16_t xoff2; /* xoff2 character (UART mode) */ + /* submode TCR_TLR */ + uint16_t tlr; /* trigger level */ + }; + uint8_t rsvd_0x1e[2]; + + /* 0x20 */ + uint16_t mdr1; /* mode definition 1 */ + uint8_t rsvd_0x22[2]; + uint16_t mdr2; /* mode definition 2 */ + uint8_t rsvd_0x26[2]; + union { + uint16_t sflsr; /* status FIFO line status reg (read) */ + uint16_t txfll; /* transmit frame length low (write) */ + }; + uint8_t rsvd_0x2a[2]; + union { + uint16_t resume; /* resume halted operation (read) */ + uint16_t txflh; /* transmit frame length high (write) */ + }; + uint8_t rsvd_0x2e[2]; + + /* 0x30 */ + union { + uint16_t sfregl; /* status FIFO low (read) */ + uint16_t rxfll; /* received frame length low (write) */ + }; + uint8_t rsvd_0x32[2]; + union { + uint16_t sfregh; /* status FIFO high (read) */ + uint16_t rxflh; /* received frame length high (write) */ + }; + uint8_t rsvd_0x36[2]; + uint16_t blr; /* BOF control */ + uint8_t rsvd_0x3a[2]; + uint16_t acreg; /* auxilliary control */ + uint8_t rsvd_0x3e[2]; + + /* 0x40 */ + uint16_t scr; /* supplementary control */ + uint8_t rsvd_0x42[2]; + uint16_t ssr; /* supplementary status */ + uint8_t rsvd_0x46[2]; + + uint16_t eblr; /* BOF length (operatoinal mode only) */ + uint8_t rsvd_0x4a[6]; + + /* 0x50 */ + uint16_t mvr; /* module version (read-only) */ + uint8_t rsvd_0x52[2]; + uint16_t sysc; /* system config */ + uint8_t rsvd_0x56[2]; + uint16_t syss; /* system status (read-only) */ + uint8_t rsvd_0x5a[2]; + uint16_t wer; /* wake-up enable */ + uint8_t rsvd_0x5e[2]; + + /* 0x60 */ + uint16_t cfps; /* carrier prescale frequency */ + uint8_t rsvd_0x62[2]; + uint16_t rxfifo_lvl; /* received FIFO level */ + uint8_t rsvd_0x66[2]; + uint16_t txfifo_lvl; /* transmit FIFO level */ + uint8_t rsvd_0x6a[2]; + uint16_t ier2; /* RX/TX FIFO empty interrupt enable */ + uint8_t rsvd_0x6e[2]; + + /* 0x70 */ + uint16_t isr2; /* RX/TX FIFO empty interrupt status */ + uint8_t rsvd_0x72[2]; + uint16_t freq_sel; /* frequency select */ + uint8_t rsvd_0x76[10]; + + /* 0x80 */ + uint16_t mdr3; /* mode definition register 3 */ + uint8_t rsvd_0x82[2]; + uint16_t txdma; /* TX DMA threshold */ + +} __attribute__((packed)); + +#endif /* AM335X_UART_H */

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Patch merged into coreboot/master: 3aa5816 am335x: Clean up/fix some settings in the am335x Kconfig.
by gerrit＠coreboot.org 03 Jun '13

03 Jun '13

the following patch was just integrated into master: commit 3aa58162e1be25ad77800879e73a087ddbdc660c Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed May 29 16:42:20 2013 +0200 am335x: Clean up/fix some settings in the am335x Kconfig. Some settings in the am335x Kconfig weren't actually used for anything, some where place holders, and some where left over from another CPU. The memory addresses are in the internal RAM in the SOC as described in the reference manual. The stack is put where the internal ROM had its stack, and the bootblock is put at the bottom of that region as the manual suggests. The ROM stage offset is set to 10K which is a bit bigger than the ~7.5K the bootblock currently takes up. Change-Id: I1a117d789a791d7e3db1118823f8216b3361433c Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3327 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/3327 for details. -gerrit

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Patch set updated for coreboot: 4516ce0 lenovo/t60 lenovo/x60: Override SMBIOS vendor name to all upper case
by Paul Menzel 03 Jun '13

03 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1557 -gerrit commit 4516ce0475aa255d33d40efe32b946a87a407cd7 Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:25:18 2012 +0200 lenovo/t60 lenovo/x60: Override SMBIOS vendor name to all upper case Allow the Linux thinkpad_acpi.ko module to understand that a ThinkPad is a ThinkPad also when it runs coreboot. Change-Id: I85c948b9a772ac878708d72012e522e87c49c2b2 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/mainboard/lenovo/t60/Kconfig | 4 ++++ src/mainboard/lenovo/x60/Kconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 952004b..306e7f3 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -39,6 +39,10 @@ config MAINBOARD_PART_NUMBER string default "ThinkPad T60 / T60p" +config MAINBOARD_SMBIOS_VENDOR + string + default "LENOVO" + config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1431a2f..09e728c 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -42,6 +42,10 @@ config MAINBOARD_PART_NUMBER string default "ThinkPad X60 / X60s" +config MAINBOARD_SMBIOS_VENDOR + string + default "LENOVO" + config MMCONF_BASE_ADDRESS hex default 0xf0000000

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Patch set updated for coreboot: 4847818 Allow mainboard vendor name and part number override in SMBIOS tables
by Peter Stuge 03 Jun '13

03 Jun '13

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1556 -gerrit commit 48478185f14bd138653c32e8b78e6eb8f72298e7 Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:18:13 2012 +0200 Allow mainboard vendor name and part number override in SMBIOS tables Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/arch/x86/boot/smbios.c | 6 +++--- src/mainboard/Kconfig | 13 +++++++++++++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 308336a..807cfad 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -192,8 +192,8 @@ static int smbios_write_type1(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); - t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_VENDOR); + t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_PART_NUMBER); t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); len = t->length + smbios_string_table_len(t->eos); @@ -210,7 +210,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_ENCLOSURE; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_VENDOR); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 1e5d4bd..d8ca2f4 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -344,4 +344,17 @@ config MAINBOARD_VERSION default "1.0" help Define the used version number which will be used by SMBIOS tables. + +config MAINBOARD_SMBIOS_VENDOR + string "BIOS table vendor string" + default MAINBOARD_VENDOR + help + Override the default mainboard vendor string used by SMBIOS tables. + +config MAINBOARD_SMBIOS_PART_NUMBER + string "BIOS table part number string" + default MAINBOARD_PART_NUMBER + help + Override the default mainboard part number string used by SMBIOS tables. + endmenu

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Patch set updated for coreboot: 9cca789 Allow mainboard vendor name and part number override in SMBIOS tables
by Denis Carikli 03 Jun '13

03 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1556 -gerrit commit 9cca7890fd925e93415d96ec99024665058ecea7 Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:18:13 2012 +0200 Allow mainboard vendor name and part number override in SMBIOS tables Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/arch/x86/boot/smbios.c | 6 +++--- src/mainboard/Kconfig | 13 +++++++++++++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 308336a..807cfad 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -192,8 +192,8 @@ static int smbios_write_type1(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); - t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_VENDOR); + t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_PART_NUMBER); t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); len = t->length + smbios_string_table_len(t->eos); @@ -210,7 +210,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_ENCLOSURE; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_VENDOR); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 1e5d4bd..199e164 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -344,4 +344,17 @@ config MAINBOARD_VERSION default "1.0" help Define the used version number which will be used by SMBIOS tables. + +config MAINBOARD_SMBIOS_VENDOR + string "BIOS table vendor string" + default MAINBOARD_VENDOR + help + Override the default mainboard vendor string used by SMBIOS tables. + +config MAINBOARD_SMBIOS_PART_NUMBER + string "BIOS table vendor string" + default MAINBOARD_PART_NUMBER + help + Override the default mainboard part number string used by SMBIOS tables. + endmenu

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Patch set updated for coreboot: ba584ac lenovo/t60 lenovo/x60: Override SMBIOS vendor name to all upper case
by Denis Carikli 03 Jun '13

03 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1557 -gerrit commit ba584ac4d104f00718df4ed1d5ad7fe7d248c06a Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:25:18 2012 +0200 lenovo/t60 lenovo/x60: Override SMBIOS vendor name to all upper case This allows the Linux thinkpad_acpi.ko module understand that a ThinkPad is a ThinkPad also when it runs coreboot. Change-Id: I85c948b9a772ac878708d72012e522e87c49c2b2 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/mainboard/lenovo/t60/Kconfig | 4 ++++ src/mainboard/lenovo/x60/Kconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 952004b..306e7f3 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -39,6 +39,10 @@ config MAINBOARD_PART_NUMBER string default "ThinkPad T60 / T60p" +config MAINBOARD_SMBIOS_VENDOR + string + default "LENOVO" + config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1431a2f..09e728c 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -42,6 +42,10 @@ config MAINBOARD_PART_NUMBER string default "ThinkPad X60 / X60s" +config MAINBOARD_SMBIOS_VENDOR + string + default "LENOVO" + config MMCONF_BASE_ADDRESS hex default 0xf0000000

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Patch set updated for coreboot: 655695a Allow mainboard vendor name and part number override in SMBIOS tables
by Peter Stuge 03 Jun '13

03 Jun '13

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1556 -gerrit commit 655695aeb8f7ff74cc2e2cec0a2bd4851a401ba2 Author: Peter Stuge <peter(a)stuge.se> Date: Thu Oct 4 21:18:13 2012 +0200 Allow mainboard vendor name and part number override in SMBIOS tables Change-Id: I0dfe38b9f6f99b3376f1547412ecc97c2f7aff2b Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/arch/x86/boot/smbios.c | 6 +++--- src/mainboard/Kconfig | 13 +++++++++++++ 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 308336a..807cfad 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -192,8 +192,8 @@ static int smbios_write_type1(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_INFORMATION; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); - t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_VENDOR); + t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_PART_NUMBER); t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); len = t->length + smbios_string_table_len(t->eos); @@ -210,7 +210,7 @@ static int smbios_write_type3(unsigned long *current, int handle) t->type = SMBIOS_SYSTEM_ENCLOSURE; t->handle = handle; t->length = len - 2; - t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR); + t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_SMBIOS_VENDOR); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 3ca21ff..bf29fca 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -341,4 +341,17 @@ config MAINBOARD_VERSION default "1.0" help Define the used version number which will be used by SMBIOS tables. + +config MAINBOARD_SMBIOS_VENDOR + string "BIOS table vendor string" + default MAINBOARD_VENDOR + help + Override the default mainboard vendor string used by SMBIOS tables. + +config MAINBOARD_SMBIOS_PART_NUMBER + string "BIOS table part number string" + default MAINBOARD_PART_NUMBER + help + Override the default mainboard part number string used by SMBIOS tables. + endmenu

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coreboot-gerrit June 2013