coreboot-gerrit March 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: d0d7e7d lynxpoint: Rework ACPI NVS to add new SerialIO variables
by gerrit＠coreboot.org 31 Mar '13

31 Mar '13

the following patch was just integrated into master: commit d0d7e7d7619e469dc936a579a6ce2adee9425ca6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Mar 22 11:05:38 2013 -0700 lynxpoint: Rework ACPI NVS to add new SerialIO variables This reclaims space in ACPI NVS by removing unused fields and adds new fields for SerialIO BARs which will be used to communicate the allocated resources to ACPI. Change-Id: I002bf396cf7b495bc5b7e54b741527e507aff716 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/2969 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Mar 29 23:06:33 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Sun Mar 31 23:46:55 2013, giving +2 See http://review.coreboot.org/2969 for details. -gerrit

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Patch set updated for coreboot: c896acf PDCurses: pdcscrn.c: Use `#ifdef` instead of `#if CONFIG_SPEAKER`
by Paul Menzel 31 Mar '13

31 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2934 -gerrit commit c896acf51810403b6bd37f368659eec95c6128bd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Mar 27 09:50:30 2013 +0100 PDCurses: pdcscrn.c: Use `#ifdef` instead of `#if CONFIG_SPEAKER` Building libpayload with the PDCurses backend the following warning is shown. /src/coreboot/payloads/libpayload(master) $ make clean /src/coreboot/payloads/libpayload(master) $ make […] CC curses/pdcurses-backend/pdcscrn.libcurses.o curses/pdcurses-backend/pdcscrn.c: In function 'PDC_scr_open': curses/pdcurses-backend/pdcscrn.c:75:5: warning: "CONFIG_SPEAKER" is not defined [-Wundef] […] The GCC documentation states [1] In some contexts this shortcut is undesirable. The -Wundef option causes GCC to warn whenever it encounters an identifier which is not a macro in an ‘#if’. and therefore use `#ifdef` [2] to silence this warning. No functional change is done, as `CONFIG_SPEAKER` is assigned the value `Y` when defined. There was some discussion going on the list [3], but my points in there turned out to be incorrect. [1] http://gcc.gnu.org/onlinedocs/cpp/If.html [2] http://gcc.gnu.org/onlinedocs/cpp/Ifdef.html [3] http://www.coreboot.org/pipermail/coreboot/2013-March/075561.html Change-Id: I8e9c9b5d01985b21ad05018986d614cf9bf2b439 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/libpayload/curses/pdcurses-backend/pdcscrn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c b/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c index d3f1849..e741b15 100644 --- a/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c +++ b/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c @@ -72,7 +72,7 @@ int PDC_scr_open(int argc, char **argv) SP->lines = PDC_get_rows(); SP->cols = PDC_get_columns(); -#if CONFIG_SPEAKER +#ifdef CONFIG_SPEAKER SP->audible = TRUE; #endif

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New patch to review for coreboot: 927e38b libpayload: cbfs_core.h: Add missing third person s in »it need*s*«
by Paul Menzel 31 Mar '13

31 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2997 -gerrit commit 927e38b487e2a73d848d846c77ef09ce4255bd1b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Jan 25 15:36:59 2013 +0100 libpayload: cbfs_core.h: Add missing third person s in »it need*s*« Introduced in »libpayload: New CBFS to support multiple firmware media sources.« (d01d0368) [1]. [1] http://review.coreboot.org/2191 Change-Id: I9feb9ab49825744cd00d6392a526f7af0ed053d1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/libpayload/include/cbfs_core.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h index 81ca866..2dc1992 100644 --- a/payloads/libpayload/include/cbfs_core.h +++ b/payloads/libpayload/include/cbfs_core.h @@ -85,7 +85,7 @@ #define CBFS_HEADER_INVALID_ADDRESS ((void*)(0xffffffff)) -/** this is the master cbfs header - it need to be located somewhere available +/** this is the master cbfs header - it needs to be located somewhere available to bootblock (to load romstage). Where it actually lives is up to coreboot. On x86, a pointer to this header will live at 0xFFFFFFFC. For other platforms, you need to define CONFIG_CBFS_HEADER_ROM_OFFSET */

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Patch set updated for coreboot: 6784efe util/inteltool: Add support for mobile 5 chipset
by Paul Menzel 31 Mar '13

31 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2993 -gerrit commit 6784efeb43aeea29ec818d0b70ed04f4c60e8d60 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 31 13:51:37 2013 +0200 util/inteltool: Add support for mobile 5 chipset Dump registers on mobile 5. Successfully tested on X201. Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/inteltool/cpu.c | 118 +++++++++++++++++++++++++++++++++++++++++++++ util/inteltool/gpio.c | 6 +++ util/inteltool/inteltool.h | 1 + util/inteltool/memory.c | 90 +++++++++++++++++++++++++++++++++- util/inteltool/powermgt.c | 6 +++ util/inteltool/rootcmplx.c | 1 + 6 files changed, 221 insertions(+), 1 deletion(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index e73f096..137602e 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -888,6 +888,123 @@ int print_intel_core_msrs(void) { 0x0600, "IA32_DS_AREA" }, }; + static const msr_entry_t model20650_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, +// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + { 0x00ce, "IA32_MSR_PLATFORM_INFO" }, + { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x019d, "MSR_THERM2_CTL" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0300, "MSR_BPU_COUNTER0" }, + { 0x0301, "MSR_BPU_COUNTER1" }, + /* Skipped through 0x3ff for now*/ + + /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being + * set in MCX_STATUS */ + { 0x400, "IA32_MC0_CTL" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x402, "IA32_MC0_ADDR" }, + { 0x403, "IA32_MC0_MISC" }, + { 0x404, "IA32_MC1_CTL" }, + { 0x405, "IA32_MC1_STATUS" }, + { 0x406, "IA32_MC1_ADDR" }, + { 0x407, "IA32_MC1_MISC" }, + { 0x408, "IA32_MC2_CTL" }, + { 0x409, "IA32_MC2_STATUS" }, + { 0x40a, "IA32_MC2_ADDR" }, + { 0x40c, "IA32_MC3_CTL" }, + { 0x40d, "IA32_MC3_STATUS" }, + { 0x40e, "IA32_MC3_ADDR" }, + { 0x410, "IA32_MC4_CTL" }, + { 0x411, "IA32_MC4_STATUS" }, + }; + + static const msr_entry_t model20650_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x009b, "IA32_SMM_MONITOR_CTL" }, + { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0186, "MSR_MCG_RBP" }, + { 0x0187, "MSR_MCG_RSP" }, + { 0x0188, "MSR_MCG_RFLAGS" }, + { 0x0189, "MSR_MCG_RIP" }, + { 0x0194, "MSR_MCG_R12" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x0199, "IA32_PERF_CTL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific + { 0x01aa, "IA32_MISC_PWR_MGMT" }, + { 0x01d9, "MSR_DEBUGCTLA" }, + { 0x01fc, "MSR_POWER_CTL" }, + { 0x0277, "IA32_PAT" }, + /** Virtualization + { 0x480, "IA32_VMX_BASIC" }, + through + { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, + Not implemented in my CPU + */ + { 0x0600, "IA32_DS_AREA" }, + /* 0x0680 - 0x06cf Branch Records Skipped */ + + { 0x3a, "IA32_FEATURE_CONTROL" }, + { 0x13c, "MSR_FEATURE_CONFIG" }, + { 0x194, "MSR_FLEX_RATIO" }, + { 0x1a0, "IA32_MISC_ENABLE" }, + { 0x1a2, "MSR_TEMPERATURE_TARGET" }, + { 0x199, "IA32_PERF_CTL" }, + { 0x19b, "IA32_THERM_INTERRUPT" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x2e, "MSR_PIC_MSG_CONTROL" }, + { 0xce, "MSR_PLATFORM_INFO" }, + { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" }, + { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" }, + { 0x1aa, "MSR_MISC_PWR_MGMT" }, + { 0x1ad, "MSR_TURBO_RATIO_LIMIT" }, + { 0x1fc, "MSR_POWER_CTL" }, + }; + typedef struct { unsigned int model; const msr_entry_t *global_msrs; @@ -904,6 +1021,7 @@ int print_intel_core_msrs(void) { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, + { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, }; cpu_t *cpu = NULL; diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 8b85593..5f3d1a4e 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -363,6 +363,12 @@ int print_gpios(struct pci_dev *sb) size = ARRAY_SIZE(i631x_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_MOBILE_5: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = i631x_gpio_registers; + size = ARRAY_SIZE(i631x_gpio_registers); + break; + case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); return 1; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index ac23fe1..2e389ff 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -60,6 +60,7 @@ #define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 +#define PCI_DEVICE_ID_INTEL_MOBILE_5 0x3b07 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_Z68 0x1c44 #define PCI_DEVICE_ID_INTEL_P67 0x1c46 diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 72a2de4..ffe3c8b 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -64,13 +64,97 @@ static const io_register_t sandybridge_mch_registers[] = { { 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data }; +volatile uint8_t *mchbar; + +static void write_mchbar32 (uint32_t addr, uint32_t val) +{ + * (volatile uint32_t *) (mchbar + addr) = val; +} + +static uint32_t read_mchbar32 (uint32_t addr) +{ + return * (volatile uint32_t *) (mchbar + addr); +} + +static uint8_t read_mchbar8 (uint32_t addr) +{ + return * (volatile uint8_t *) (mchbar + addr); +} + +static u16 read_500 (int channel, u16 addr, int split) +{ + uint32_t val; + write_mchbar32 (0x500 + (channel << 10), 0); + while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000); + write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr)); + while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000); + val = read_mchbar32 (0x508 + (channel << 10)); + + return val & ((1 << split) - 1); +} + +static inline u16 get_lane_offset (int slot, int rank, int lane) +{ + return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8); +} + +static inline u16 get_timing_register_addr (int lane, int tm, int slot, int rank) +{ + const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c }; + return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4]; +} + +static void write_1d0 (u32 val, u16 addr, int bits, int flag) +{ + write_mchbar32 (0x1d0, 0); + while (read_mchbar32 (0x1d0) & 0x800000); + write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); + write_mchbar32 (0x1d0, 0x40000000 | addr); + while (read_mchbar32 (0x1d0) & 0x800000); +} + +static u16 read_1d0 (u16 addr, int split) +{ + u32 val; + write_mchbar32 (0x1d0, 0); + while (read_mchbar32 (0x1d0) & 0x800000); + write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr)); + while (read_mchbar32 (0x1d0) & 0x800000); + val = read_mchbar32 (0x1d8); + write_1d0 (0, 0x33d, 0, 0); + write_1d0 (0, 0x33d, 0, 0); + return val & ((1 << split) - 1); +} + +static void dump_timings (void) +{ + int channel, slot, rank, lane, i; + printf ("Timings:\n"); + for (channel = 0; channel < 2; channel++) + for (slot = 0; slot < 2; slot++) + for (rank = 0; rank < 2; rank++) { + printf ("channel %d, slot %d, rank %d\n", channel, slot, rank); + for (lane = 0; lane < 9; lane++) { + printf ("lane %d: ", lane); + for (i = 0; i < 4; i++) { + printf ("%x ", read_500 (channel, + get_timing_register_addr (lane, i, slot, rank), 9)); + } + printf ("\n"); + } + } + + printf ("[178] = %x\n", read_1d0 (0x178, 7)); + printf ("[10b] = %x\n", read_1d0 (0x10b, 6)); +} + + /* * (G)MCH MMIO Config Space */ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) { int i, size = (16 * 1024); - volatile uint8_t *mchbar; uint64_t mchbar_phys; const io_register_t *mch_registers = NULL; struct pci_dev *nb_device6; /* "overflow device" on i865 */ @@ -229,6 +313,10 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) } } + if (nb->device_id == PCI_DEVICE_ID_INTEL_CORE_1ST_GEN) { + printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1); + dump_timings (); + } unmap_physical((void *)mchbar, size); return 0; } diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 71dfc49..7e1a20e 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -677,6 +677,12 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) size = ARRAY_SIZE(i63xx_pm_registers); break; + case PCI_DEVICE_ID_INTEL_MOBILE_5: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = i63xx_pm_registers; + size = ARRAY_SIZE(i63xx_pm_registers); + break; + case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have PMBASE.\n"); return 1; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 7cc55de..8cf2ffb 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -47,6 +47,7 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: case PCI_DEVICE_ID_INTEL_I63XX: + case PCI_DEVICE_ID_INTEL_MOBILE_5: case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: case PCI_DEVICE_ID_INTEL_UM67:

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New patch to review for coreboot: 62c8896 inteltool: Allow to override Makefile variables
by Paul Menzel 31 Mar '13

31 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2996 -gerrit commit 62c88966d6c7bd75fd62a8759fdbb7f444a34319 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 31 22:15:43 2013 +0200 inteltool: Allow to override Makefile variables Allow to override the variables `CC`, `INSTALL`, `PREFIX`, `CFLAGS` and `LDFLAGS`. Though append `-lpci -lz` to `LDFLAGS`. This way for example a different compiler can easily be used. CC=clang make As a side note, Clang in contrast to GCC does *not* issue the following warnings. $ clang --version Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2) Target: i386-pc-linux-gnu Thread model: posix $ gcc --version gcc-4.7.real (Debian 4.7.2-15) 4.7.2 Copyright (C) 2012 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. $ make […] amb.c: In function ‘amb_read_config32’: amb.c:31:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:31:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config16’: amb.c:45:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:45:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] amb.c: In function ‘amb_read_config8’: amb.c:60:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] amb.c:60:10: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] […] Change-Id: Id75dea081ecb35390f283520a7e5dce520f4c98d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/inteltool/Makefile | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 6c94460..2028a4a 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -21,17 +21,17 @@ PROGRAM = inteltool -CC = gcc -INSTALL = /usr/bin/install -PREFIX = /usr/local -CFLAGS = -O2 -g -Wall -W -LDFLAGS = -lpci -lz +CC ?= gcc +INSTALL ?= /usr/bin/install +PREFIX ?= /usr/local +CFLAGS ?= -O2 -g -Wall -W +LDFLAGS += -lpci -lz OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) -LDFLAGS = -framework DirectHW -lpci -lz +LDFLAGS += -framework DirectHW endif ifeq ($(OS_ARCH), FreeBSD) CFLAGS += -I/usr/local/include

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New patch to review for coreboot: 8d24557 intel/bd82x6x: Support mobile 5 southbridge
by Vladimir Serbinenko 31 Mar '13

31 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2995 -gerrit commit 8d245579f0fd7fd39e16b525237f7386e5316cbe Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 31 22:22:10 2013 +0200 intel/bd82x6x: Support mobile 5 southbridge Adjust bd82x6x to support mobile 5 revision as well. Successfully tested on Lenovo X201. Change-Id: I18054cf7edae92f2d8776561661d5b87599ece25 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/parrot/devicetree.cb | 11 ++ src/mainboard/intel/emeraldlake2/devicetree.cb | 11 ++ src/mainboard/samsung/lumpy/devicetree.cb | 11 ++ src/mainboard/samsung/stumpy/devicetree.cb | 11 ++ src/southbridge/intel/bd82x6x/Kconfig | 20 ++++ src/southbridge/intel/bd82x6x/Makefile.inc | 1 + src/southbridge/intel/bd82x6x/azalia.c | 2 +- src/southbridge/intel/bd82x6x/chip.h | 44 ++++++++ src/southbridge/intel/bd82x6x/early_smbus.c | 15 +++ src/southbridge/intel/bd82x6x/lpc.c | 103 +++++++++++++++++- src/southbridge/intel/bd82x6x/me.c | 17 ++- src/southbridge/intel/bd82x6x/me.h | 1 + src/southbridge/intel/bd82x6x/pch.h | 43 ++------ src/southbridge/intel/bd82x6x/sata.c | 46 +++++--- src/southbridge/intel/bd82x6x/smbus.c | 2 +- src/southbridge/intel/bd82x6x/smbus.h | 144 +++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/spi.c | 3 +- src/southbridge/intel/bd82x6x/thermal.c | 84 +++++++++++++++ src/southbridge/intel/bd82x6x/usb_debug.c | 9 +- src/southbridge/intel/bd82x6x/usb_ehci.c | 41 ++++--- 20 files changed, 544 insertions(+), 75 deletions(-) diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf..32d7c54 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -64,6 +64,17 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" + register "sata_irq_line" = "0xa" + register "ide_tim_pri" = "IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0" + register "ide_sdma_cnt" = "IDE_PSDE0" + register "ide_sdma_tim" = "0x0001" + register "ide_config" = "SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0" + register "set98" = "0" + register "sir4" = "0x00001600" + register "sir28" = "0xa0000033" + register "sir54" = "0x5555aa" + register "sir64" = "0xcccc8484" + register "sir88" = "0x88338822" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C register "gen1_dec" = "0x0004fd61" diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0bb42d6..cf82e45 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -53,6 +53,17 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" + register "sata_irq_line" = "0xa" + register "ide_tim_pri" = "IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0" + register "ide_sdma_cnt" = "IDE_PSDE0" + register "ide_sdma_tim" = "0x0001" + register "ide_config" = "SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0" + register "set98" = "0" + register "sir4" = "0x00001600" + register "sir28" = "0xa0000033" + register "sir54" = "0x5555aa" + register "sir64" = "0xcccc8484" + register "sir88" = "0x88338822" # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index cdd7a5c..26b6d73 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -62,6 +62,17 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" + register "sata_irq_line" = "0xa" + register "ide_tim_pri" = "IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0" + register "ide_sdma_cnt" = "IDE_PSDE0" + register "ide_sdma_tim" = "0x0001" + register "ide_config" = "SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0" + register "set98" = "0" + register "sir4" = "0x00001600" + register "sir28" = "0xa0000033" + register "sir54" = "0x5555aa" + register "sir64" = "0xcccc8484" + register "sir88" = "0x88338822" # EC range is 0xa00-0xa3f register "gen1_dec" = "0x003c0a01" diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ee01e8a..cf308e9 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -52,6 +52,17 @@ chip northbridge/intel/sandybridge register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" + register "sata_irq_line" = "0xa" + register "ide_tim_pri" = "IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0" + register "ide_sdma_cnt" = "IDE_PSDE0" + register "ide_sdma_tim" = "0x0001" + register "ide_config" = "SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0" + register "set98" = "0" + register "sir4" = "0x00001600" + register "sir28" = "0xa0000033" + register "sir54" = "0x5555aa" + register "sir64" = "0xcccc8484" + register "sir88" = "0x88338822" # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 5dd492c..71881f3 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -72,4 +72,24 @@ config LOCK_MANAGEMENT_ENGINE If unsure, say N. +config USBDEBUG_DEV + int + default 29 + +config USBDEBUG_FUNC + int + default 7 + +config USBDEBUG_DEFAULT_PORT + int + default 2 + +config IO_APIC_ID + int + default 2 + +config PMCON_RAMINIT_REVERSED + int + default 1 + endif diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index bc3ff4b..366b7e4 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -33,6 +33,7 @@ ramstage-y += usb_xhci.c ramstage-y += me.c ramstage-y += me_8.x.c ramstage-y += smbus.c +ramstage-y += thermal.c ramstage-y += me_status.c ramstage-y += reset.c diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 2d854a4..17141d6 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -362,7 +362,7 @@ static struct device_operations azalia_ops = { .ops_pci = &azalia_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 }; +static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0x3b56, 0 }; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops, diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 828466c..c2c25ec 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -20,6 +20,39 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) + +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) + struct southbridge_intel_bd82x6x_config { /** * Interrupt Routing configuration @@ -69,6 +102,17 @@ struct southbridge_intel_bd82x6x_config { uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; + uint8_t sata_irq_line; + uint16_t ide_tim_pri; + uint32_t ide_config; + uint16_t ide_sdma_cnt; + uint16_t ide_sdma_tim; + uint32_t sir4; + uint32_t sir28; + uint32_t sir54; + uint32_t sir64; + uint32_t sir88; + int set98; /** * SATA Interface Speed Support Configuration diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 9de97e7..d8aff92 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -60,3 +60,18 @@ int smbus_read_byte(unsigned device, unsigned address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } +int smbus_write_byte(unsigned device, unsigned address, u8 data) +{ + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); +} + +int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf) +{ + return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); +} + +int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf) +{ + return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); +} + diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index df37ddc..835f0c8 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -52,7 +52,7 @@ static void pch_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, 0x80); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (CONFIG_IO_APIC_ID << 24); /* affirm full set of redirection table entries ("write once") */ *ioapic_index = 1; @@ -63,7 +63,7 @@ static void pch_enable_apic(struct device *dev) *ioapic_index = 0; reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) + if (reg32 != (CONFIG_IO_APIC_ID << 24)) die("APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); @@ -391,6 +391,96 @@ static void ppt_pm_init(struct device *dev) RCBA32_AND_OR(0x21b0, ~0UL, 0xf); } +static void mobile5_pm_init(struct device *dev) +{ + int i; + + printk(BIOS_DEBUG, "Mobile 5 PM init\n"); + pci_write_config8(dev, 0xa9, 0x47); + + RCBA32 (0x1d44) = 0x00000000; + (void) RCBA32 (0x1d44); + RCBA32 (0x1d48) = 0x00030000; + (void) RCBA32 (0x1d48); + RCBA32 (0x1e80) = 0x000c0801; + (void) RCBA32 (0x1e80); + RCBA32 (0x1e84) = 0x000200f0; + (void) RCBA32 (0x1e84); + + const u32 rcba2010[] = + { + /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, + /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 + }; + for (i = 0; i < sizeof (rcba2010) / sizeof (rcba2010[0]); i++) + { + RCBA32 (0x2010 + 4 * i) = rcba2010[i]; + RCBA32 (0x2010 + 4 * i); + } + + RCBA32 (0x2100) = 0x00000000; + (void) RCBA32 (0x2100); + RCBA32 (0x2104) = 0x00000757; + (void) RCBA32 (0x2104); + RCBA32 (0x2108) = 0x00170001; + (void) RCBA32 (0x2108); + + RCBA32 (0x211c) = 0x00000000; + (void) RCBA32 (0x211c); + RCBA32 (0x2120) = 0x00010000; + (void) RCBA32 (0x2120); + + RCBA32 (0x21fc) = 0x00000000; + (void) RCBA32 (0x21fc); + RCBA32 (0x2200) = 0x20000044; + (void) RCBA32 (0x2200); + RCBA32 (0x2204) = 0x00000001; + (void) RCBA32 (0x2204); + RCBA32 (0x2208) = 0x00003457; + (void) RCBA32 (0x2208); + + const u32 rcba2210[] = + { + /* 2210 */ 0x00000000, 0x00000001, 0xa0fff210, 0x0000df00, + /* 2220 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2230 */ 0x00e30880, 0x00000070, 0x00004000, 0x00000000, + /* 2240 */ 0x00002301, 0x36000000, 0x00010107, 0x00160000, + /* 2250 */ 0x00001b01, 0x36000000, 0x00010107, 0x00160000, + /* 2260 */ 0x00000601, 0x16000000, 0x00010107, 0x00160000, + /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 + }; + + for (i = 0; i < sizeof (rcba2210) / sizeof (rcba2210[0]); i++) + { + RCBA32 (0x2210 + 4 * i) = rcba2210[i]; + RCBA32 (0x2210 + 4 * i); + } + + const u32 rcba2300[] = + { + /* 2300: */ 0x00000000, 0x40000000, 0x4646827b, 0x6e803131, + /* 2310: */ 0x32c77887, 0x00077733, 0x00007447, 0x00000040, + /* 2320: */ 0xcccc0cfc, 0x0fbb0fff + }; + + for (i = 0; i < sizeof (rcba2300) / sizeof (rcba2300[0]); i++) + { + RCBA32 (0x2300 + 4 * i) = rcba2300[i]; + RCBA32 (0x2300 + 4 * i); + } + + RCBA32 (0x37fc) = 0x00000000; + (void) RCBA32 (0x37fc); + RCBA32 (0x3dfc) = 0x00000000; + (void) RCBA32 (0x3dfc); + RCBA32 (0x3e7c) = 0xffffffff; + (void) RCBA32 (0x3e7c); + RCBA32 (0x3efc) = 0x00000000; + (void) RCBA32 (0x3efc); + RCBA32 (0x3f00) = 0x0000010b; + (void) RCBA32 (0x3f00); +} + static void enable_hpet(void) { u32 reg32; @@ -503,12 +593,14 @@ static void pch_disable_smm_only_flashing(struct device *dev) static void pch_fixups(struct device *dev) { +#if CONFIG_PMCON_RAMINIT_REVERSED u8 gen_pmcon_2; /* Indicate DRAM init done for MRC S3 to know it can resume */ gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); gen_pmcon_2 |= (1 << 7); pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); +#endif /* * Enable DMI ASPM in the PCH @@ -537,6 +629,9 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + if (pch_silicon_type() == PCH_TYPE_MOBILE5) + mobile5_pm_init (dev); + /* IO APIC initialization. */ pch_enable_apic(dev); @@ -556,6 +651,8 @@ static void lpc_init(struct device *dev) case PCH_TYPE_PPT: /* PantherPoint */ ppt_pm_init(dev); break; + case PCH_TYPE_MOBILE5: + break; default: printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); } @@ -700,7 +797,7 @@ static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c52, 0x1c54, 0x1e55, 0x1c56, 0x1e57, 0x1c5c, - 0x1e5d, 0x1e5e, 0x1e5f, + 0x1e5d, 0x1e5e, 0x1e5f, 0x3b07, 0 }; static const struct pci_driver pch_lpc __pci_driver = { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7fdf926..123fc73 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -724,10 +724,13 @@ static void intel_me_init(device_t dev) break; #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) - /* Print ME firmware version */ - mkhi_get_fw_version(); - /* Print ME firmware capabilities */ - mkhi_get_fwcaps(); + if (dev->device == 0x1c3a) + { + /* Print ME firmware version */ + mkhi_get_fw_version(); + /* Print ME firmware capabilities */ + mkhi_get_fwcaps(); + } #endif /* @@ -768,10 +771,14 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { 0x1c3a, 0x3b64, + 0 }; + + static const struct pci_driver intel_me __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x1c3a, + .devices = pci_device_ids }; #endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index aaeb24d..6e2062d 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -194,6 +194,7 @@ struct mei_header { #define MKHI_MDES_ENABLE 0x09 #define MKHI_GET_FW_VERSION 0x02 +#define MKHI_SET_UMA 0x08 #define MKHI_END_OF_POST 0x0c #define MKHI_FEATURE_OVERRIDE 0x14 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7f64571..b7b4c92 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -22,8 +22,9 @@ #define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H /* PCH types */ -#define PCH_TYPE_CPT 0x1c /* CougarPoint */ -#define PCH_TYPE_PPT 0x1e /* IvyBridge */ +#define PCH_TYPE_CPT 0x1c /* CougarPoint */ +#define PCH_TYPE_PPT 0x1e /* IvyBridge */ +#define PCH_TYPE_MOBILE5 0x3b /* PCH stepping values for LPC device */ #define PCH_STEP_A0 0 @@ -73,6 +74,9 @@ void pch_log_state(void); void enable_smbus(void); void enable_usb_bar(void); int smbus_read_byte(unsigned device, unsigned address); +int smbus_write_byte(unsigned device, unsigned address, u8 data); +int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); +int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); int early_spi_read(u32 offset, u32 size, u8 *buffer); #endif #endif @@ -150,29 +154,15 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ +#define SKPAD_ACPI_S3_MAGIC 0xcafed00d +#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe + /* PCI Configuration Space (D31:F1): IDE */ #define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ @@ -184,20 +174,6 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define IDE_SDMA_TIM 0x4a #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -342,6 +318,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ #define D31IP_SIP2 20 /* SATA Pin 2 */ +#define D31IP_UNKIP 16 #define D31IP_SMIP 12 /* SMBUS Pin */ #define D31IP_SIP 8 /* SATA Pin */ #define D30IP 0x3104 /* 32bit */ diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 594b09d..9655711 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <delay.h> #include "pch.h" typedef struct southbridge_intel_bd82x6x_config config_t; @@ -96,27 +97,26 @@ static void sata_init(struct device *dev) ((config->sata_port_map ^ 0x3f) << 24) | 0x183); } else if(config->sata_ahci) { u32 abar; + int i; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); + udelay (1000); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); + pci_write_config8(dev, INTR_LN, config->sata_irq_line); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_PRI, config->ide_tim_pri); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); + pci_write_config16(dev, IDE_SDMA_CNT, config->ide_sdma_cnt); + pci_write_config16(dev, IDE_SDMA_TIM, config->ide_sdma_tim); /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + pci_write_config32(dev, IDE_CONFIG, config->ide_config); /* for AHCI, Port Enable is managed in memory mapped space */ reg16 = pci_read_config16(dev, 0x92); @@ -126,10 +126,14 @@ static void sata_init(struct device *dev) /* SATA Initialization register */ pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + ((config->sata_port_map ^ 0x3f) << 24) | 0x183 | (config->set98 << 30)); + if (config->set98) + pci_write_config32(dev, 0x98, 0x00590200); /* Initialize AHCI memory-mapped space */ abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + udelay (1000); + printk(BIOS_DEBUG, "ABAR: %08X\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = read32(abar + 0x00); @@ -143,6 +147,16 @@ static void sata_init(struct device *dev) << 20; } write32(abar + 0x00, reg32); + + /* AHCI enable. */ + for (i = 0; i < 5; i++) + { + write32(abar + 0x04, read32 (abar + 0x04) | 0x80000000); + mdelay (1); + if (read32 (abar + 0x04) & 0x80000000) + break; + } + /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); (void) read32(abar + 0x0c); /* Read back 1 */ @@ -212,13 +226,14 @@ static void sata_init(struct device *dev) config->sata_port1_gen3_tx); /* Additional Programming Requirements */ - sir_write(dev, 0x04, 0x00001600); - sir_write(dev, 0x28, 0xa0000033); + sir_write(dev, 0x04, config->sir4); + sir_write(dev, 0x28, config->sir28); reg32 = sir_read(dev, 0x54); reg32 &= 0xff000000; - reg32 |= 0x5555aa; + reg32 |= config->sir54; + sir_write(dev, 0x54, reg32); - sir_write(dev, 0x64, 0xcccc8484); + sir_write(dev, 0x64, config->sir64); reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0xcccc; @@ -226,9 +241,10 @@ static void sata_init(struct device *dev) reg32 = sir_read(dev, 0x78); reg32 &= 0x0000ffff; reg32 |= 0x88880000; + sir_write(dev, 0x78, reg32); sir_write(dev, 0x84, 0x001c7000); - sir_write(dev, 0x88, 0x88338822); + sir_write(dev, 0x88, config->sir88); sir_write(dev, 0xa0, 0x001c7000); // a4 sir_write(dev, 0xc4, 0x0c0c0c0c); @@ -287,7 +303,7 @@ static struct device_operations sata_ops = { static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03, 0x1e00, 0x1e01, 0x1e02, 0x1e03, - 0 }; + 0x3b2e, 0 }; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 4786d8b..ad7c8f9 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -100,7 +100,7 @@ static struct device_operations smbus_ops = { .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0 }; +static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x3b30, 0 }; static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, diff --git a/src/southbridge/intel/bd82x6x/smbus.h b/src/southbridge/intel/bd82x6x/smbus.h index 81e5949..d6e4ce5 100644 --- a/src/southbridge/intel/bd82x6x/smbus.h +++ b/src/southbridge/intel/bd82x6x/smbus.h @@ -98,3 +98,147 @@ static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned add return byte; } +#ifdef __PRE_RAM__ + +static int do_smbus_write_byte(unsigned smbus_base, unsigned device, unsigned address, unsigned data) +{ + unsigned char global_status_register; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(address & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a byte data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Clear the data byte... */ + outb(data, smbus_base + SMBHSTDAT0); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; + + global_status_register = inb(smbus_base + SMBHSTSTAT); + + /* Ignore the "In Use" status... */ + global_status_register &= ~(3 << 5); + + /* Read results of transaction */ + if (global_status_register != (1 << 1)) + return SMBUS_ERROR; + + return 0; +} + +static int do_smbus_block_write(unsigned smbus_base, unsigned device, + unsigned cmd, unsigned bytes, const u8 *buf) +{ + u8 status; + + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(cmd & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a block data write */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* set number of bytes to transfer */ + outb(bytes, smbus_base + SMBHSTDAT0); + + outb(*buf++, smbus_base + SMBBLKDAT); + bytes--; + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + /* Poll for transaction completion */ + do { + status = inb(smbus_base + SMBHSTSTAT); + if (status & ((1 << 4) | /* FAILED */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ + return SMBUS_ERROR; + + if (status & 0x80) { /* Byte done */ + outb(*buf++, smbus_base + SMBBLKDAT); + outb(status, smbus_base + SMBHSTSTAT); + } + } while(status & 0x01); + + return 0; +} + +static int do_smbus_block_read(unsigned smbus_base, unsigned device, + unsigned cmd, unsigned bytes, u8 *buf) +{ + u8 status; + int bytes_read = 0; + if (smbus_wait_until_ready(smbus_base) < 0) + return SMBUS_WAIT_UNTIL_READY_TIMEOUT; + + /* Setup transaction */ + /* Disable interrupts */ + outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); + /* Set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); + /* Set the command/address... */ + outb(cmd & 0xff, smbus_base + SMBHSTCMD); + /* Set up for a block data read */ + outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x5 << 2), + (smbus_base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); + + /* Start the command */ + outb((inb(smbus_base + SMBHSTCTL) | 0x40), + smbus_base + SMBHSTCTL); + + while(!(inb(smbus_base + SMBHSTSTAT) & 1)); + /* Poll for transaction completion */ + do { + status = inb(smbus_base + SMBHSTSTAT); + if (status & ((1 << 4) | /* FAILED */ + (1 << 3) | /* BUS ERR */ + (1 << 2))) /* DEV ERR */ + return SMBUS_ERROR; + + if (status & 0x80) { /* Byte done */ + *buf = inb(smbus_base + SMBBLKDAT); + buf++; + bytes_read++; + outb(status, smbus_base + SMBHSTSTAT); + if (--bytes == 1) { + /* indicate that next byte is the last one */ + outb(inb(smbus_base + SMBHSTCTL) | 0x20, + smbus_base + SMBHSTCTL); + } + } + } while(status & 0x01); + + return bytes_read; +} +#endif diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..26553fe 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -315,7 +315,8 @@ static inline int get_ich_version(uint16_t device_id) if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) + || device_id == 0x3b07) return 9; return 0; diff --git a/src/southbridge/intel/bd82x6x/thermal.c b/src/southbridge/intel/bd82x6x/thermal.c new file mode 100644 index 0000000..c1040c5 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/thermal.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "pch.h" +#include <usbdebug.h> +#include <arch/io.h> + +static void thermal_init(struct device *dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "Thermal init start.\n"); + + res = find_resource(dev, 0x10); + if (!res) return; + + write32 (res->base + 4, 0x3a2b); + write8 (res->base + 0xe, 0x40); + write32 (res->base + 0x12, 0x1a40); + write16 (res->base + 0x16, 0x7746); + write16 (res->base + 0x1a, 0x10f0); + write16 (res->base + 0x56, 0xffff); + write16 (res->base + 0x64, 0xffff); + write16 (res->base + 0x66, 0xffff); + write16 (res->base + 0x68, 0xfa); + + write8 (res->base + 1, 0xb8); + + printk(BIOS_DEBUG, "Thermal init done.\n"); +} + + +static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations pci_ops = { + .set_subsystem = set_subsystem, +}; + +static struct device_operations thermal_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = thermal_init, + .scan_bus = 0, + .ops_pci = &pci_ops, +}; + +static const unsigned short pci_device_ids[] = { 0x3b32, 0 }; + +static const struct pci_driver pch_thermal __pci_driver = { + .ops = &thermal_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c index 79a43bd..22ab83b 100644 --- a/src/southbridge/intel/bd82x6x/usb_debug.c +++ b/src/southbridge/intel/bd82x6x/usb_debug.c @@ -28,16 +28,17 @@ void enable_usbdebug(unsigned int port) { u32 dbgctl; - device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ + device_t dev = PCI_DEV(0, CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC); + device_t bdev = PCI_DEV(0, 0, 0); /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR); + pci_write_config16(bdev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Force ownership of the Debug Port to the EHCI controller. */ - printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); @@ -47,6 +48,6 @@ void enable_usbdebug(unsigned int port) /* Required for successful build, but currently empty. */ void set_debug_port(unsigned int port) { - /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ + /* Not needed, the ICH* southbridges hardcode physical USB port 2. */ } diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index aec230c..4723ce9 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -36,6 +36,17 @@ static void usb_ehci_init(struct device *dev) RCBA32(0x35b0) = reg32; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); + + if (dev->device == 0x3b34 || dev->device == 0x3b3c) + { + pci_write_config32 (dev, 0x84, 0x130c8911); + pci_write_config32 (dev, 0x88, 0xa0); + pci_write_config32 (dev, 0xf4, 0x80808588); + pci_write_config32 (dev, 0xf4, 0x00808588); + pci_write_config32 (dev, 0xf4, 0x00808588); + pci_write_config32 (dev, 0xfc, 0x301b1728); + } + reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; //reg32 |= PCI_COMMAND_SERR; @@ -68,22 +79,28 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic static void usb_ehci_set_resources(struct device *dev) { #if CONFIG_USBDEBUG - struct resource *res; - u32 base; - u32 usb_debug; + u32 usb_debug = 0; - usb_debug = get_ehci_debug(); - set_ehci_debug(0); + if (dev->path.pci.devfn == PCI_DEVFN (CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC)) + { + usb_debug = get_ehci_debug(); + set_ehci_debug(0); + } #endif pci_dev_set_resources(dev); #if CONFIG_USBDEBUG - res = find_resource(dev, 0x10); - set_ehci_debug(usb_debug); - if (!res) return; - base = res->base; - set_ehci_base(base); - report_resource_stored(dev, res, ""); + if (dev->path.pci.devfn == PCI_DEVFN (CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC)) + { + struct resource *res; + u32 base; + res = find_resource(dev, 0x10); + if (!res) return; + base = res->base; + set_ehci_debug(usb_debug); + set_ehci_base(base); + report_resource_stored(dev, res, ""); + } #endif } @@ -103,7 +120,7 @@ static struct device_operations usb_ehci_ops = { }; static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d, - 0 }; + 0x3b34, 0x3b3c, 0 }; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops,

1 0

New patch to review for coreboot: 69f78c5 inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t`
by Paul Menzel 31 Mar '13

31 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2994 -gerrit commit 69f78c59ef8882ab2f5d29dc78ed01310f111ebe Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Mar 31 22:02:16 2013 +0200 inteltool: Use `ll` instead of `l` as the length modifier for `uint64_t` When buidling inteltool with GCC, the following warning is printed. $ make […] gcc -O2 -g -Wall -W -c -o memory.o memory.c memory.c: In function ‘print_mchbar’: memory.c:287:7: warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘uint64_t’ [-Wformat] […] This was introduced in commit »inteltool: Add support for H65 Express chipset« (c7fc4422) [1]. Address this warning, by using `%llx` instead of `%lx`. [1] http://review.coreboot.org/1258 Change-Id: I4f714edce7e8b405e1a7a417d02fa498322c88a8 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/inteltool/memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 72a2de4..6847e5c 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -197,7 +197,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) for (i = 0; i < size; i++) { switch (mch_registers[i].size) { case 8: - printf("mchbase+0x%04x: 0x%016lx (%s)\n", + printf("mchbase+0x%04x: 0x%016llx (%s)\n", mch_registers[i].addr, *(uint64_t *)(mchbar+mch_registers[i].addr), mch_registers[i].name);

1 0

New patch to review for coreboot: 39c578c util/inteltool: Add support for mobile 5 chipset
by Vladimir Serbinenko 31 Mar '13

31 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2993 -gerrit commit 39c578cf2b64c1fa7664d7b7c433d9862af72a14 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 31 13:51:37 2013 +0200 util/inteltool: Add support for mobile 5 chipset Dump registers on mobile 5. Successfully tested on X201. Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/inteltool/cpu.c | 118 +++++++++++++++++++++++++++++++++++++++++++++ util/inteltool/gpio.c | 6 +++ util/inteltool/inteltool.h | 1 + util/inteltool/memory.c | 102 ++++++++++++++++++++++++++++++++++++++- util/inteltool/powermgt.c | 6 +++ util/inteltool/rootcmplx.c | 1 + 6 files changed, 233 insertions(+), 1 deletion(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index e73f096..137602e 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -888,6 +888,123 @@ int print_intel_core_msrs(void) { 0x0600, "IA32_DS_AREA" }, }; + static const msr_entry_t model20650_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, +// WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + { 0x00ce, "IA32_MSR_PLATFORM_INFO" }, + { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x019d, "MSR_THERM2_CTL" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0300, "MSR_BPU_COUNTER0" }, + { 0x0301, "MSR_BPU_COUNTER1" }, + /* Skipped through 0x3ff for now*/ + + /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being + * set in MCX_STATUS */ + { 0x400, "IA32_MC0_CTL" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x402, "IA32_MC0_ADDR" }, + { 0x403, "IA32_MC0_MISC" }, + { 0x404, "IA32_MC1_CTL" }, + { 0x405, "IA32_MC1_STATUS" }, + { 0x406, "IA32_MC1_ADDR" }, + { 0x407, "IA32_MC1_MISC" }, + { 0x408, "IA32_MC2_CTL" }, + { 0x409, "IA32_MC2_STATUS" }, + { 0x40a, "IA32_MC2_ADDR" }, + { 0x40c, "IA32_MC3_CTL" }, + { 0x40d, "IA32_MC3_STATUS" }, + { 0x40e, "IA32_MC3_ADDR" }, + { 0x410, "IA32_MC4_CTL" }, + { 0x411, "IA32_MC4_STATUS" }, + }; + + static const msr_entry_t model20650_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x009b, "IA32_SMM_MONITOR_CTL" }, + { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0186, "MSR_MCG_RBP" }, + { 0x0187, "MSR_MCG_RSP" }, + { 0x0188, "MSR_MCG_RFLAGS" }, + { 0x0189, "MSR_MCG_RIP" }, + { 0x0194, "MSR_MCG_R12" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x0199, "IA32_PERF_CTL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific + { 0x01aa, "IA32_MISC_PWR_MGMT" }, + { 0x01d9, "MSR_DEBUGCTLA" }, + { 0x01fc, "MSR_POWER_CTL" }, + { 0x0277, "IA32_PAT" }, + /** Virtualization + { 0x480, "IA32_VMX_BASIC" }, + through + { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, + Not implemented in my CPU + */ + { 0x0600, "IA32_DS_AREA" }, + /* 0x0680 - 0x06cf Branch Records Skipped */ + + { 0x3a, "IA32_FEATURE_CONTROL" }, + { 0x13c, "MSR_FEATURE_CONFIG" }, + { 0x194, "MSR_FLEX_RATIO" }, + { 0x1a0, "IA32_MISC_ENABLE" }, + { 0x1a2, "MSR_TEMPERATURE_TARGET" }, + { 0x199, "IA32_PERF_CTL" }, + { 0x19b, "IA32_THERM_INTERRUPT" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x2e, "MSR_PIC_MSG_CONTROL" }, + { 0xce, "MSR_PLATFORM_INFO" }, + { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" }, + { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" }, + { 0x1aa, "MSR_MISC_PWR_MGMT" }, + { 0x1ad, "MSR_TURBO_RATIO_LIMIT" }, + { 0x1fc, "MSR_POWER_CTL" }, + }; + typedef struct { unsigned int model; const msr_entry_t *global_msrs; @@ -904,6 +1021,7 @@ int print_intel_core_msrs(void) { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, + { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, }; cpu_t *cpu = NULL; diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 8b85593..5f3d1a4e 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -363,6 +363,12 @@ int print_gpios(struct pci_dev *sb) size = ARRAY_SIZE(i631x_gpio_registers); break; + case PCI_DEVICE_ID_INTEL_MOBILE_5: + gpiobase = pci_read_word(sb, 0x48) & 0xfffc; + gpio_registers = i631x_gpio_registers; + size = ARRAY_SIZE(i631x_gpio_registers); + break; + case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); return 1; diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index ac23fe1..2e389ff 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -60,6 +60,7 @@ #define PCI_DEVICE_ID_INTEL_ICH9M 0x2919 #define PCI_DEVICE_ID_INTEL_ICH9ME 0x2917 #define PCI_DEVICE_ID_INTEL_ICH10R 0x3a16 +#define PCI_DEVICE_ID_INTEL_MOBILE_5 0x3b07 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 #define PCI_DEVICE_ID_INTEL_Z68 0x1c44 #define PCI_DEVICE_ID_INTEL_P67 0x1c46 diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 72a2de4..536e223 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -64,13 +64,108 @@ static const io_register_t sandybridge_mch_registers[] = { { 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data }; +volatile uint8_t *mchbar; + +static void +write_mchbar32 (uint32_t addr, uint32_t val) +{ + * (volatile uint32_t *) (mchbar + addr) = val; +} + +static uint32_t +read_mchbar32 (uint32_t addr) +{ + return * (volatile uint32_t *) (mchbar + addr); +} + +static uint8_t +read_mchbar8 (uint32_t addr) +{ + return * (volatile uint8_t *) (mchbar + addr); +} + +static u16 +read_500 (int channel, u16 addr, int split) +{ + uint32_t val; + write_mchbar32 (0x500 + (channel << 10), 0); + while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000); + write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr)); + while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000); + val = read_mchbar32 (0x508 + (channel << 10)); + return val & ((1 << split) - 1); +} + +static inline u16 +get_lane_offset (int slot, int rank, int lane) +{ + return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8); +} + +static inline u16 +get_timing_register_addr (int lane, int tm, int slot, int rank) +{ + const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c }; + return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4]; +} + +static void +write_1d0 (u32 val, u16 addr, int bits, int flag) +{ + write_mchbar32 (0x1d0, 0); + while (read_mchbar32 (0x1d0) & 0x800000); + write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); + write_mchbar32 (0x1d0, 0x40000000 | addr); + while (read_mchbar32 (0x1d0) & 0x800000); +} + +static u16 +read_1d0 (u16 addr, int split) +{ + u32 val; + write_mchbar32 (0x1d0, 0); + while (read_mchbar32 (0x1d0) & 0x800000); + write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr)); + while (read_mchbar32 (0x1d0) & 0x800000); + val = read_mchbar32 (0x1d8); + write_1d0 (0, 0x33d, 0, 0); + write_1d0 (0, 0x33d, 0, 0); + return val & ((1 << split) - 1); +} + + +static void +dump_timings (void) +{ + int channel, slot, rank, lane, i; + printf ("Timings:\n"); + for (channel = 0; channel < 2; channel++) + for (slot = 0; slot < 2; slot++) + for (rank = 0; rank < 2; rank++) + { + printf ("channel %d, slot %d, rank %d\n", channel, slot, rank); + for (lane = 0; lane < 9; lane++) + { + printf ("lane %d: ", lane); + for (i = 0; i < 4; i++) + { + printf ("%x ", read_500 (channel, + get_timing_register_addr (lane, i, slot, rank), 9)); + } + printf ("\n"); + } + } + printf ("[178] = %x\n", read_1d0 (0x178, 7)); + printf ("[10b] = %x\n", read_1d0 (0x10b, 6)); +} + + /* * (G)MCH MMIO Config Space */ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) { int i, size = (16 * 1024); - volatile uint8_t *mchbar; uint64_t mchbar_phys; const io_register_t *mch_registers = NULL; struct pci_dev *nb_device6; /* "overflow device" on i865 */ @@ -229,6 +324,11 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) } } + if (nb->device_id == PCI_DEVICE_ID_INTEL_CORE_1ST_GEN) + { + printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1); + dump_timings (); + } unmap_physical((void *)mchbar, size); return 0; } diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c index 71dfc49..7e1a20e 100644 --- a/util/inteltool/powermgt.c +++ b/util/inteltool/powermgt.c @@ -677,6 +677,12 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) size = ARRAY_SIZE(i63xx_pm_registers); break; + case PCI_DEVICE_ID_INTEL_MOBILE_5: + pmbase = pci_read_word(sb, 0x40) & 0xfffc; + pm_registers = i63xx_pm_registers; + size = ARRAY_SIZE(i63xx_pm_registers); + break; + case 0x1234: // Dummy for non-existent functionality printf("This southbridge does not have PMBASE.\n"); return 1; diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c index 7cc55de..8cf2ffb 100644 --- a/util/inteltool/rootcmplx.c +++ b/util/inteltool/rootcmplx.c @@ -47,6 +47,7 @@ int print_rcba(struct pci_dev *sb) case PCI_DEVICE_ID_INTEL_ICH10R: case PCI_DEVICE_ID_INTEL_NM10: case PCI_DEVICE_ID_INTEL_I63XX: + case PCI_DEVICE_ID_INTEL_MOBILE_5: case PCI_DEVICE_ID_INTEL_Z68: case PCI_DEVICE_ID_INTEL_P67: case PCI_DEVICE_ID_INTEL_UM67:

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Patch set updated for coreboot: 8e36bf8 util/cbmem: Don't output trailing garbage for cbmemc
by Paul Menzel 30 Mar '13

30 Mar '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2991 -gerrit commit 8e36bf8099019ecdb9bf9d1f7480234e9a7d9c2f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:15:12 2013 +0100 util/cbmem: Don't output trailing garbage for cbmemc Current code outputs the whole cbmemc buffer even if only part of it is really used. Fix it to output only the used part and notify the user if the buffer was too small for the required data. Change-Id: I68c1970cf84d49b2d7d6007dae0679d7a7a0cb99 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/cbmem/cbmem.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index bc6bd6b..aed133a 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -308,12 +308,21 @@ static void dump_timestamps(void) unmap_memory(); } +static const char *future_ngettext (const char *sing, const char *plural, + unsigned long int n) +{ + if (n == 1) + return sing; + return plural; +} + /* dump the cbmem console */ static void dump_console(void) { void *console_p; char *console_c; uint32_t size; + uint32_t cursor; if (console.tag != LB_TAG_CBMEM_CONSOLE) { fprintf(stderr, "No console found in coreboot table.\n"); @@ -328,6 +337,12 @@ static void dump_console(void) * Hence we have to add 8 to get to the actual console string. */ size = *(uint32_t *)console_p; + cursor = *(uint32_t *) (console_p + 4); + /* Cursor continues to go on even after no more data fits in + * the buffer but the data is dropped in this case. + */ + if (size > cursor) + size = cursor; console_c = malloc(size + 1); if (!console_c) { fprintf(stderr, "Not enough memory for console.\n"); @@ -337,7 +352,11 @@ static void dump_console(void) memcpy(console_c, console_p + 8, size); console_c[size] = 0; - printf("%s", console_c); + printf("%s\n", console_c); + if (size < cursor) + printf(future_ngettext("one byte lost\n", + "%d bytes lost\n", cursor - size), + cursor - size); free(console_c);

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Patch set updated for coreboot: dc322e6 Intel: Return on missing microcode file to fix null pointer dereference
by Vladimir Serbinenko 30 Mar '13

30 Mar '13

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2990 -gerrit commit dc322e66370034efefb830df83e5ce78a08b1d88 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Mar 30 12:04:23 2013 +0100 Intel: Return on missing microcode file to fix null pointer dereference Selecting `CPU_MICROCODE_IN_CBFS` in Kconfig but not having the microcode blob `cpu_microcode_blob.bin` in CBFS results in a null pointer dereference later on resulting in a crash. for(c = microcode_updates; m->hdrver; m = (const struct microcode *)c) { Fix this by returning if `microcode_updates` is `NULL`, that means no file is found. This patch is successfully tested on the Lenovo X201. Change-Id: I6e18fd37256910bf047061e4633a66cf29ad7b69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/microcode/microcode.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index d908c25..82ab7a2 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -130,6 +130,9 @@ const void *intel_microcode_find(void) CBFS_TYPE_MICROCODE); #endif + /* No need for explicit error message since the user already gets + "file not found" from cbfs. + */ if (!microcode_updates) return microcode_updates; @@ -202,6 +205,9 @@ void intel_update_microcode(const void *microcode_updates) const char *c; msr_t msr; + if (!microcode_updates) + return; + /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; msr.hi = 0;

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coreboot-gerrit March 2013