Andy Pont has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/48643 )
Change subject: chipset_enable.c: Remove futile attempt to disable lock
......................................................................
chipset_enable.c: Remove futile attempt to disable lock
For all recent Intel chipsets (and possibly others) the ability to
disable the lock fails. This leads to confusing messages being
presented to the user where unlocking fails but the flash update
process works correctly.
Remove the unlock attempt which had alreayd been marked in the source
code comments as "futile".
Signed-off-by: Andy Pont <andy.pont(a)sdcsystems.com>
Change-Id: Id70e132f8feb7b91cbf79d8cdf07744f8763e11b
---
M chipset_enable.c
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/43/48643/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 9205d0e..3ca6ba8 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -333,7 +333,6 @@
wanted |= (1 << 2);
wanted |= (1 << 0); /* Set BIOS Write Enable */
- wanted &= ~(1 << 1); /* Disable lock (futile) */
/* Only write the register if it's necessary */
if (wanted != old) {
--
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Gerrit-Change-Id: Id70e132f8feb7b91cbf79d8cdf07744f8763e11b
Gerrit-Change-Number: 48643
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Gerrit-Owner: Andy Pont <andy.pont(a)sdcsystems.com>
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Hello Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/flashrom/+/34629
to review the following change.
Change subject: dediprog: Fix SF600 4BA mode
......................................................................
dediprog: Fix SF600 4BA mode
Flash chips greater than 16MiB require 4BA mode support.
Current master doesn't support such mode as the SF600 uses
PROTOCOL_V3.
Fix protocol version check to support 4BA on PROTOCOL_V3, too.
Tested on SF600 V:7.2.45
Able to read and write "IS25WP256" (32768 kB, SPI).
Change-Id: I2d3089693fbd2f8f7717a8f71be242be131ce707
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M dediprog.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/34629/1
diff --git a/dediprog.c b/dediprog.c
index 3566109..add478d 100644
--- a/dediprog.c
+++ b/dediprog.c
@@ -1160,7 +1160,7 @@
if (dediprog_devicetype == DEV_SF100 && protocol() == PROTOCOL_V1)
spi_master_dediprog.features &= ~SPI_MASTER_NO_4BA_MODES;
- if (protocol() == PROTOCOL_V2)
+ if (protocol() >= PROTOCOL_V2)
spi_master_dediprog.features |= SPI_MASTER_4BA;
if (register_spi_master(&spi_master_dediprog) || dediprog_set_leds(LED_NONE))
--
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47166 )
Change subject: flaschips.c: Fix building with CONFIG_DUMMY=no
......................................................................
flaschips.c: Fix building with CONFIG_DUMMY=no
With CONFIG_DUMMY=yes dummuflasher.c is not linked in so there is
definition of probe_variable_size.
Change-Id: Ib9bae93fadc55cf133e837e63419da104a6298be
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M flashchips.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/47166/1
diff --git a/flashchips.c b/flashchips.c
index 48efb85..1681f42 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -19081,3 +19081,7 @@
};
const unsigned int flashchips_size = ARRAY_SIZE(flashchips);
+
+#if !CONFIG_DUMMY
+int probe_variable_size(struct flashctx *flash) { return 0; };
+#endif
--
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Sean Anderson has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43608 )
Change subject: buspirate: Add option for setting the aux pin
......................................................................
buspirate: Add option for setting the aux pin
This adds a parameter to drive the aux pin low (or high if you
explicitly want the previous behavior). Some boards need to have a reset
pin driven low before the firmware can be safely flashed. With the Bus
Pirate, this is most easily done with the auxiliary pin.
Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775
Signed-off-by: Sean Anderson <seanga2(a)gmail.com>
---
M buspirate_spi.c
M flashrom.8.tmpl
2 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/43608/1
diff --git a/buspirate_spi.c b/buspirate_spi.c
index fdfc0e4..1ccb107 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -228,6 +228,7 @@
int serialspeed_index = -1;
int ret = 0;
int pullup = 0;
+ int aux = 1;
dev = extract_programmer_param("dev");
if (dev && !strlen(dev)) {
@@ -277,6 +278,17 @@
}
free(tmp);
+ tmp = extract_programmer_param("aux");
+ if (tmp) {
+ if (strcasecmp("high", tmp) == 0)
+ ; /* Default */
+ else if (strcasecmp("low", tmp) == 0)
+ aux = 0;
+ else
+ msg_perr("Invalid AUX state, driving high by default.\n");
+ }
+ free(tmp);
+
/* Default buffer size is 19: 16 bytes data, 3 bytes control. */
#define DEFAULT_BUFSIZE (16 + 3)
bp_commbuf = malloc(DEFAULT_BUFSIZE);
@@ -520,11 +532,18 @@
}
/* Initial setup (SPI peripherals config): Enable power, CS high, AUX */
- bp_commbuf[0] = 0x40 | 0x0b;
+ bp_commbuf[0] = 0x40 | 0x09;
if (pullup == 1) {
bp_commbuf[0] |= (1 << 2);
msg_pdbg("Enabling pull-up resistors.\n");
}
+ if (aux) {
+ bp_commbuf[0] |= (1 << 1);
+ msg_pdbg("Driving AUX high.\n");
+ } else {
+ msg_pdbg("Driving AUX low.\n");
+ }
+
ret = buspirate_sendrecv(bp_commbuf, 1, 1);
if (ret)
return 1;
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index db50d59..caf860c 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -902,6 +902,19 @@
.URLB "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…" \
"in a guide by dangerousprototypes" .
Only the external supply voltage (Vpu) is supported as of this writing.
+.sp
+An optional aux parameter specifies the state of the Bus Pirate auxiliary pin.
+This may be used to drive the auxiliary pin high or low before a transfer.
+Syntax is
+.sp
+.B " flashrom -p buspirate_spi:aux=state"
+.sp
+where
+.B state
+can be
+.BR high " or " low .
+The default
+.BR state " is " high .
.SS
.BR "pickit2_spi " programmer
.IP
--
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70003 )
Change subject: cli, manpage: Clean up occurrences of old image argument
......................................................................
Patch Set 3: Code-Review+2
--
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70128 )
Change subject: flashrom: Skip read/write/erase/verify ops on inaccessable flash regions
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70128/comment/d9db1355_797d5fbd
PS6, Line 18: S
Co-Author?
File flashrom.c:
https://review.coreboot.org/c/flashrom/+/70128/comment/014b0736_47b3f781
PS6, Line 1082: static int write_flash(st
keep this hunk in place of the previous `write_flash()` hunk to make the diff easier to parse/revert.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70169 )
Change subject: ichspi: Handle EC region permissions
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70169/comment/eb74055a_8e576b56
PS3, Line 9: WIP. Not sure if we need this.
maybe mark the patch as WIP while we validate this to avoid delays on the other patches before this.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70126 )
Change subject: programmer: Add get_region to spi/opaque masters
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File include/programmer.h:
https://review.coreboot.org/c/flashrom/+/70126/comment/36cc62e1_312bf466
PS2, Line 291: /* TODO: integrate/deduplicate with layout data structures. */
How about including CB:69196 in your series without the two `bool R|W_prot` fields and changing *this* patch on top just to include the two `bool R|W_prot` fields in the struct so the comment in CB:69196 can be resolved.
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