Sean Anderson has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43608 )
Change subject: buspirate: Add option for setting the aux pin
......................................................................
buspirate: Add option for setting the aux pin
This adds a parameter to drive the aux pin low (or high if you
explicitly want the previous behavior). Some boards need to have a reset
pin driven low before the firmware can be safely flashed. With the Bus
Pirate, this is most easily done with the auxiliary pin.
Change-Id: Ieeecfdf1afc06dadda9b8f99547cd74854ca6775
Signed-off-by: Sean Anderson <seanga2(a)gmail.com>
---
M buspirate_spi.c
M flashrom.8.tmpl
2 files changed, 33 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/43608/1
diff --git a/buspirate_spi.c b/buspirate_spi.c
index fdfc0e4..1ccb107 100644
--- a/buspirate_spi.c
+++ b/buspirate_spi.c
@@ -228,6 +228,7 @@
int serialspeed_index = -1;
int ret = 0;
int pullup = 0;
+ int aux = 1;
dev = extract_programmer_param("dev");
if (dev && !strlen(dev)) {
@@ -277,6 +278,17 @@
}
free(tmp);
+ tmp = extract_programmer_param("aux");
+ if (tmp) {
+ if (strcasecmp("high", tmp) == 0)
+ ; /* Default */
+ else if (strcasecmp("low", tmp) == 0)
+ aux = 0;
+ else
+ msg_perr("Invalid AUX state, driving high by default.\n");
+ }
+ free(tmp);
+
/* Default buffer size is 19: 16 bytes data, 3 bytes control. */
#define DEFAULT_BUFSIZE (16 + 3)
bp_commbuf = malloc(DEFAULT_BUFSIZE);
@@ -520,11 +532,18 @@
}
/* Initial setup (SPI peripherals config): Enable power, CS high, AUX */
- bp_commbuf[0] = 0x40 | 0x0b;
+ bp_commbuf[0] = 0x40 | 0x09;
if (pullup == 1) {
bp_commbuf[0] |= (1 << 2);
msg_pdbg("Enabling pull-up resistors.\n");
}
+ if (aux) {
+ bp_commbuf[0] |= (1 << 1);
+ msg_pdbg("Driving AUX high.\n");
+ } else {
+ msg_pdbg("Driving AUX low.\n");
+ }
+
ret = buspirate_sendrecv(bp_commbuf, 1, 1);
if (ret)
return 1;
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index db50d59..caf860c 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -902,6 +902,19 @@
.URLB "http://dangerousprototypes.com/docs/Practical_guide_to_Bus_Pirate_pull-up_r…" \
"in a guide by dangerousprototypes" .
Only the external supply voltage (Vpu) is supported as of this writing.
+.sp
+An optional aux parameter specifies the state of the Bus Pirate auxiliary pin.
+This may be used to drive the auxiliary pin high or low before a transfer.
+Syntax is
+.sp
+.B " flashrom -p buspirate_spi:aux=state"
+.sp
+where
+.B state
+can be
+.BR high " or " low .
+The default
+.BR state " is " high .
.SS
.BR "pickit2_spi " programmer
.IP
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70003 )
Change subject: cli, manpage: Clean up occurrences of old image argument
......................................................................
Patch Set 3: Code-Review+2
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70128 )
Change subject: flashrom: Skip read/write/erase/verify ops on inaccessable flash regions
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70128/comment/d9db1355_797d5fbd
PS6, Line 18: S
Co-Author?
File flashrom.c:
https://review.coreboot.org/c/flashrom/+/70128/comment/014b0736_47b3f781
PS6, Line 1082: static int write_flash(st
keep this hunk in place of the previous `write_flash()` hunk to make the diff easier to parse/revert.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70169 )
Change subject: ichspi: Handle EC region permissions
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/70169/comment/eb74055a_8e576b56
PS3, Line 9: WIP. Not sure if we need this.
maybe mark the patch as WIP while we validate this to avoid delays on the other patches before this.
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Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70126 )
Change subject: programmer: Add get_region to spi/opaque masters
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File include/programmer.h:
https://review.coreboot.org/c/flashrom/+/70126/comment/36cc62e1_312bf466
PS2, Line 291: /* TODO: integrate/deduplicate with layout data structures. */
How about including CB:69196 in your series without the two `bool R|W_prot` fields and changing *this* patch on top just to include the two `bool R|W_prot` fields in the struct so the comment in CB:69196 can be resolved.
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Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59402 )
Change subject: [RFC][OTP] spi: add functions for OTP regions
......................................................................
Patch Set 25:
(1 comment)
Patchset:
PS25:
> Mailing list thread for convenience: https://mail.coreboot.org/hyperkitty/list/flashrom@flashrom. […]
Abandoned the series as no one has shown any interest in over 6 months.
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