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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55408 )
Change subject: tests: Move test environment header files into tests directory
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/55408/comment/04047176_13b5a1ab
PS1, Line 8:
I agree with the change, but I'd appreciate if you could add a sentence to explain why this is a good idea.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54968 )
Change subject: flashchips: add support for Winbond W25Q01JV
......................................................................
Patch Set 4:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/54968/comment/e3c4e52b_071bba5d
PS1, Line 17757: /* Full chip erase is fastest, typically takes 200s */
> Fair enough, I can start a thread on the mailing list exploring options. […]
The problem is that there is no common use-case to tune the list for.
Placing smaller blocks first is better for smaller changes, placing
bigger blocks first is better for bigger changes. We don't know in
advance what to expect.
My idea how to re-arrange things:
* Add an optional function to the programmer drivers that can check if a command is expected to succeed (or rather fail, the most obvious example is Intel's internal programmer that can be configured to only allow a specific set of SPI commands). With such a function, the list of block erasers to consider can be filtered at runtime.
* Once we know the set of block erasers that is expected to work, we can apply a heuristic that chooses the biggest block that won't unnecessarily erase unchanged data. Or maybe with a threshold, e.g. prefer 64K over 4K if >80% of the 4K blocks would get erased.
Well, maybe there is one low-hanging fruit: For the erase commandline
option (-E), we could iterate over the list in reverse order?
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55358 )
Change subject: dummyflasher: Replace another case of `sizeof(struct ...)`
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I meant to say, thank you, it is an honour for me!
You're welcome :) And let's say it was overdue anyway, the requirements
for the reviewers group[1] are not very high:
People who can +2 / -1 changes.
Contributors with more activity than a one-off commit.
My personal expectations may be higher, but you have exceeded those
too anyway ;) You have shown that you are able and willing to read.
A trait not common among people in that group Oo
[1] https://review.coreboot.org/admin/groups
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49255 )
Change subject: bitbang-spi.c: support clock polarity and phase
......................................................................
Patch Set 28:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/49255/comment/1eede23b_3763e24d
PS26, Line 11: may not be
> This "may not be" is rather vague. […]
I will not comment further on this review until this is answered.
File bitbang_spi.c:
https://review.coreboot.org/c/flashrom/+/49255/comment/88568544_ebde19db
PS26, Line 121: programmer_delay(master->half_period);
: bitbang_spi_set_sck_set_mosi(master, !cpol, (val >> i) & 1);
: programmer_delay(master->half_period);
: bitbang_spi_set_sck(master, cpol);
> The hardware logic only requires that the data state is stable after the clock changes. […]
Hmm, what can I say more? Please have a careful look at the diagrams
in the Wikipedia article you linked and the datasheet of the chip you
used for testing.
Long story short, your (later corrected) order of signal changes is
eventually correct. But your delays are 100% off. You also have to
account for programmer drivers that change MOSI and CLK at once in
bitbang_spi_set_sck_set_mosi().
If you continue trying to correct your code, please also include
logic-analyzer traces before/after the patch and test programming
speed as well, so no prior, precious optimizations to this code
are lost.
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55295 )
Change subject: tests: Do not build a test if its driver is not built
......................................................................
Patch Set 2:
(1 comment)
File tests/init_shutdown.c:
https://review.coreboot.org/c/flashrom/+/55295/comment/57330655_0e6c3643
PS1, Line 35: #if CONFIG_DUMMY == 1
: void dummy_init_and_shutdown_test_success(void **state)
: {
: run_lifecycle(state, PROGRAMMER_DUMMY, "bus=parallel+lpc+fwh+spi");
: }
: #endif /* CONFIG_DUMMY */
> Right, this would actually benefit from removing the #if's from `programmer.h`. […]
Ok, great, I will rebase and try - and so marking comment unresolved until this is done.
I will be off for next week, then return back and do everything.
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Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/49264
to look at the new patch set (#16).
Change subject: bitbang_spi.c: fix spi sequence in time and rename
......................................................................
bitbang_spi.c: fix spi sequence in time and rename
SPI write operation requires the change of mosi before the change of
sck. For this reason, the interface set_sck_set_mosi was rename to
set_mosi_set_sck. And the sequence in time bug was corrected.
Change-Id: I107803afef044996c94ebfaf0b0e0040cea9f8c1
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M bitbang_spi.c
M developerbox_spi.c
M programmer.h
3 files changed, 9 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/49264/16
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