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Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/49264
to look at the new patch set (#15).
Change subject: bitbang_spi.c: fix spi sequence in time and rename
......................................................................
bitbang_spi.c: fix spi sequence in time and rename
SPI write operation requires the change of mosi before the change of
sck. For this reason, the interface set_sck_set_mosi was rename to
set_mosi_set_sck. And the sequence in time bug was corrected.
Change-Id: I107803afef044996c94ebfaf0b0e0040cea9f8c1
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M bitbang_spi.c
M developerbox_spi.c
M programmer.h
3 files changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/64/49264/15
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Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/49255
to look at the new patch set (#28).
Change subject: bitbang-spi.c: support clock polarity and phase
......................................................................
bitbang-spi.c: support clock polarity and phase
SPI has four modes, which are determined by Clock polarity and Clock
phase. See https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_an…
for details. The previous code only supports one mode and may not be
able to handle some special spi flash. This patch uses spi's mode0 by
default to be consistent with the previous code.
TEST=build and run flashrom with sysfsgpio on raspberrypi to read W25Q128.V
Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M bitbang_spi.c
1 file changed, 69 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/49255/28
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Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/49262
to look at the new patch set (#25).
Change subject: bitbang_spi.c: fix bitbang_spi_send_command to make the delay symmetric
......................................................................
bitbang_spi.c: fix bitbang_spi_send_command to make the delay symmetric
This patch is used to make the following delays as equal as possible:
delay from getting the bus to enabling the chip
delay from disabling the chip to releasing the bus
delay from enabling the chip to the start of communication
delay from ending communication to the disabling of the chip
Change-Id: Icf8b65aed20244ccffc231da2c599c6ca1796104
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M bitbang_spi.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/49262/25
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Xiang W has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49255 )
Change subject: bitbang-spi.c: support clock polarity and phase
......................................................................
Patch Set 27:
(5 comments)
File bitbang_spi.c:
https://review.coreboot.org/c/flashrom/+/49255/comment/a66c18ba_b05abecb
PS26, Line 34: data transmission
> Technically, it's the data sampling (or capturing, as Wikipedia puts it) […]
Done
https://review.coreboot.org/c/flashrom/+/49255/comment/88c2f26b_d1c3f969
PS26, Line 96: bitbang_spi_set_sck(master, !cpol);
> The first clock change always needs to happen with a delay after […]
There is no need to operate CS when sending each byte, the operation of CS is in bitbang_spi_send_command
https://review.coreboot.org/c/flashrom/+/49255/comment/ecce7cf0_1f0f1bb9
PS26, Line 121: programmer_delay(master->half_period);
: bitbang_spi_set_sck_set_mosi(master, !cpol, (val >> i) & 1);
: programmer_delay(master->half_period);
: bitbang_spi_set_sck(master, cpol);
> This does not look right and is probably what led to the follow up commit. […]
The hardware logic only requires that the data state is stable after the clock changes.
The following sequence is correct:
- delay
- set mosi
- first edge
- delay
- second edge
So I submitted a patch to fix bitbang_spi_set_sck_set_mosi:https://review.coreboot.org/c/flashrom/+/49264…https://review.coreboot.org/c/flashrom/+/49255/comment/210f26a2_24685a38
PS26, Line 184: if (strlen(mode)) {
> So an empty string is not reported as error?
Done
https://review.coreboot.org/c/flashrom/+/49255/comment/474d8d1a_b766bb26
PS26, Line 187: mode == endptr
> This does not account for trailing garbage. It's better to check for […]
Done
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Hello build bot (Jenkins), Stefan Reinauer, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/49255
to look at the new patch set (#27).
Change subject: bitbang-spi.c: support clock polarity and phase
......................................................................
bitbang-spi.c: support clock polarity and phase
SPI has four modes, which are determined by Clock polarity and Clock
phase. See https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Clock_polarity_an…
for details. The previous code only supports one mode and may not be
able to handle some special spi flash. This patch uses spi's mode0 by
default to be consistent with the previous code.
TEST=build and run flashrom with sysfsgpio on raspberrypi to read W25Q128.V
Change-Id: I04c1dfe132d756119229b27c3cd611d1be1abc8d
Signed-off-by: Xiang Wang <merle(a)hardenedlinux.org>
---
M bitbang_spi.c
1 file changed, 65 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/49255/27
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David Bartley has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54968 )
Change subject: flashchips: add support for Winbond W25Q01JV
......................................................................
Patch Set 3:
(7 comments)
Patchset:
PS3:
PTAL
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/54968/comment/6c32e1ab_addeeaf7
PS1, Line 17745: 5
> The `5` seems spurious?
Done
https://review.coreboot.org/c/flashrom/+/54968/comment/b6d3b189_ac73f07a
PS1, Line 17745: W25Q501V
> Flash chip entries are sorted alphabetically by vendor and name. […]
Done
https://review.coreboot.org/c/flashrom/+/54968/comment/4e13b08f_4a3bd4d6
PS1, Line 17757: /* Full chip erase is fastest, typically takes 200s */
> Block erasers for the other flash chip entries are intentionally sorted in ascending block size. […]
Fair enough, I can start a thread on the mailing list exploring options. FTR, it takes almost an hour to erase using the 4kb block eraser...
https://review.coreboot.org/c/flashrom/+/54968/comment/673b435b_439d368b
PS1, Line 17781: spi_prettyprint_status_register_plain
> spi_prettyprint_status_register_bp3_srwd
Done
https://review.coreboot.org/c/flashrom/+/54968/comment/fbbbfe10_e49e2591
PS1, Line 17782: spi_disable_blockprotect
> spi_disable_blockprotect_bp3_srwd
Done
https://review.coreboot.org/c/flashrom/+/54968/comment/4f3b7ddc_50dca430
PS1, Line 17788:
> nit: use only one blank line (there's two right now)
Done
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/52877 )
Change subject: buspirate_spi.c: Separate shutdown from failed init cleanup
......................................................................
Patch Set 5:
(1 comment)
File buspirate_spi.c:
https://review.coreboot.org/c/flashrom/+/52877/comment/0c5958ac_55421c9c
PS4, Line 620: ret = 1;
> Actually yes, return values come from serialport_write and serialport_read, and those seems to retur […]
So yes, I will do this and also suggestion from CB:52958. Just wanted to say I am off for next week, and then return back and do everything.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55403 )
Change subject: lspcon: restart MPU on programmer shutdown
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File lspcon_i2c_spi.c:
https://review.coreboot.org/c/flashrom/+/55403/comment/860483c5_f512210f
PS1, Line 314: (unsigned)1e8
h-how does this work
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/52958 )
Change subject: buspirate_spi.c: Refactor singleton states into reentrant pattern
......................................................................
Patch Set 4:
(1 comment)
File buspirate_spi.c:
https://review.coreboot.org/c/flashrom/+/52958/comment/2d1f9618_c15b328f
PS4, Line 315: int buspirate_spi_init(void)
> Perhaps a bit out of scope for this commit however you may wish to add one or two change before this […]
I agree it is large. Also I agree this is out of scope for this commit. So just to confirm, you suggest to add one or two patches before this one in this chain, do I understand correctly?
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Change subject: buspirate_spi.c: Separate shutdown from failed init cleanup
......................................................................
Patch Set 4:
(1 comment)
File buspirate_spi.c:
https://review.coreboot.org/c/flashrom/+/52877/comment/b46394a6_cd22575f
PS4, Line 620: ret = 1;
> For another patch: We could get rid of these `ret = 1;` statements and just use the existing non-zer […]
Actually yes, return values come from serialport_write and serialport_read, and those seems to return 1s for any error.
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