flashrom-gerrit June 2021

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Change in flashrom[master]: nic3com.c: Refactor singleton states into reentrant pattern
by Edward O'Callaghan (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55106 ) Change subject: nic3com.c: Refactor singleton states into reentrant pattern ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/55106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1c3e4836760cc9f4f9a0bd4294e8d2407b150566 Gerrit-Change-Number: 55106 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 03:25:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: nic3com.c: Allocate data and register shutdown at the end of init
by Edward O'Callaghan (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55107 ) Change subject: nic3com.c: Allocate data and register shutdown at the end of init ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/55107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9834b82650cd070556cf82207796bc6bd6b31b28 Gerrit-Change-Number: 55107 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 03:22:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: nicrealtek.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 01 Jun '21

01 Jun '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/55108 ) Change subject: nicrealtek.c: Refactor singleton states into reentrant pattern ...................................................................... nicrealtek.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the par_master data field for the life-time of the driver. This is one of the steps on the way to move par_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: If0cb0fefb53b2c6bb65a85f4c8dc6f323954dd0c Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M nicrealtek.c 1 file changed, 31 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/55108/1 diff --git a/nicrealtek.c b/nicrealtek.c index 788c088..544abab 100644 --- a/nicrealtek.c +++ b/nicrealtek.c @@ -24,8 +24,11 @@ #define PCI_VENDOR_ID_REALTEK 0x10ec #define PCI_VENDOR_ID_SMC1211 0x1113 -static uint32_t io_base_addr = 0; -static int bios_rom_addr, bios_rom_data; +struct nicrealtek_data { + uint32_t io_base_addr; + int bios_rom_addr; + int bios_rom_data; +}; const struct dev_entry nics_realtek[] = { {0x10ec, 0x8139, OK, "Realtek", "RTL8139/8139C/8139C+"}, @@ -37,38 +40,41 @@ static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { + struct nicrealtek_data *data = flash->mst->par.data; + /* Output addr and data, set WE to 0, set OE to 1, set CS to 0, * enable software access. */ OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24), - io_base_addr + bios_rom_addr); + data->io_base_addr + data->bios_rom_addr); /* Output addr and data, set WE to 1, set OE to 1, set CS to 1, * enable software access. */ OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), - io_base_addr + bios_rom_addr); + data->io_base_addr + data->bios_rom_addr); } static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr) { + struct nicrealtek_data *data = flash->mst->par.data; uint8_t val; /* FIXME: Can we skip reading the old data and simply use 0? */ /* Read old data. */ - val = INB(io_base_addr + bios_rom_data); + val = INB(data->io_base_addr + data->bios_rom_data); /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0, * enable software access. */ OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24), - io_base_addr + bios_rom_addr); + data->io_base_addr + data->bios_rom_addr); /* Read new data. */ - val = INB(io_base_addr + bios_rom_data); + val = INB(data->io_base_addr + data->bios_rom_data); /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1, * enable software access. */ OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24), - io_base_addr + bios_rom_addr); + data->io_base_addr + data->bios_rom_addr); return val; } @@ -87,12 +93,16 @@ static int nicrealtek_shutdown(void *data) { /* FIXME: We forgot to disable software access again. */ + free(data); return 0; } int nicrealtek_init(void) { struct pci_dev *dev = NULL; + uint32_t io_base_addr = 0; + int bios_rom_addr; + int bios_rom_data; if (rget_io_perms()) return 1; @@ -119,10 +129,21 @@ break; } - if (register_shutdown(nicrealtek_shutdown, NULL)) + struct nicrealtek_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for PAR master data\n"); return 1; + } + data->io_base_addr = io_base_addr; + data->bios_rom_addr = bios_rom_addr; + data->bios_rom_data = bios_rom_data; - register_par_master(&par_master_nicrealtek, BUS_PARALLEL, NULL); + if (register_shutdown(nicrealtek_shutdown, data)) { + free(data); + return 1; + } + + register_par_master(&par_master_nicrealtek, BUS_PARALLEL, data); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/55108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If0cb0fefb53b2c6bb65a85f4c8dc6f323954dd0c Gerrit-Change-Number: 55108 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ogp_spi.c: Refactor singleton states into reentrant pattern
by Edward O'Callaghan (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54996 ) Change subject: ogp_spi.c: Refactor singleton states into reentrant pattern ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6b8f6ecd7c9949ffb4098bf56a8936393283382f Gerrit-Change-Number: 54996 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 01:52:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: pony_spi.c: Refactor singleton states into reentrant pattern
by Edward O'Callaghan (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Nico Huber, Angel Pons, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/54997 ) Change subject: pony_spi.c: Refactor singleton states into reentrant pattern ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/54997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Icf1125dadcdaa287ebe3c07ca95adb770bb19412 Gerrit-Change-Number: 54997 Gerrit-PatchSet: 3 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 01:52:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in flashrom[master]: nic3com.c: Allocate data and register shutdown at the end of init
by Anastasia Klimchuk (Code Review) 01 Jun '21

01 Jun '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/55107 ) Change subject: nic3com.c: Allocate data and register shutdown at the end of init ...................................................................... nic3com.c: Allocate data and register shutdown at the end of init This unlocks API change which plans to move register_shutdown inside register master API, see https://review.coreboot.org/c/flashrom/+/51761 BUG=b:185191942 TEST=builds Change-Id: I9834b82650cd070556cf82207796bc6bd6b31b28 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M nic3com.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/55107/1 diff --git a/nic3com.c b/nic3com.c index 4266413..17cf406 100644 --- a/nic3com.c +++ b/nic3com.c @@ -139,6 +139,8 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); + max_rom_decode.parallel = 128 * 1024; + struct nic3com_data *data = calloc(1, sizeof(*data)); if (!data) { msg_perr("Unable to allocate space for PAR master data\n"); @@ -152,8 +154,6 @@ free(data); return 1; } - - max_rom_decode.parallel = 128 * 1024; register_par_master(&par_master_nic3com, BUS_PARALLEL, data); return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/55107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I9834b82650cd070556cf82207796bc6bd6b31b28 Gerrit-Change-Number: 55107 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: nic3com.c: Refactor singleton states into reentrant pattern
by Anastasia Klimchuk (Code Review) 01 Jun '21

01 Jun '21

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/55106 ) Change subject: nic3com.c: Refactor singleton states into reentrant pattern ...................................................................... nic3com.c: Refactor singleton states into reentrant pattern Move global singleton states into a struct and store within the par_master data field for the life-time of the driver. This is one of the steps on the way to move par_master data memory management behind the initialisation API, for more context see other patches under the same topic "register_master_api". BUG=b:185191942 TEST=builds Change-Id: I1c3e4836760cc9f4f9a0bd4294e8d2407b150566 Signed-off-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M nic3com.c 1 file changed, 36 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/55106/1 diff --git a/nic3com.c b/nic3com.c index d60b03c..4266413 100644 --- a/nic3com.c +++ b/nic3com.c @@ -29,9 +29,11 @@ #define PCI_VENDOR_ID_3COM 0x10b7 -static uint32_t io_base_addr = 0; -static uint32_t internal_conf; -static uint16_t id; +struct nic3com_data { + uint32_t io_base_addr; + uint32_t internal_conf; + uint16_t id; +}; const struct dev_entry nics_3com[] = { /* 3C90xB */ @@ -56,15 +58,19 @@ static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr) { - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - OUTB(val, io_base_addr + BIOS_ROM_DATA); + struct nic3com_data *data = flash->mst->par.data; + + OUTL((uint32_t)addr, data->io_base_addr + BIOS_ROM_ADDR); + OUTB(val, data->io_base_addr + BIOS_ROM_DATA); } static uint8_t nic3com_chip_readb(const struct flashctx *flash, const chipaddr addr) { - OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR); - return INB(io_base_addr + BIOS_ROM_DATA); + struct nic3com_data *data = flash->mst->par.data; + + OUTL((uint32_t)addr, data->io_base_addr + BIOS_ROM_ADDR); + return INB(data->io_base_addr + BIOS_ROM_DATA); } static const struct par_master par_master_nic3com = { @@ -78,22 +84,29 @@ .chip_writen = fallback_chip_writen, }; -static int nic3com_shutdown(void *data) +static int nic3com_shutdown(void *par_data) { + struct nic3com_data *data = par_data; + const uint16_t id = data->id; + /* 3COM 3C90xB cards need a special fixup. */ if (id == 0x9055 || id == 0x9001 || id == 0x9004 || id == 0x9005 || id == 0x9006 || id == 0x900a || id == 0x905a || id == 0x9058) { /* Select register window 3 and restore the receiver status. */ - OUTW(SELECT_REG_WINDOW + 3, io_base_addr + INT_STATUS); - OUTL(internal_conf, io_base_addr + INTERNAL_CONFIG); + OUTW(SELECT_REG_WINDOW + 3, data->io_base_addr + INT_STATUS); + OUTL(data->internal_conf, data->io_base_addr + INTERNAL_CONFIG); } + free(data); return 0; } int nic3com_init(void) { struct pci_dev *dev = NULL; + uint32_t io_base_addr = 0; + uint32_t internal_conf = 0; + uint16_t id; if (rget_io_perms()) return 1; @@ -126,11 +139,22 @@ */ OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); - if (register_shutdown(nic3com_shutdown, NULL)) + struct nic3com_data *data = calloc(1, sizeof(*data)); + if (!data) { + msg_perr("Unable to allocate space for PAR master data\n"); return 1; + } + data->io_base_addr = io_base_addr; + data->internal_conf = internal_conf; + data->id = id; + + if (register_shutdown(nic3com_shutdown, data)) { + free(data); + return 1; + } max_rom_decode.parallel = 128 * 1024; - register_par_master(&par_master_nic3com, BUS_PARALLEL, NULL); + register_par_master(&par_master_nic3com, BUS_PARALLEL, data); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/55106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1c3e4836760cc9f4f9a0bd4294e8d2407b150566 Gerrit-Change-Number: 55106 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: newchange

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flashrom-gerrit June 2021