July 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: [stlinkv3_spi]Added missing line ends, and added a note about the fir...
by Miklós Márton (Code Review) 04 Aug '20

04 Aug '20

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43900 ) Change subject: [stlinkv3_spi]Added missing line ends, and added a note about the first version of the updater which contains the necessary V3 bridge feature. ...................................................................... [stlinkv3_spi]Added missing line ends, and added a note about the first version of the updater which contains the necessary V3 bridge feature. Change-Id: Ib45efa37b192489bdfe26f1f0fd1d81035a08c70 Signed-off-by: Miklós Márton <martonmiklosqdev(a)gmail.com> --- M stlinkv3_spi.c 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/00/43900/1 diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c index ae865be..c75f7db 100644 --- a/stlinkv3_spi.c +++ b/stlinkv3_spi.c @@ -253,21 +253,22 @@ enum fw_version_check_result fw_check_result; if (stlinkv3_check_version(&fw_check_result)) { - msg_perr("Failed to query FW version"); + msg_perr("Failed to query FW version\n"); return -1; } if (fw_check_result != FW_VERSION_OK) { msg_pinfo("Your STLink V3 has too old version of the bridge interface\n" - "Please update the firmware with the STSW-LINK007 which can be downloaded from here:\n" - "https://www.st.com/en/development-tools/stsw-link007.html"); + "Please update the firmware with version 2.33.25 or newer of the STSW-LINK007\n" + "which can be downloaded from here:\n" + "https://www.st.com/en/development-tools/stsw-link007.html\n"); return -1; } if (stlinkv3_spi_calc_prescaler(reqested_freq_in_kHz, &prescaler, &SCK_freq_in_kHz)) { - msg_perr("Failed to calculate SPI clock prescaler"); + msg_perr("Failed to calculate SPI clock prescaler\n"); return -1; } msg_pinfo("SCK frequency set to %d kHz\n", SCK_freq_in_kHz); -- To view, visit https://review.coreboot.org/c/flashrom/+/43900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib45efa37b192489bdfe26f1f0fd1d81035a08c70 Gerrit-Change-Number: 43900 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call
by Simon Buhrow (Code Review) 27 Jul '20

27 Jul '20

Simon Buhrow has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/40477 ) Change subject: ft2232_spi.c: Pack WREN and op in one ftdi_write_data() call ...................................................................... Patch Set 14: Just a try to show what effect the change has: To do one PageProgram the Flash needs the following cmds/information (PROG=PageProgramCmd): Flash-Cmds: JEDEC_WREN + PROG + ADDR + DATA As flashrom communicates with the FTDI, there are additional FTDI-cmds necessary, of course. This gives the following calls: ft2232_spi_send_command(XX, XX, ['JEDEC_WREN'], XX) before: -> send_buf(XX, [FTDI-CMD + 'JEDEC_WREN' + FTDI-CMD], 10) now: -> save i and buf as they are static, no further function call; buf = [FTDI-CMD + 'JEDEC_WREN' + FTDI-CMD] ft2232_spi_send_command(XX, XX, ['PROG', 'ADDR', 'DATA'], XX) before: -> send_buf(XX, [FTDI-CMD + 'PROG' + 'ADDR' + 'DATA' + FTDI-CMD], 270) now: -> send_buf(XX, [FTDI-CMD + 'JEDEC_WREN' + FTDI-CMD + FTDI-CMD + 'PROG' + 'ADDR' + 'DATA' + FTDI-CMD], 280) => saves one send_buf/ftdi_write_data call every page-program or erase action. -- To view, visit https://review.coreboot.org/c/flashrom/+/40477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ie4a07499ec5ef0af23818593f45dc427285a9e8a Gerrit-Change-Number: 40477 Gerrit-PatchSet: 14 Gerrit-Owner: Simon Buhrow Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 27 Jul 2020 14:16:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in flashrom[master]: ich_descriptors.h: Upstream PCH100+ region comment
by Edward O'Callaghan (Code Review) 26 Jul '20

26 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43896 ) Change subject: ich_descriptors.h: Upstream PCH100+ region comment ...................................................................... ich_descriptors.h: Upstream PCH100+ region comment Useful information we should extract out of the chromium fork of flashrom and ingest into upstream. Change-Id: I246c56aa86bb44f27c5934ab5883f555a8307784 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ich_descriptors.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/43896/1 diff --git a/ich_descriptors.h b/ich_descriptors.h index c6bf5d8..98535e1 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -234,6 +234,14 @@ :3; }; /* From Skylake on */ + /* + * Flash Descriptor Master Access settings for PCH100+ + * + * [31:20] Master Region Write Access (regions 11:0) + * [19:8] Master Region Read Access (regions 11:0) + * [7:4] Extended Region Write Access (regions 15:12) + * [3:0] Extended Region Read access (regions 15:12) + */ struct { uint32_t ext_read :4, ext_write :4, -- To view, visit https://review.coreboot.org/c/flashrom/+/43896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I246c56aa86bb44f27c5934ab5883f555a8307784 Gerrit-Change-Number: 43896 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Take chromiums flash desc sec override msg
by Edward O'Callaghan (Code Review) 26 Jul '20

26 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43895 ) Change subject: ichspi.c: Take chromiums flash desc sec override msg ...................................................................... ichspi.c: Take chromiums flash desc sec override msg Line wrapped and a little more descriptive. Change-Id: I1043bed042f5507788ed2b417bd44d0fe3dc0aa6 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/43895/1 diff --git a/ichspi.c b/ichspi.c index 1cc1cd7..d9f13ef 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1849,9 +1849,11 @@ if (tmp2 & HSFS_FDV) desc_valid = 1; if (!(tmp2 & HSFS_FDOPSS) && desc_valid) - msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n" - "the Master Section of the flash descriptor are NOT in effect. Please note\n" - "that Protected Range (PR) restrictions still apply.\n"); + msg_pinfo("The Flash Descriptor Security Override " + "Strap-Pin is set. Restrictions implied\n" + "by the FRAP and FREG registers are NOT in " + "effect. Please note that Protected\n" + "Range (PR) restrictions still apply.\n"); ich_init_opcodes(ich_gen); if (desc_valid) { -- To view, visit https://review.coreboot.org/c/flashrom/+/43895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1043bed042f5507788ed2b417bd44d0fe3dc0aa6 Gerrit-Change-Number: 43895 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Consolidate ich_spi_mode select into a switch stmt
by Edward O'Callaghan (Code Review) 26 Jul '20

26 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43894 ) Change subject: ichspi.c: Consolidate ich_spi_mode select into a switch stmt ...................................................................... ichspi.c: Consolidate ich_spi_mode select into a switch stmt Change-Id: I35535c3dac9fa796d204d60e5fc72a7d5f85d706 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/94/43894/1 diff --git a/ichspi.c b/ichspi.c index 4dbe69a..1cc1cd7 100644 --- a/ichspi.c +++ b/ichspi.c @@ -2002,16 +2002,18 @@ ich_spi_mode = ich_hwseq; } - if (ich_spi_mode == ich_auto && - (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || - ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { - msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); - ich_spi_mode = ich_hwseq; - } - - if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { - msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); - ich_spi_mode = ich_hwseq; + if (ich_spi_mode == ich_auto) { + switch (ich_gen) { + case CHIPSET_100_SERIES_SUNRISE_POINT: + case CHIPSET_300_SERIES_CANNON_POINT: + case CHIPSET_APOLLO_LAKE: + msg_pdbg("Enabling hardware sequencing by default " + "for 100+ series PCH.\n"); + ich_spi_mode = ich_hwseq; + break; + default: + break; + } } if (ich_spi_mode == ich_hwseq) { -- To view, visit https://review.coreboot.org/c/flashrom/+/43894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I35535c3dac9fa796d204d60e5fc72a7d5f85d706 Gerrit-Change-Number: 43894 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: Add support for Winbond W25X05CL
by Miklós Márton (Code Review) 26 Jul '20

26 Jul '20

Miklós Márton has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43573 ) Change subject: Add support for Winbond W25X05CL ...................................................................... Add support for Winbond W25X05CL This commit adds support for the Winbond W25X05CL SPI flash chip. The Winbond W25X05CL is a 512K-BIT SPI flash chip with 4KB sectors. I have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL flash chip using a test clip. Reading, erasing, and writing all function as expected. Datasheet: http://www.winbond.com/resource-files/w25x05cl_f%2004252017.pdf Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc Signed-off-by: Jacob Appelbaum <jacob(a)appelbaum.net> --- M flashchips.c M flashchips.h 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/43573/1 diff --git a/flashchips.c b/flashchips.c index 48405fe..3d8042d 100644 --- a/flashchips.c +++ b/flashchips.c @@ -17329,6 +17329,38 @@ { .vendor = "Winbond", + .name = "W25X05", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25X05, + .total_size = 64, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 2} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_d8, + } + }, + .printlock = spi_prettyprint_status_register_plain, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2300, 3600}, + }, + + { + .vendor = "Winbond", .name = "W25X10", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index c58595d..f6e2588 100644 --- a/flashchips.h +++ b/flashchips.h @@ -917,6 +917,7 @@ #define WINBOND_NEX_W25P80 0x2014 #define WINBOND_NEX_W25P16 0x2015 #define WINBOND_NEX_W25P32 0x2016 +#define WINBOND_NEX_W25X05 0x3010 /* W25X05CL */ #define WINBOND_NEX_W25X10 0x3011 #define WINBOND_NEX_W25X20 0x3012 #define WINBOND_NEX_W25X40 0x3013 -- To view, visit https://review.coreboot.org/c/flashrom/+/43573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc Gerrit-Change-Number: 43573 Gerrit-PatchSet: 1 Gerrit-Owner: Miklós Márton <martonmiklosqdev(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: meson: fix compilation under uClibc-ng
by David Hendricks (Code Review) 21 Jul '20

21 Jul '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43599 ) Change subject: meson: fix compilation under uClibc-ng ...................................................................... meson: fix compilation under uClibc-ng fileno requires _POSIX_C_SOURCE to only be defined. nanosleep requires _POSIX_C_SOURCE to be defined to 199309L. strndup requires _POSIX_C_SOURCE to be defined to 200809L. Change-Id: Idb80937bb78e173eb03f2a0c0cdd8925fcd7bfa1 Signed-off-by: Rosen Penev <rosenp(a)gmail.com> --- M meson.build 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/43599/1 diff --git a/meson.build b/meson.build index 5374e87..ef7ac2c 100644 --- a/meson.build +++ b/meson.build @@ -25,7 +25,7 @@ cc = meson.get_compiler('c') add_project_arguments(cc.get_supported_arguments(warning_flags), language : 'c') add_project_arguments('-D_DEFAULT_SOURCE', language : 'c') -add_project_arguments('-D_POSIX_C_SOURCE', language : 'c') # required for fileno +add_project_arguments('-D_POSIX_C_SOURCE=200809L', language : 'c') # required for fileno, nanosleep, and strndup add_project_arguments('-D_BSD_SOURCE', language : 'c') # required for glibc < v2.19 add_project_arguments('-DFLASHROM_VERSION="' + meson.project_version() + '"', language : 'c') -- To view, visit https://review.coreboot.org/c/flashrom/+/43599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Idb80937bb78e173eb03f2a0c0cdd8925fcd7bfa1 Gerrit-Change-Number: 43599 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: endiantest: Fix #if expression
by David Hendricks (Code Review) 21 Jul '20

21 Jul '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43598 ) Change subject: endiantest: Fix #if expression ...................................................................... endiantest: Fix #if expression Without this, `gcc -E endiantest.c` can fail and return the incorrect endiannes as well as exiting with non-zero. Here is the actual error shown in the output: endiantest.c:2:31: error: #if with no expression #if __FLASHROM_LITTLE_ENDIAN__ I was able to reproduce this using gcc-6.3.0 and clang-4.0.1, but newer compilers didn't have this issue. Change-Id: Iba2febd861471ec821a494336e800c2564984332 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M endiantest.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/43598/1 diff --git a/endiantest.c b/endiantest.c index de44ec5..9766061 100644 --- a/endiantest.c +++ b/endiantest.c @@ -1,5 +1,5 @@ #include "platform.h" -#if __FLASHROM_LITTLE_ENDIAN__ +#if defined __FLASHROM_LITTLE_ENDIAN__ little #else big -- To view, visit https://review.coreboot.org/c/flashrom/+/43598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iba2febd861471ec821a494336e800c2564984332 Gerrit-Change-Number: 43598 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: raiden_debug_spi: add param for a custom reset setup
by Mary Ruthven (Code Review) 21 Jul '20

21 Jul '20

Mary Ruthven has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43527 ) Change subject: raiden_debug_spi: add param for a custom reset setup ...................................................................... raiden_debug_spi: add param for a custom reset setup Cr50 asserts EC_RST_L to flash the AP. Asserting EC_RST_L breaks flashing the AP on some boards. This change adds a custom_rst arg to tell cr50 not to assert any system reset signals during flash AP setup. BUG=b:154885210 BRANCH=none TEST=manual sudo flashrom -p raiden_debug_spi:target=EC -r sudo flashrom -p raiden_debug_spi:target=AP -r sudo flashrom -p raiden_debug_spi:target=AP,custom_rst=true -r sudo flashrom -p raiden_debug_spi:target=AP,custom_rst=bogus -r sudo flashrom -p raiden_debug_spi -r Signed-off-by: Mary Ruthven <mruthven(a)chromium.org> Change-Id: I2da26469120c5304bc129b5578fcb7ca805fc1d1 --- M raiden_debug_spi.c 1 file changed, 30 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/27/43527/1 diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index b55307a..6b3468e 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -136,17 +136,17 @@ }; enum raiden_debug_spi_request { - RAIDEN_DEBUG_SPI_REQ_ENABLE = 0x0000, - RAIDEN_DEBUG_SPI_REQ_DISABLE = 0x0001, - RAIDEN_DEBUG_SPI_REQ_ENABLE_AP = 0x0002, - RAIDEN_DEBUG_SPI_REQ_ENABLE_EC = 0x0003, - RAIDEN_DEBUG_SPI_REQ_ENABLE_H1 = 0x0004, - RAIDEN_DEBUG_SPI_REQ_RESET = 0x0005, - RAIDEN_DEBUG_SPI_REQ_BOOT_CFG = 0x0006, - RAIDEN_DEBUG_SPI_REQ_SOCKET = 0x0007, - RAIDEN_DEBUG_SPI_REQ_SIGNING_START = 0x0008, - RAIDEN_DEBUG_SPI_REQ_SIGNING_SIGN = 0x0009, - + RAIDEN_DEBUG_SPI_REQ_ENABLE = 0x0000, + RAIDEN_DEBUG_SPI_REQ_DISABLE = 0x0001, + RAIDEN_DEBUG_SPI_REQ_ENABLE_AP = 0x0002, + RAIDEN_DEBUG_SPI_REQ_ENABLE_EC = 0x0003, + RAIDEN_DEBUG_SPI_REQ_ENABLE_H1 = 0x0004, + RAIDEN_DEBUG_SPI_REQ_RESET = 0x0005, + RAIDEN_DEBUG_SPI_REQ_BOOT_CFG = 0x0006, + RAIDEN_DEBUG_SPI_REQ_SOCKET = 0x0007, + RAIDEN_DEBUG_SPI_REQ_SIGNING_START = 0x0008, + RAIDEN_DEBUG_SPI_REQ_SIGNING_SIGN = 0x0009, + RAIDEN_DEBUG_SPI_REQ_ENABLE_AP_CUSTOM = 0x000a, }; #define PACKET_HEADER_SIZE (2) @@ -452,6 +452,23 @@ return 0; } +static int get_ap_request_type(void) +{ + int ap_request = RAIDEN_DEBUG_SPI_REQ_ENABLE_AP; + char *custom_rst_str = extract_programmer_param("custom_rst"); + if (custom_rst_str) { + if (!strcasecmp(custom_rst_str, "true")) + ap_request = RAIDEN_DEBUG_SPI_REQ_ENABLE_AP_CUSTOM; + else { + msg_perr("Invalid custom rst param: %s\n", + custom_rst_str); + ap_request = -1; + } + } + free(custom_rst_str); + return ap_request; +} + static int get_target(void) { int request_enable = RAIDEN_DEBUG_SPI_REQ_ENABLE; @@ -459,7 +476,7 @@ char *target_str = extract_programmer_param("target"); if (target_str) { if (!strcasecmp(target_str, "ap")) - request_enable = RAIDEN_DEBUG_SPI_REQ_ENABLE_AP; + request_enable = get_ap_request_type(); else if (!strcasecmp(target_str, "ec")) request_enable = RAIDEN_DEBUG_SPI_REQ_ENABLE_EC; else { @@ -468,6 +485,7 @@ } } free(target_str); + msg_pinfo("Raiden target: %d\n", request_enable); return request_enable; } -- To view, visit https://review.coreboot.org/c/flashrom/+/43527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2da26469120c5304bc129b5578fcb7ca805fc1d1 Gerrit-Change-Number: 43527 Gerrit-PatchSet: 1 Gerrit-Owner: Mary Ruthven <mruthven(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: raiden_debug_spi: add missing USB_SPI requests
by Mary Ruthven (Code Review) 21 Jul '20

21 Jul '20

Mary Ruthven has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43525 ) Change subject: raiden_debug_spi: add missing USB_SPI requests ...................................................................... raiden_debug_spi: add missing USB_SPI requests Add the missing USB_SPI requests from platform/cr50 BUG=none BRANCH=none TEST=none Signed-off-by: Mary Ruthven <mruthven(a)chromium.org> Change-Id: I49c0c28566ed36af6fa03e23a878d19462c55f70 --- M raiden_debug_spi.c 1 file changed, 11 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/25/43525/1 diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index ac74c0b..b55307a 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -136,10 +136,17 @@ }; enum raiden_debug_spi_request { - RAIDEN_DEBUG_SPI_REQ_ENABLE = 0x0000, - RAIDEN_DEBUG_SPI_REQ_DISABLE = 0x0001, - RAIDEN_DEBUG_SPI_REQ_ENABLE_AP = 0x0002, - RAIDEN_DEBUG_SPI_REQ_ENABLE_EC = 0x0003, + RAIDEN_DEBUG_SPI_REQ_ENABLE = 0x0000, + RAIDEN_DEBUG_SPI_REQ_DISABLE = 0x0001, + RAIDEN_DEBUG_SPI_REQ_ENABLE_AP = 0x0002, + RAIDEN_DEBUG_SPI_REQ_ENABLE_EC = 0x0003, + RAIDEN_DEBUG_SPI_REQ_ENABLE_H1 = 0x0004, + RAIDEN_DEBUG_SPI_REQ_RESET = 0x0005, + RAIDEN_DEBUG_SPI_REQ_BOOT_CFG = 0x0006, + RAIDEN_DEBUG_SPI_REQ_SOCKET = 0x0007, + RAIDEN_DEBUG_SPI_REQ_SIGNING_START = 0x0008, + RAIDEN_DEBUG_SPI_REQ_SIGNING_SIGN = 0x0009, + }; #define PACKET_HEADER_SIZE (2) -- To view, visit https://review.coreboot.org/c/flashrom/+/43525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I49c0c28566ed36af6fa03e23a878d19462c55f70 Gerrit-Change-Number: 43525 Gerrit-PatchSet: 1 Gerrit-Owner: Mary Ruthven <mruthven(a)chromium.org> Gerrit-MessageType: newchange

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