July 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: spi: Allow cached ID bytes to be cleared
by Edward O'Callaghan (Code Review) 26 Aug '20

26 Aug '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41399 ) Change subject: spi: Allow cached ID bytes to be cleared ...................................................................... spi: Allow cached ID bytes to be cleared This does two things: 1. Removes the static variables from various ID functions and moves them to a single struct. 2. Adds a function to clear the struct. The idea of the original caching mechanism introduced years ago was simply to speed up probe_flash() by not issuing the same read ID commands dozens or hundreds of times for a single chip. That implementation assumed that we would only call probe_flash() once. However, there are cases when we want to call probe_flash() multiple times, for example, if using an external programmer and using different voltages (for probing the chip). This patch is extremely similar to the original works of: `commit 57b7524b1448189d3630d6c4735e60dbbdf14d51`. Author: David Hendricks <dhendrix(a)chromium.org> && `commit 7f7c711ee1a41649607f81f1533e5135fc1361fc`. Author: David Hendricks <dhendrix(a)chromium.org> BUG=b:15656443 BRANCH=none TEST=none Change-Id: I879cb08dbe66db9ab0c3b8a7f93b04fe1c5980f4 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M spi.h M spi25.c 2 files changed, 50 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/41399/1 diff --git a/spi.h b/spi.h index 3f45038..c1ca46a 100644 --- a/spi.h +++ b/spi.h @@ -192,4 +192,6 @@ #define SPI_FLASHROM_BUG -5 #define SPI_PROGRAMMER_ERROR -6 +void clear_spi_id_cache(void); + #endif /* !__SPI_H__ */ diff --git a/spi25.c b/spi25.c index fb91903..b4fbe6d 100644 --- a/spi25.c +++ b/spi25.c @@ -27,6 +27,26 @@ #include "programmer.h" #include "spi.h" +enum id_type { + RDID, + RDID4, + REMS, + RES2, + RES3, + NUM_ID_TYPES, +}; + +static struct { + int is_cached; + unsigned char bytes[4]; /* enough to hold largest ID type */ +} id_cache[NUM_ID_TYPES]; + +void clear_spi_id_cache(void) +{ + memset(id_cache, 0, sizeof(id_cache)); + return; +} + static int spi_rdid(struct flashctx *flash, unsigned char *readarr, int bytes) { static const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID }; @@ -138,18 +158,20 @@ static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) { const struct flashchip *chip = flash->chip; - unsigned char readarr[4]; uint32_t id1; uint32_t id2; + enum id_type idty = bytes == 3 ? RDID : RDID4; - const int ret = spi_rdid(flash, readarr, bytes); - if (ret == SPI_INVALID_LENGTH) - msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes); - if (ret) - return 0; + if (!id_cache[idty].is_cached) { + const int ret = spi_rdid(flash, id_cache[idty].bytes, bytes); + if (ret == SPI_INVALID_LENGTH) + msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes); + if (ret) + return 0; + id_cache[idty].is_cached = 1; + } - rdid_get_ids(readarr, bytes, &id1, &id2); - + rdid_get_ids(id_cache[idty].bytes, bytes, &id1, &id2); return compare_id(chip, id1, id2); } @@ -166,16 +188,16 @@ int probe_spi_rems(struct flashctx *flash) { const struct flashchip *chip = flash->chip; - unsigned char readarr[JEDEC_REMS_INSIZE]; uint32_t id1, id2; - if (spi_rems(flash, readarr)) { - return 0; + if (!id_cache[REMS].is_cached) { + if (spi_rems(flash, id_cache[REMS].bytes)) + return 0; + id_cache[REMS].is_cached = 1; } - id1 = readarr[0]; - id2 = readarr[1]; - + id1 = id_cache[REMS].bytes[0]; + id2 = id_cache[REMS].bytes[1]; return compare_id(chip, id1, id2); } @@ -222,16 +244,16 @@ int probe_spi_res2(struct flashctx *flash) { - unsigned char readarr[2]; uint32_t id1, id2; - if (spi_res(flash, readarr, 2)) { - return 0; + if (!id_cache[RES2].is_cached) { + if (spi_res(flash, id_cache[RES2].bytes, 2)) + return 0; + id_cache[RES2].is_cached = 1; } - id1 = readarr[0]; - id2 = readarr[1]; - + id1 = id_cache[RES2].bytes[0]; + id2 = id_cache[RES2].bytes[1]; msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) @@ -242,16 +264,16 @@ int probe_spi_res3(struct flashctx *flash) { - unsigned char readarr[3]; uint32_t id1, id2; - if (spi_res(flash, readarr, 3)) { - return 0; + if (!id_cache[RES3].is_cached) { + if (spi_res(flash, id_cache[RES3].bytes, 3)) + return 0; + id_cache[RES3].is_cached = 1; } - id1 = (readarr[0] << 8) | readarr[1]; - id2 = readarr[2]; - + id1 = (id_cache[RES3].bytes[0] << 8) | id_cache[RES3].bytes[1]; + id2 = id_cache[RES3].bytes[3]; msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); if (id1 != flash->chip->manufacture_id || id2 != flash->chip->model_id) -- To view, visit https://review.coreboot.org/c/flashrom/+/41399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I879cb08dbe66db9ab0c3b8a7f93b04fe1c5980f4 Gerrit-Change-Number: 41399 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: spi25.c: Factor out rdid_get_ids() and compare_id()
by Edward O'Callaghan (Code Review) 26 Aug '20

26 Aug '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41398 ) Change subject: spi25.c: Factor out rdid_get_ids() and compare_id() ...................................................................... spi25.c: Factor out rdid_get_ids() and compare_id() This is in preparation for implementing a cache for the probe results of RDID and REMS (3&4-byte variant) commands. The intention is to make probing of SPI rom's slightly faster, a few 10's of ms dependant upon the spi master used. BUG=b:15656443 BRANCH=none TEST=builds Change-Id: I1556e97a7c70425069e3d1dc0d5daf0aeec4e7bf Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M spi25.c 1 file changed, 30 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/41398/1 diff --git a/spi25.c b/spi25.c index 0a939e7..fb91903 100644 --- a/spi25.c +++ b/spi25.c @@ -93,19 +93,9 @@ return spi_send_command(flash, sizeof(cmd), 0, cmd, NULL); } -static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) +static void rdid_get_ids(unsigned char *readarr, int bytes, + uint32_t *id1, uint32_t *id2) { - const struct flashchip *chip = flash->chip; - unsigned char readarr[4]; - uint32_t id1; - uint32_t id2; - - const int ret = spi_rdid(flash, readarr, bytes); - if (ret == SPI_INVALID_LENGTH) - msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes); - if (ret) - return 0; - if (!oddparity(readarr[0])) msg_cdbg("RDID byte 0 parity violation. "); @@ -115,17 +105,20 @@ if (readarr[0] == 0x7f) { if (!oddparity(readarr[1])) msg_cdbg("RDID byte 1 parity violation. "); - id1 = (readarr[0] << 8) | readarr[1]; - id2 = readarr[2]; + *id1 = (readarr[0] << 8) | readarr[1]; + *id2 = readarr[2]; if (bytes > 3) { - id2 <<= 8; - id2 |= readarr[3]; + *id2 <<= 8; + *id2 |= readarr[3]; } } else { - id1 = readarr[0]; - id2 = (readarr[1] << 8) | readarr[2]; + *id1 = readarr[0]; + *id2 = (readarr[1] << 8) | readarr[2]; } +} +static int compare_id(const struct flashchip *chip, uint32_t id1, uint32_t id2) +{ msg_cdbg("%s: id1 0x%02x, id2 0x%02x\n", __func__, id1, id2); if (id1 == chip->manufacture_id && id2 == chip->model_id) @@ -142,6 +135,24 @@ return 0; } +static int probe_spi_rdid_generic(struct flashctx *flash, int bytes) +{ + const struct flashchip *chip = flash->chip; + unsigned char readarr[4]; + uint32_t id1; + uint32_t id2; + + const int ret = spi_rdid(flash, readarr, bytes); + if (ret == SPI_INVALID_LENGTH) + msg_cinfo("%d byte RDID not supported on this SPI controller\n", bytes); + if (ret) + return 0; + + rdid_get_ids(readarr, bytes, &id1, &id2); + + return compare_id(chip, id1, id2); +} + int probe_spi_rdid(struct flashctx *flash) { return probe_spi_rdid_generic(flash, 3); @@ -165,20 +176,7 @@ id1 = readarr[0]; id2 = readarr[1]; - msg_cdbg("%s: id1 0x%x, id2 0x%x\n", __func__, id1, id2); - - if (id1 == chip->manufacture_id && id2 == chip->model_id) - return 1; - - /* Test if this is a pure vendor match. */ - if (id1 == chip->manufacture_id && GENERIC_DEVICE_ID == chip->model_id) - return 1; - - /* Test if there is any vendor ID. */ - if (GENERIC_MANUF_ID == chip->manufacture_id && id1 != 0xff && id1 != 0x00) - return 1; - - return 0; + return compare_id(chip, id1, id2); } int probe_spi_res1(struct flashctx *flash) -- To view, visit https://review.coreboot.org/c/flashrom/+/41398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1556e97a7c70425069e3d1dc0d5daf0aeec4e7bf Gerrit-Change-Number: 41398 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...flashrom[master]: dediprog: Use 4BA page program without 0x12
by David Hendricks (Code Review) 25 Aug '20

25 Aug '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/30521 Change subject: dediprog: Use 4BA page program without 0x12 ...................................................................... dediprog: Use 4BA page program without 0x12 It's not clear exactly what the difference is between WRITE_MODE_4B_ADDR_256B_PAGE_PGM with and without _0x12 from the SF600 command spec, but the former seems to work more reliably. Tested using an SF600 (FW v7.2.21), IS25LP256D, W25Q256JV, and MX25L25735. Change-Id: I3cb37ec8838f5bb02948ed52b4a2906fa033cf83 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M dediprog.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/30521/1 diff --git a/dediprog.c b/dediprog.c index 2a190d2..303f1d5 100644 --- a/dediprog.c +++ b/dediprog.c @@ -398,7 +398,8 @@ } } else if (dedi_spi_cmd == WRITE_MODE_PAGE_PGM) { if (flash->chip->feature_bits & FEATURE_4BA_WRITE) { - data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12; +// data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM_0x12; + data_packet[3] = WRITE_MODE_4B_ADDR_256B_PAGE_PGM; data_packet[4] = JEDEC_BYTE_PROGRAM_4BA; use_4ba = true; } else if (flash->in_4ba_mode) { -- To view, visit https://review.coreboot.org/c/flashrom/+/30521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I3cb37ec8838f5bb02948ed52b4a2906fa033cf83 Gerrit-Change-Number: 30521 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: Makefile: Fix building on AArch64 NixOS
by Pyry Kontio (Code Review) 24 Aug '20

24 Aug '20

Pyry Kontio has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43140 ) Change subject: Makefile: Fix building on AArch64 NixOS ...................................................................... Makefile: Fix building on AArch64 NixOS Signed-off-by: Pyry Kontio <pyry.kontio(a)drasa.eu> Change-Id: Iaa4477a71e758cf9ecad2c22f3b77bc6508a3510 --- M Makefile 1 file changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/43140/1 diff --git a/Makefile b/Makefile index 803529f..6a2abd1 100644 --- a/Makefile +++ b/Makefile @@ -106,7 +106,8 @@ # IMPORTANT: The following line must be placed before TARGET_OS is ever used # (of course), but should come after any lines setting CC because the line # below uses CC itself. -override TARGET_OS := $(strip $(call debug_shell,$(CC) $(CPPFLAGS) -E os.h 2>/dev/null | grep -v '^\#' | grep '"' | cut -f 2 -d'"')) +override TARGET_OS := $(strip $(call debug_shell,$(CC) $(CPPFLAGS) -E os.h 2>/dev/null \ + | grep -v '^\#' | grep '"' | tail -1 | cut -f 2 -d'"')) ifeq ($(TARGET_OS), Darwin) override CPPFLAGS += -I/opt/local/include -I/usr/local/include @@ -460,8 +461,10 @@ # IMPORTANT: The following line must be placed before ARCH is ever used # (of course), but should come after any lines setting CC because the line # below uses CC itself. -override ARCH := $(strip $(call debug_shell,$(CC) $(CPPFLAGS) -E archtest.c 2>/dev/null | grep -v '^\#' | grep '"' | cut -f 2 -d'"')) -override ENDIAN := $(strip $(call debug_shell,$(CC) $(CPPFLAGS) -E endiantest.c 2>/dev/null | grep -v '^\#')) +override ARCH := $(strip $(call debug_shell,$(CC) $(CPPFLAGS) -E archtest.c 2>/dev/null \ + | grep -v '^\#' | grep '"' | tail -1 | cut -f 2 -d'"')) +override ENDIAN := $(strip $(call debug_shell,$(CC) $(CPPFLAGS) -E endiantest.c 2>/dev/null \ + | grep -v '^\#')) # Disable the internal programmer on unsupported architectures (everything but x86 and mipsel) ifneq ($(ARCH)-little, $(filter $(ARCH),x86 mips)-$(ENDIAN)) @@ -1253,12 +1256,12 @@ @printf "Target arch is " @# FreeBSD wc will output extraneous whitespace. @echo $(ARCH)|wc -w|grep -q '^[[:blank:]]*1[[:blank:]]*$$' || \ - ( echo "unknown. Aborting."; exit 1) + ( echo "unknown (\"$(ARCH)\"). Aborting."; exit 1) @printf "%s\n" '$(ARCH)' @printf "Target OS is " @# FreeBSD wc will output extraneous whitespace. @echo $(TARGET_OS)|wc -w|grep -q '^[[:blank:]]*1[[:blank:]]*$$' || \ - ( echo "unknown. Aborting."; exit 1) + ( echo "unknown (\"$(TARGET_OS)\"). Aborting."; exit 1) @printf "%s\n" '$(TARGET_OS)' ifeq ($(TARGET_OS), libpayload) @$(CC) --version 2>&1 | grep -q coreboot || \ -- To view, visit https://review.coreboot.org/c/flashrom/+/43140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iaa4477a71e758cf9ecad2c22f3b77bc6508a3510 Gerrit-Change-Number: 43140 Gerrit-PatchSet: 1 Gerrit-Owner: Pyry Kontio <pyry.kontio(a)drasa.eu> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Add W25Q256JW_IM
by David Hendricks (Code Review) 19 Aug '20

19 Aug '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42386 ) Change subject: flashchips: Add W25Q256JW_IM ...................................................................... flashchips: Add W25Q256JW_IM W25Q256JW has two variants, the W25Q256JW with device ID 0x6019 added in CB:40855 and the W25q256JW-IM which is added by this patch. Change-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M flashchips.c M flashchips.h 2 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/42386/1 diff --git a/flashchips.c b/flashchips.c index b4006df..dc43162 100644 --- a/flashchips.c +++ b/flashchips.c @@ -16808,6 +16808,53 @@ { .vendor = "Winbond", + .name = "W25Q256JW", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q256_JW, + .total_size = 32768, + .page_size = 256, + /* supports SFDP */ + /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {1700, 1950}, + }, + + { + .vendor = "Winbond", .name = "W25Q32.V", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/flashchips.h b/flashchips.h index e5ef390..2a0cf80 100644 --- a/flashchips.h +++ b/flashchips.h @@ -945,6 +945,7 @@ #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ #define WINBOND_NEX_W25Q64JW 0x8017 #define WINBOND_NEX_W25Q128_DTR 0x8018 /* W25Q128JW_DTR */ +#define WINBOND_NEX_W25Q256_JW 0x8019 /* W25Q256JW */ #define WINBOND_ID 0xDA /* Winbond */ #define WINBOND_W19B160BB 0x49 -- To view, visit https://review.coreboot.org/c/flashrom/+/42386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4 Gerrit-Change-Number: 42386 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: udelay.c: Enable providing delay calibration value through CLI
by Hrvoje Čavrak (Code Review) 17 Aug '20

17 Aug '20

Hrvoje Čavrak has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39841 ) Change subject: udelay.c: Enable providing delay calibration value through CLI ...................................................................... udelay.c: Enable providing delay calibration value through CLI This commit implements --delay option to retrieve and provide the calibration loop delay through the command line. The delay calibration procedure can take up to few seconds, which adds up when executed a number of times consecutively. Therefore, this provides a means to execute it only once, and then re-use the calibrated value on subsequent runs. Also, it implements a sanity check, expecting the value to land within 10% of the theoretical delay expectance, otherwise it ignores the provided value and runs the calibration procedure instead. modified: cli_classic.c modified: flashrom.8.tmpl modified: programmer.h modified: udelay.c Change-Id: Iea2a7f62300663bc0a32ed4abced57c8c55c90c8 Signed-off-by: Hrvoje Cavrak <hrvoje(a)hrvoje.org> --- M cli_classic.c M flashrom.8.tmpl M programmer.h M udelay.c 4 files changed, 51 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/41/39841/1 diff --git a/cli_classic.c b/cli_classic.c index 73cc417..f0842d4 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -63,6 +63,8 @@ " -o | --output <logfile> log output to <logfile>\n" " --flash-contents <ref-file> assume flash contents to be <ref-file>\n" " -L | --list-supported print supported devices\n" + " -d | --loop-delay <value> set loop delay calibration manually\n" + " --loop-delay get show loop delay calibration\n" #if CONFIG_PRINT_WIKI == 1 " -z | --list-supported-wiki print supported devices in wiki syntax\n" #endif @@ -118,6 +120,7 @@ int flash_name = 0, flash_size = 0; int read_it = 0, write_it = 0, erase_it = 0, verify_it = 0; int dont_verify_it = 0, dont_verify_all = 0, list_supported = 0, operation_specified = 0; + unsigned long provided_delay = 0; struct flashrom_layout *layout = NULL; enum programmer prog = PROGRAMMER_INVALID; enum { @@ -130,7 +133,7 @@ }; int ret = 0; - static const char optstring[] = "r:Rw:v:nNVEfc:l:i:p:Lzho:"; + static const char optstring[] = "r:Rw:v:nNVEfc:l:i:p:Lzho:d:"; static const struct option long_options[] = { {"read", 1, NULL, 'r'}, {"write", 1, NULL, 'w'}, @@ -156,6 +159,7 @@ {"help", 0, NULL, 'h'}, {"version", 0, NULL, 'R'}, {"output", 1, NULL, 'o'}, + {"delay", 1, NULL, 'd'}, {NULL, 0, NULL, 0}, }; @@ -362,6 +366,14 @@ } #endif /* STANDALONE */ break; + case 'd': + provided_delay = strtoul(strdup(optarg), NULL, 0); + if (!provided_delay) { + /* Make it easy for scripts to parse this by omitting anything else */ + msg_pinfo("%lu\n", get_calibration_value()); + exit(0); + } + break; default: cli_classic_abort_usage(NULL); break; @@ -454,7 +466,10 @@ } /* FIXME: Delay calibration should happen in programmer code. */ - myusec_calibrate_delay(); + if (provided_delay) + set_external_calibration(provided_delay); + else + myusec_calibrate_delay(); if (programmer_init(prog, pparam)) { msg_perr("Error: Programmer initialization failed.\n"); diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index fde98c0..c14f2de 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -50,7 +50,7 @@ [\fB\-E\fR|\fB\-r\fR <file>|\fB\-w\fR <file>|\fB\-v\fR <file>] [(\fB\-l\fR <file>|\fB\-\-ifd|\fB \-\-fmap\fR|\fB\-\-fmap-file\fR <file>) [\fB\-i\fR <image>]] [\fB\-n\fR] [\fB\-N\fR] [\fB\-f\fR])] - [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>] + [\fB\-V\fR[\fBV\fR[\fBV\fR]]] [\fB-o\fR <logfile>] [\fB-d\fR get | <value>] .SH DESCRIPTION .B flashrom is a utility for detecting, reading, writing, verifying and erasing flash @@ -364,6 +364,18 @@ .TP .B "\-R, \-\-version" Show version information and exit. +.TP +.B "\-d, \-\-loop\-delay" +Retrieve the loop calibration delay value or provide one externally. Calibrate +delay procedure can take a few seconds and for repeated execution on a large +number of hosts it can provide a significant overhead. Therefore, this argument +makes it possible to provide the calibration delay through the command line +option. + +To retrieve the value, run +.BR "flashrom \-\-loop\-delay get " "and to provide it during programming, add " +.BR "\-\-loop\-delay <value> " "to your command." + .SH PROGRAMMER-SPECIFIC INFORMATION Some programmer drivers accept further parameters to set programmer-specific parameters. These parameters are separated from the programmer name by a diff --git a/programmer.h b/programmer.h index 08500c6..a659a18 100644 --- a/programmer.h +++ b/programmer.h @@ -277,6 +277,8 @@ void myusec_calibrate_delay(void); void internal_sleep(unsigned int usecs); void internal_delay(unsigned int usecs); +unsigned long get_calibration_value(void); +void set_external_calibration(unsigned long external_micro); #if CONFIG_INTERNAL == 1 /* board_enable.c */ diff --git a/udelay.c b/udelay.c index 6c0efc4..90c4c9e 100644 --- a/udelay.c +++ b/udelay.c @@ -221,6 +221,25 @@ msg_pinfo("OK.\n"); } +void set_external_calibration(unsigned long external_micro) +{ + micro = external_micro; + unsigned long elapsed = measure_delay(100000); + /* Do a sanity check if the provided parameter makes loops fall within 10% of + * the desired value. Otherwise, ignore provided value and recalibrate. + */ + if (elapsed > 90000 && elapsed < 110000) + msg_pinfo("Provided delay is acceptable!\n"); + else + myusec_calibrate_delay(); +} + +unsigned long get_calibration_value(void) +{ + myusec_calibrate_delay(); + return micro; +} + /* Not very precise sleep. */ void internal_sleep(unsigned int usecs) { -- To view, visit https://review.coreboot.org/c/flashrom/+/39841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iea2a7f62300663bc0a32ed4abced57c8c55c90c8 Gerrit-Change-Number: 39841 Gerrit-PatchSet: 1 Gerrit-Owner: Hrvoje Čavrak <github(a)hrvoje.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: flashchips: Add support for Macronix MX25L5121E
by Steve Markgraf (Code Review) 04 Aug '20

04 Aug '20

Steve Markgraf has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43416 ) Change subject: flashchips: Add support for Macronix MX25L5121E ...................................................................... flashchips: Add support for Macronix MX25L5121E Change-Id: I881e2cda938083ba271b2ee0c457d2bbd8e1a766 Signed-off-by: Steve Markgraf <steve(a)steve-m.de> --- M flashchips.c M flashchips.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/43416/1 diff --git a/flashchips.c b/flashchips.c index 48405fe..996865a 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8543,6 +8543,44 @@ { .vendor = "Macronix", + .name = "MX25L5121E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25L5121E, + .total_size = 64, + .page_size = 32, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 16} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {64 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .printlock = spi_prettyprint_status_register_bp1_srwd, + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported, MX25L5121E supports dual I/O */ + .voltage = {2700, 3600}, /* 2.35-3.6V for MX25L5121E */ + }, + + { + .vendor = "Macronix", .name = "MX25L6405", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, diff --git a/flashchips.h b/flashchips.h index c58595d..597f659 100644 --- a/flashchips.h +++ b/flashchips.h @@ -482,6 +482,7 @@ * Generalplus SPI chips seem to be compatible with Macronix * and use the same set of IDs. */ #define MACRONIX_MX25L512 0x2010 /* Same as MX25L512E, MX25V512, MX25V512C */ +#define MACRONIX_MX25L5121E 0x2210 #define MACRONIX_MX25L1005 0x2011 /* Same as MX25L1005C, MX25L1006E */ #define MACRONIX_MX25L2005 0x2012 /* Same as MX25L2005C, MX25L2006E */ #define MACRONIX_MX25L4005 0x2013 /* Same as MX25L4005A, MX25L4005C, MX25L4006E */ -- To view, visit https://review.coreboot.org/c/flashrom/+/43416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I881e2cda938083ba271b2ee0c457d2bbd8e1a766 Gerrit-Change-Number: 43416 Gerrit-PatchSet: 1 Gerrit-Owner: Steve Markgraf <steve(a)steve-m.de> Gerrit-MessageType: newchange

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Change in flashrom[master]: lspcon_i2c_spi.c: Add debug message that shows the active block.
by Shiyu Sun (Code Review) 04 Aug '20

04 Aug '20

Shiyu Sun has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/41779 ) Change subject: lspcon_i2c_spi.c: Add debug message that shows the active block. ...................................................................... lspcon_i2c_spi.c: Add debug message that shows the active block. This is all for debug propose to verify A/B update work as expected. BUG=b:148746232 BRANCH=none TEST=flashrom -p lspcon_i2c_spi:bus=7 --flash-size -V verified the related message appears. Signed-off-by: Shiyu Sun <sshiyu(a)chromium.org> Change-Id: I1b3022542f98f114097c6f39254ef4c2cf188c90 --- M lspcon_i2c_spi.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/41779/1 diff --git a/lspcon_i2c_spi.c b/lspcon_i2c_spi.c index 7b9f1c0..e5e5dc9 100644 --- a/lspcon_i2c_spi.c +++ b/lspcon_i2c_spi.c @@ -27,6 +27,7 @@ #define REGISTER_ADDRESS (0x94 >> 1) #define PAGE_ADDRESS (0x9e >> 1) +#define ACTIVE_BLOCK_ADDRESS (0x9a >> 1) #define PAGE_SIZE 256 #define MAX_SPI_WAIT_RETRIES 1000 @@ -472,6 +473,27 @@ return ret; } +static void lspcon_i2c_spi_boot_block_info(int fd) +{ + uint8_t block_id = 0; + int ret = 0; + ret |= lspcon_i2c_spi_write_register(fd, 0xbc, 0xc0); + ret |= lspcon_i2c_spi_write_register(fd, 0xbc, 0x40); + ret |= lspcon_i2c_spi_write_register(fd, 0x8e, 0x00); + ret |= lspcon_i2c_spi_write_register(fd, 0x8f, 0x00); + struct timespec wait_10ms = { 0, (unsigned)1e7 }; + nanosleep(&wait_10ms, NULL); + + uint8_t command[] = { 0x0e }; + ret |= lspcon_i2c_spi_write_data(fd, ACTIVE_BLOCK_ADDRESS, command, 1); + ret |= lspcon_i2c_spi_read_data(fd, ACTIVE_BLOCK_ADDRESS, &block_id, 1); + if (ret) { + msg_pdbg("Failed to get LSPCON boot block information.\n"); + } else { + msg_pdbg("LSPCON is booting from block #%d.\n", block_id); + } +} + int lspcon_i2c_spi_init(void) { int lspcon_i2c_spi_bus = get_bus(); @@ -489,6 +511,9 @@ return ret; } + /* Show current activate block information for debug propose. */ + lspcon_i2c_spi_boot_block_info(fd); + struct lspcon_i2c_spi_data *data = calloc(1, sizeof(struct lspcon_i2c_spi_data)); if (!data) { msg_perr("Unable to allocate space for extra SPI master data.\n"); -- To view, visit https://review.coreboot.org/c/flashrom/+/41779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I1b3022542f98f114097c6f39254ef4c2cf188c90 Gerrit-Change-Number: 41779 Gerrit-PatchSet: 1 Gerrit-Owner: Shiyu Sun <sshiyu(a)google.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: git-hooks: Add check-style for pre-commit hook
by David Hendricks (Code Review) 04 Aug '20

04 Aug '20

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43602 ) Change subject: git-hooks: Add check-style for pre-commit hook ...................................................................... git-hooks: Add check-style for pre-commit hook This imports check-style and some related lint tools from coreboot for the pre-commit hook: - Add check-style rule to Makefile - Replace the current pre-commit hook with the one from coreboot, omitting lint-stable for the time being. - Import checkpatch.pl, along with certain dependencies (spelling.txt and const_structs.checkpatch) and .checkpatch.conf. - Add .clang-format from CB:38673. Change-Id: Ieb77aa1aa2911e081c69c93929a2f1c4430cd2b9 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- A .checkpatch.conf A .clang-format M Makefile M util/git-hooks/pre-commit A util/lint/check-style A util/lint/checkpatch.pl A util/lint/const_structs.checkpatch A util/lint/lint-007-checkpatch A util/lint/spelling.txt 9 files changed, 16,655 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/43602/1 -- To view, visit https://review.coreboot.org/c/flashrom/+/43602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ieb77aa1aa2911e081c69c93929a2f1c4430cd2b9 Gerrit-Change-Number: 43602 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: meson: Do not compile with -DSTANDALONE
by Richard Hughes (Code Review) 04 Aug '20

04 Aug '20

Richard Hughes has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42230 ) Change subject: meson: Do not compile with -DSTANDALONE ...................................................................... meson: Do not compile with -DSTANDALONE This enables the -o option which is used to collect logs for debugging. Change-Id: If6c12c682ba72cd519e30f1f8c96552322ff75e3 Signed-off-by: Richard Hughes <richard(a)hughsie.com> --- M meson.build 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/42230/1 diff --git a/meson.build b/meson.build index 5d8e630..4b00339 100644 --- a/meson.build +++ b/meson.build @@ -415,7 +415,6 @@ ], c_args : [ cargs, - '-DSTANDALONE', '-DCONFIG_DEFAULT_PROGRAMMER=PROGRAMMER_INVALID', '-DCONFIG_DEFAULT_PROGRAMMER_ARGS=""', ], -- To view, visit https://review.coreboot.org/c/flashrom/+/42230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If6c12c682ba72cd519e30f1f8c96552322ff75e3 Gerrit-Change-Number: 42230 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Hughes <richard(a)hughsie.com> Gerrit-MessageType: newchange

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