July 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: linux_spi: Add max_xfer programmer parameter
by David Hendricks (Code Review) July 19, 2020

July 19, 2020

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/42405 ) Change subject: linux_spi: Add max_xfer programmer parameter ...................................................................... linux_spi: Add max_xfer programmer parameter This enables the user to manually set the max transfer size, overriding the value that would otherwise come from sysfs or getpagesize(). Change-Id: Iea868c2e48e61e981472ebcc5e15aaaaf161cab4 Signed-off-by: David Hendricks <david.hendricks(a)gmail.com> --- M linux_spi.c 1 file changed, 48 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/42405/1 diff --git a/linux_spi.c b/linux_spi.c index 1ef8f2b..d804b48 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -46,7 +46,7 @@ static int fd = -1; #define BUF_SIZE_FROM_SYSFS "/sys/module/spidev/parameters/bufsiz" -static size_t max_kernel_buf_size; +static size_t max_xfer; static int linux_spi_shutdown(void *data); static int linux_spi_send_command(const struct flashctx *flash, unsigned int writecnt, @@ -110,6 +110,51 @@ } free(dev); + p = extract_programmer_param("max_xfer"); + if (p && strlen(p)) { + max_xfer = (uint32_t)strtoul(p, &endp, 0); + if (p == endp || max_xfer == 0) { + msg_perr("%s: invalid max transfer size: %s bytes\n", __func__, p); + free(p); + return 1; + } + } else { + /* Read max buffer size from sysfs, or use page size as fallback. */ + FILE *fp = fopen(BUF_SIZE_FROM_SYSFS, "r"); + if (!fp) { + msg_pwarn("Cannot open %s: %s.\n", BUF_SIZE_FROM_SYSFS, strerror(errno)); + goto out; + } + + char buf[10]; + if (!fgets(buf, sizeof(buf), fp)) { + if (feof(fp)) + msg_pwarn("Cannot read %s: file is empty.\n", BUF_SIZE_FROM_SYSFS); + else + msg_pwarn("Cannot read %s: %s.\n", BUF_SIZE_FROM_SYSFS, strerror(errno)); + fclose(fp); + goto out; + } + fclose(fp); + + long int tmp; + errno = 0; + tmp = strtol(buf, NULL, 0); + if ((tmp < 0) || errno) { + msg_pwarn("Buffer size %ld from %s seems wrong.\n", tmp, BUF_SIZE_FROM_SYSFS); + } else { + msg_pdbg("%s: Using value from %s as max_xfer size.\n", __func__, BUF_SIZE_FROM_SYSFS); + max_xfer = (size_t)tmp; + } + + if (!max_xfer) { + msg_pdbg("%s: Using page size as max_xfer size.\n", __func__); + max_xfer = (size_t)getpagesize(); + } + } + msg_pdbg("%s: max_xfer: %zu\n", __func__, max_xfer); + free(p); + if (register_shutdown(linux_spi_shutdown, NULL)) return 1; /* We rely on the shutdown function for cleanup from here on. */ @@ -133,43 +178,7 @@ return 1; } - /* Read max buffer size from sysfs, or use page size as fallback. */ - FILE *fp; - fp = fopen(BUF_SIZE_FROM_SYSFS, "r"); - if (!fp) { - msg_pwarn("Cannot open %s: %s.\n", BUF_SIZE_FROM_SYSFS, strerror(errno)); - goto out; - } - - char buf[10]; - if (!fgets(buf, sizeof(buf), fp)) { - if (feof(fp)) - msg_pwarn("Cannot read %s: file is empty.\n", BUF_SIZE_FROM_SYSFS); - else - msg_pwarn("Cannot read %s: %s.\n", BUF_SIZE_FROM_SYSFS, strerror(errno)); - goto out; - } - - long int tmp; - errno = 0; - tmp = strtol(buf, NULL, 0); - if ((tmp < 0) || errno) { - msg_pwarn("Buffer size %ld from %s seems wrong.\n", tmp, BUF_SIZE_FROM_SYSFS); - } else { - msg_pdbg("%s: Using value from %s as max buffer size.\n", __func__, BUF_SIZE_FROM_SYSFS); - max_kernel_buf_size = (size_t)tmp; - } - out: - if (fp) - fclose(fp); - - if (!max_kernel_buf_size) { - msg_pdbg("%s: Using page size as max buffer size.\n", __func__); - max_kernel_buf_size = (size_t)getpagesize(); - } - - msg_pdbg("%s: max_kernel_buf_size: %zu\n", __func__, max_kernel_buf_size); register_spi_master(&spi_master_linux); return 0; } @@ -225,13 +234,13 @@ { /* Older kernels use a single buffer for combined input and output data. So account for longest possible command + address, too. */ - return spi_read_chunked(flash, buf, start, len, max_kernel_buf_size - 5); + return spi_read_chunked(flash, buf, start, len, max_xfer - 5); } static int linux_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { /* 5 bytes must be reserved for longest possible command + address. */ - return spi_write_chunked(flash, buf, start, len, max_kernel_buf_size - 5); + return spi_write_chunked(flash, buf, start, len, max_xfer - 5); } #endif // CONFIG_LINUX_SPI == 1 -- To view, visit https://review.coreboot.org/c/flashrom/+/42405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iea868c2e48e61e981472ebcc5e15aaaaf161cab4 Gerrit-Change-Number: 42405 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Make ich_init_spi() parameteric on spibar
by Edward O'Callaghan (Code Review) July 16, 2020

July 16, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43506 ) Change subject: ichspi.c: Make ich_init_spi() parameteric on spibar ...................................................................... ichspi.c: Make ich_init_spi() parameteric on spibar The ich_init_spi() fn takes spibar as a parameter and sets the global ich_spibar with it but then uses the global symbol instead of using the parameter directly. Change-Id: Id809c33d8a4074acbee8e1cd8e3b7b00ce0cb3ec Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/06/43506/1 diff --git a/ichspi.c b/ichspi.c index b90b864..4dbe69a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1785,29 +1785,29 @@ case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: msg_pdbg("0x00: 0x%04x (SPIS)\n", - mmio_readw(ich_spibar + 0)); + mmio_readw(spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", - mmio_readw(ich_spibar + 2)); + mmio_readw(spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", - mmio_readl(ich_spibar + 4)); - ichspi_bbar = mmio_readl(ich_spibar + 0x50); + mmio_readl(spibar + 4)); + ichspi_bbar = mmio_readl(spibar + 0x50); msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); msg_pdbg("0x54: 0x%04x (PREOP)\n", - mmio_readw(ich_spibar + 0x54)); + mmio_readw(spibar + 0x54)); msg_pdbg("0x56: 0x%04x (OPTYPE)\n", - mmio_readw(ich_spibar + 0x56)); + mmio_readw(spibar + 0x56)); msg_pdbg("0x58: 0x%08x (OPMENU)\n", - mmio_readl(ich_spibar + 0x58)); + mmio_readl(spibar + 0x58)); msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", - mmio_readl(ich_spibar + 0x5c)); + mmio_readl(spibar + 0x5c)); for (i = 0; i < 3; i++) { int offs; offs = 0x60 + (i * 4); msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs, - mmio_readl(ich_spibar + offs), i); + mmio_readl(spibar + offs), i); } - if (mmio_readw(ich_spibar) & (1 << 15)) { + if (mmio_readw(spibar) & (1 << 15)) { msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } @@ -1839,7 +1839,7 @@ } free(arg); - tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); + tmp2 = mmio_readw(spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); prettyprint_ich9_reg_hsfs(tmp2, ich_gen); if (tmp2 & HSFS_FLOCKDN) { @@ -1855,12 +1855,12 @@ ich_init_opcodes(ich_gen); if (desc_valid) { - tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); + tmp2 = mmio_readw(spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); prettyprint_ich9_reg_hsfc(tmp2, ich_gen); } - tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); + tmp = mmio_readl(spibar + ICH9_REG_FADDR); msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp); switch (ich_gen) { @@ -1868,7 +1868,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: case CHIPSET_APOLLO_LAKE: - tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK); + tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); prettyprint_pch100_reg_dlock(tmp); break; @@ -1877,7 +1877,7 @@ } if (desc_valid) { - tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); + tmp = mmio_readl(spibar + ICH9_REG_FRAP); msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); @@ -1916,24 +1916,24 @@ break; } - tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc); + tmp = mmio_readl(spibar + swseq_data.reg_ssfsc); msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff); prettyprint_ich9_reg_ssfs(tmp); if (tmp & SSFS_FCERR) { msg_pdbg("Clearing SSFS.FCERR\n"); - mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc); + mmio_writeb(SSFS_FCERR, spibar + swseq_data.reg_ssfsc); } msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8); prettyprint_ich9_reg_ssfc(tmp); msg_pdbg("0x%zx: 0x%04x (PREOP)\n", - swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop)); + swseq_data.reg_preop, mmio_readw(spibar + swseq_data.reg_preop)); msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n", - swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype)); + swseq_data.reg_optype, mmio_readw(spibar + swseq_data.reg_optype)); msg_pdbg("0x%zx: 0x%08x (OPMENU)\n", - swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu)); + swseq_data.reg_opmenu, mmio_readl(spibar + swseq_data.reg_opmenu)); msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n", - swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4)); + swseq_data.reg_opmenu + 4, mmio_readl(spibar + swseq_data.reg_opmenu + 4)); if (desc_valid) { switch (ich_gen) { @@ -1945,24 +1945,24 @@ case CHIPSET_BAYTRAIL: break; default: - ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); + ichspi_bbar = mmio_readl(spibar + ICH9_REG_BBAR); msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); ich_set_bbar(0, ich_gen); break; } if (ich_gen == CHIPSET_ICH8) { - tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); + tmp = mmio_readl(spibar + ICH8_REG_VSCC); msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp); msg_pdbg("VSCC: "); prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); } else { - tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); + tmp = mmio_readl(spibar + ICH9_REG_LVSCC); msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp); msg_pdbg("LVSCC: "); prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); - tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); + tmp = mmio_readl(spibar + ICH9_REG_UVSCC); msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp); msg_pdbg("UVSCC: "); prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false); @@ -1976,12 +1976,12 @@ case CHIPSET_APOLLO_LAKE: break; default: - tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); + tmp = mmio_readl(spibar + ICH9_REG_FPB); msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp); break; } - if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK) + if (read_ich_descriptors_via_fdo(ich_gen, spibar, &desc) == ICH_RET_OK) prettyprint_ich_descriptors(ich_gen, &desc); /* If the descriptor is valid and indicates multiple -- To view, visit https://review.coreboot.org/c/flashrom/+/43506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id809c33d8a4074acbee8e1cd8e3b7b00ce0cb3ec Gerrit-Change-Number: 43506 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Make pprinters parameterics on ich_generation
by Edward O'Callaghan (Code Review) July 16, 2020

July 16, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43501 ) Change subject: ichspi.c: Make pprinters parameterics on ich_generation ...................................................................... ichspi.c: Make pprinters parameterics on ich_generation Make the two prettyprint functions pure by depending on the ich_generation as a function parameter over a global variable: * prettyprint_ich9_reg_hsfs() * prettyprint_ich9_reg_hsfc() Change-Id: I5d4fb012c6b9b843ac30c1fe2ea6fe754c545a43 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 17 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/43501/1 diff --git a/ichspi.c b/ichspi.c index 306b778..b90b864 100644 --- a/ichspi.c +++ b/ichspi.c @@ -389,13 +389,13 @@ #define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off) #define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep) -static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen) { msg_pdbg("HSFS: "); pprint_reg(HSFS, FDONE, reg_val, ", "); pprint_reg(HSFS, FCERR, reg_val, ", "); pprint_reg(HSFS, AEL, reg_val, ", "); - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -405,7 +405,7 @@ break; } pprint_reg(HSFS, SCIP, reg_val, ", "); - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -420,11 +420,11 @@ pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); } -static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val, enum ich_chipset ich_gen) { msg_pdbg("HSFC: "); pprint_reg(HSFC, FGO, reg_val, ", "); - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -1283,7 +1283,8 @@ Returns 0 if the cycle completes successfully without errors within timeout us, 1 on errors. */ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, - unsigned int len) + unsigned int len, + enum ich_chipset ich_gen) { uint16_t hsfs; uint32_t addr; @@ -1300,8 +1301,8 @@ msg_perr("Timeout error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); - prettyprint_ich9_reg_hsfs(hsfs); - prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + prettyprint_ich9_reg_hsfs(hsfs, ich_gen); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen); return 1; } @@ -1310,8 +1311,8 @@ msg_perr("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); - prettyprint_ich9_reg_hsfs(hsfs); - prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + prettyprint_ich9_reg_hsfs(hsfs, ich_gen); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen); return 1; } return 0; @@ -1415,10 +1416,10 @@ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); - prettyprint_ich9_reg_hsfc(hsfc); + prettyprint_ich9_reg_hsfc(hsfc, ich_generation); REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_generation)) return -1; return 0; } @@ -1455,7 +1456,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) return 1; ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; @@ -1497,7 +1498,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) return -1; addr += block_len; buf += block_len; @@ -1840,7 +1841,7 @@ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - prettyprint_ich9_reg_hsfs(tmp2); + prettyprint_ich9_reg_hsfs(tmp2, ich_gen); if (tmp2 & HSFS_FLOCKDN) { msg_pinfo("SPI Configuration is locked down.\n"); ichspi_lock = 1; @@ -1856,7 +1857,7 @@ if (desc_valid) { tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); - prettyprint_ich9_reg_hsfc(tmp2); + prettyprint_ich9_reg_hsfc(tmp2, ich_gen); } tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); -- To view, visit https://review.coreboot.org/c/flashrom/+/43501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5d4fb012c6b9b843ac30c1fe2ea6fe754c545a43 Gerrit-Change-Number: 43501 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Make ich_set_bbar() parameteric on ich_generation
by Edward O'Callaghan (Code Review) July 16, 2020

July 16, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43500 ) Change subject: ichspi.c: Make ich_set_bbar() parameteric on ich_generation ...................................................................... ichspi.c: Make ich_set_bbar() parameteric on ich_generation Work towards dropping ich_generation global usage and make the ich_set_bbar() function pure. Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/00/43500/1 diff --git a/ichspi.c b/ichspi.c index 82bbf9f..306b778 100644 --- a/ichspi.c +++ b/ichspi.c @@ -714,10 +714,10 @@ * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(uint32_t min_addr) +static void ich_set_bbar(uint32_t min_addr, enum ich_chipset ich_gen) { int bbar_off; - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -1811,7 +1811,7 @@ ichspi_lock = 1; } ich_init_opcodes(ich_gen); - ich_set_bbar(0); + ich_set_bbar(0, ich_gen); register_spi_master(&spi_master_ich7); break; case CHIPSET_ICH8: @@ -1946,7 +1946,7 @@ default: ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); - ich_set_bbar(0); + ich_set_bbar(0, ich_gen); break; } @@ -2099,7 +2099,7 @@ ichspi_lock = 1; } - ich_set_bbar(0); + ich_set_bbar(0, ich_generation); ich_init_opcodes(ich_generation); return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/43500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Gerrit-Change-Number: 43500 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Make ich_init_opcodes() parameteric on ich_generation
by Edward O'Callaghan (Code Review) July 16, 2020

July 16, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43499 ) Change subject: ichspi.c: Make ich_init_opcodes() parameteric on ich_generation ...................................................................... ichspi.c: Make ich_init_opcodes() parameteric on ich_generation Work towards dropping ich_generation global usage and make the ich_init_opcodes() function pure. Change-Id: I68cc078cc8bc1c772f52ca3e5e12559991180210 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/43499/1 diff --git a/ichspi.c b/ichspi.c index c044eb9..82bbf9f 100644 --- a/ichspi.c +++ b/ichspi.c @@ -288,8 +288,8 @@ /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); static int find_preop(OPCODES *op, uint8_t preop); -static int generate_opcodes(OPCODES * op); -static int program_opcodes(OPCODES *op, int enable_undo); +static int generate_opcodes(OPCODES * op, enum ich_chipset ich_gen); +static int program_opcodes(OPCODES *op, int enable_undo, enum ich_chipset ich_gen); static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); @@ -524,7 +524,7 @@ int oppos = 2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes, 0); + program_opcodes(curopcodes, 0, ich_generation); oppos = find_opcode(curopcodes, opcode); msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); return oppos; @@ -565,7 +565,7 @@ } /* Create a struct OPCODES based on what we find in the locked down chipset. */ -static int generate_opcodes(OPCODES * op) +static int generate_opcodes(OPCODES * op, enum ich_chipset ich_gen) { int a; uint16_t preop, optype; @@ -576,7 +576,7 @@ return -1; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -619,7 +619,7 @@ return 0; } -static int program_opcodes(OPCODES *op, int enable_undo) +static int program_opcodes(OPCODES *op, int enable_undo, enum ich_chipset ich_gen) { uint8_t a; uint16_t preop, optype; @@ -650,7 +650,7 @@ } msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -801,7 +801,7 @@ * * It should be called before ICH sends any spi command. */ -static int ich_init_opcodes(void) +static int ich_init_opcodes(enum ich_chipset ich_gen) { int rc = 0; OPCODES *curopcodes_done; @@ -812,11 +812,11 @@ if (ichspi_lock) { msg_pdbg("Reading OPCODES... "); curopcodes_done = &O_EXISTING; - rc = generate_opcodes(curopcodes_done); + rc = generate_opcodes(curopcodes_done, ich_gen); } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; - rc = program_opcodes(curopcodes_done, 1); + rc = program_opcodes(curopcodes_done, 1, ich_gen); } if (rc) { @@ -1810,7 +1810,7 @@ msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } - ich_init_opcodes(); + ich_init_opcodes(ich_gen); ich_set_bbar(0); register_spi_master(&spi_master_ich7); break; @@ -1851,7 +1851,7 @@ msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n" "the Master Section of the flash descriptor are NOT in effect. Please note\n" "that Protected Range (PR) restrictions still apply.\n"); - ich_init_opcodes(); + ich_init_opcodes(ich_gen); if (desc_valid) { tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); @@ -2100,7 +2100,7 @@ } ich_set_bbar(0); - ich_init_opcodes(); + ich_init_opcodes(ich_generation); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/43499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I68cc078cc8bc1c772f52ca3e5e12559991180210 Gerrit-Change-Number: 43499 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Make ich_init_spi() parametric on ich_generation
by Edward O'Callaghan (Code Review) July 16, 2020

July 16, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43498 ) Change subject: ichspi.c: Make ich_init_spi() parametric on ich_generation ...................................................................... ichspi.c: Make ich_init_spi() parametric on ich_generation Work towards dropping ich_generation global usage and make the ich_init_spi() function more pure. Change-Id: I5293e7ae6f20a2299577172655c2926861091f5a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/43498/1 diff --git a/ichspi.c b/ichspi.c index c780d52..c044eb9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1736,7 +1736,7 @@ memset(&desc, 0x00, sizeof(struct ich_descriptors)); /* Moving registers / bits */ - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -1763,7 +1763,7 @@ hwseq_data.hsfc_fcycle = HSFC_FCYCLE; break; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: num_freg = 10; break; @@ -1779,7 +1779,7 @@ break; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -2021,14 +2021,14 @@ return ERROR_FATAL; } - int tmpi = getFCBA_component_density(ich_generation, &desc, 0); + int tmpi = getFCBA_component_density(ich_gen, &desc, 0); if (tmpi < 0) { msg_perr("Could not determine density of flash component %d.\n", 0); return ERROR_FATAL; } hwseq_data.size_comp0 = tmpi; - tmpi = getFCBA_component_density(ich_generation, &desc, 1); + tmpi = getFCBA_component_density(ich_gen, &desc, 1); if (tmpi < 0) { msg_perr("Could not determine density of flash component %d.\n", 1); return ERROR_FATAL; -- To view, visit https://review.coreboot.org/c/flashrom/+/43498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5293e7ae6f20a2299577172655c2926861091f5a Gerrit-Change-Number: 43498 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: WIP Put ich_spibar inside spi_master data feild
by Edward O'Callaghan (Code Review) July 16, 2020

July 16, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43507 ) Change subject: ichspi.c: WIP Put ich_spibar inside spi_master data feild ...................................................................... ichspi.c: WIP Put ich_spibar inside spi_master data feild Change-Id: I74469a48420eff9ef4f07040dcb2d297143859df Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/43507/1 diff --git a/ichspi.c b/ichspi.c index 661236e..4ea80c8 100644 --- a/ichspi.c +++ b/ichspi.c @@ -240,6 +240,7 @@ struct ich_spi_data { enum ich_chipset ich_gen; + void *ich_spibar; }; typedef struct _OPCODE { @@ -1753,7 +1754,6 @@ } ich_spi_mode = ich_auto; size_t num_freg, num_pr, reg_pr0; - ich_spibar = spibar; struct ich_spi_data *ich_data = calloc(1, sizeof(struct ich_spi_data)); if (!ich_data) { msg_perr("Unable to allocate space for extra SPI master data.\n"); @@ -1761,6 +1761,7 @@ } ich_data->ich_gen = ich_gen; + ich_data->ich_spibar = spibar; spi_master_ich7.data = ich_data; spi_master_ich9.data = ich_data; @@ -2098,13 +2099,6 @@ /* Not sure if it speaks all these bus protocols. */ internal_buses_supported &= BUS_LPC | BUS_FWH; - struct ich_spi_data ich_data = { - .ich_gen = CHIPSET_ICH7, - }; - spi_master_via.data = &ich_data; - - register_spi_master(&spi_master_via); - msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4)); @@ -2135,9 +2129,17 @@ ichspi_lock = 1; } + struct ich_spi_data ich_data = { + .ich_gen = CHIPSET_ICH7, + .ich_spibar = ich_spibar, + }; + spi_master_via.data = &ich_data; + ich_set_bbar(0, ich_data.ich_gen); ich_init_opcodes(ich_data.ich_gen); + register_spi_master(&spi_master_via); + return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/43507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I74469a48420eff9ef4f07040dcb2d297143859df Gerrit-Change-Number: 43507 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi: WIP Move global state into spi_master 'data' field
by Edward O'Callaghan (Code Review) July 16, 2020

July 16, 2020

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43504 ) Change subject: ichspi: WIP Move global state into spi_master 'data' field ...................................................................... ichspi: WIP Move global state into spi_master 'data' field NOT-FOR-MERGE-YET. Change-Id: I368846039445f5e52a7c84a91676ee13b4aab9be Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 42 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/43504/1 diff --git a/ichspi.c b/ichspi.c index b90b864..19ce8cf 100644 --- a/ichspi.c +++ b/ichspi.c @@ -239,6 +239,10 @@ static void *ich_spibar = NULL; +struct ich_spi_data { + enum ich_chipset ich_gen; +}; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -494,7 +498,7 @@ return 0xFF; } -static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) +static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt, enum ich_chipset ich_gen) { uint8_t spi_type; @@ -524,7 +528,7 @@ int oppos = 2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes, 0, ich_generation); + program_opcodes(curopcodes, 0, ich_gen); oppos = find_opcode(curopcodes, opcode); msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); return oppos; @@ -1079,8 +1083,11 @@ { /* max_data_read == max_data_write for all Intel/VIA SPI masters */ uint8_t maxlength = flash->mst->spi.max_data_read; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; - if (ich_generation == CHIPSET_ICH_UNKNOWN) { + if (ich_gen == CHIPSET_ICH_UNKNOWN) { msg_perr("%s: unsupported chipset\n", __func__); return -1; } @@ -1092,7 +1099,7 @@ return SPI_INVALID_LENGTH; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -1115,12 +1122,15 @@ uint32_t addr = 0; uint8_t *data; int count; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; /* find cmd in opcodes-table */ opcode_index = find_opcode(curopcodes, cmd); if (opcode_index == -1) { if (!ichspi_lock) - opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); + opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt, ich_gen); if (opcode_index == SPI_INVALID_LENGTH) { msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd); return SPI_INVALID_LENGTH; @@ -1380,6 +1390,9 @@ uint32_t erase_block; uint16_t hsfc; uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; erase_block = ich_hwseq_get_erase_block_size(addr); if (len != erase_block) { @@ -1416,10 +1429,10 @@ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); - prettyprint_ich9_reg_hsfc(hsfc, ich_generation); + prettyprint_ich9_reg_hsfc(hsfc, ich_gen); REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_gen)) return -1; return 0; } @@ -1430,6 +1443,9 @@ uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; if (addr + len > flash->chip->total_size * 1024) { msg_perr("Request to read from an inaccessible memory address " @@ -1456,7 +1472,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_gen)) return 1; ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; @@ -1471,6 +1487,9 @@ uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; if (addr + len > flash->chip->total_size * 1024) { msg_perr("Request to write to an inaccessible memory address " @@ -1498,7 +1517,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_gen)) return -1; addr += block_len; buf += block_len; @@ -1539,7 +1558,7 @@ * No need to bother with fixups. */ if (!ichspi_lock) { - oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); + oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt, ich_gen); if (oppos == -1) continue; curopcodes->opcode[oppos].atomic = preoppos + 1; @@ -1686,7 +1705,7 @@ msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); } -static const struct spi_master spi_master_ich7 = { +static struct spi_master spi_master_ich7 = { .max_data_read = 64, .max_data_write = 64, .command = ich_spi_send_command, @@ -1696,7 +1715,7 @@ .write_aai = default_spi_write_aai, }; -static const struct spi_master spi_master_ich9 = { +static struct spi_master spi_master_ich9 = { .max_data_read = 64, .max_data_write = 64, .command = ich_spi_send_command, @@ -1733,6 +1752,16 @@ ich_generation = ich_gen; ich_spibar = spibar; + struct ich_spi_data *ich_data = calloc(1, sizeof(struct ich_spi_data)); + if (!ich_data) { + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + + ich_data->ich_gen = ich_gen; + spi_master_ich7.data = ich_data; + spi_master_ich9.data = ich_data; + spi_master_via.data = ich_data; memset(&desc, 0x00, sizeof(struct ich_descriptors)); @@ -2046,7 +2075,7 @@ return 0; } -static const struct spi_master spi_master_via = { +static struct spi_master spi_master_via = { .max_data_read = 16, .max_data_write = 16, .command = ich_spi_send_command, -- To view, visit https://review.coreboot.org/c/flashrom/+/43504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I368846039445f5e52a7c84a91676ee13b4aab9be Gerrit-Change-Number: 43504 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: Install the man file when using meson as a buildsystem
by Richard Hughes (Code Review) July 15, 2020

July 15, 2020

Richard Hughes has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38939 ) Change subject: Install the man file when using meson as a buildsystem ...................................................................... Install the man file when using meson as a buildsystem This fixes a regression with the Fedora package. Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c Signed-off-by: Richard Hughes <richard(a)hughsie.com> --- M meson.build 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/38939/1 diff --git a/meson.build b/meson.build index 375089c..df39290 100644 --- a/meson.build +++ b/meson.build @@ -299,6 +299,7 @@ prefix = get_option('prefix') sbindir = join_paths(prefix, get_option('sbindir')) libdir = join_paths(prefix, get_option('libdir')) +mandir = join_paths(prefix, get_option('mandir')) install_headers([ 'libflashrom.h', @@ -372,6 +373,14 @@ description : 'library to interact with flashrom', ) +configure_file( + input : 'flashrom.8.tmpl', + output : 'flashrom.8', + copy: true, + install: true, + install_dir: join_paths(mandir, 'man8'), +) + flashrom_dep = declare_dependency( link_with : flashrom, include_directories : include_directories('.'), -- To view, visit https://review.coreboot.org/c/flashrom/+/38939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c Gerrit-Change-Number: 38939 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Hughes <richard(a)hughsie.com> Gerrit-MessageType: newchange

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Change in flashrom[master]: Add Gemini Lake support
by Angel Pons (Code Review) July 11, 2020

July 11, 2020

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/43349 to look at the new patch set (#4). Change subject: Add Gemini Lake support ...................................................................... Add Gemini Lake support FIXME: Split detailed softstrap printing into its own commit Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Change-Id: I926a44176558115a2c833ef0954956eeb75061ff --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 638 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/43349/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/43349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I926a44176558115a2c833ef0954956eeb75061ff Gerrit-Change-Number: 43349 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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