July 2020 - flashrom-gerrit - mail.coreboot.org

Change in flashrom[master]: ichspi.c: Make pprinters parameterics on ich_generation
by Edward O'Callaghan (Code Review) 16 Jul '20

16 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43501 ) Change subject: ichspi.c: Make pprinters parameterics on ich_generation ...................................................................... ichspi.c: Make pprinters parameterics on ich_generation Make the two prettyprint functions pure by depending on the ich_generation as a function parameter over a global variable: * prettyprint_ich9_reg_hsfs() * prettyprint_ich9_reg_hsfc() Change-Id: I5d4fb012c6b9b843ac30c1fe2ea6fe754c545a43 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 17 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/01/43501/1 diff --git a/ichspi.c b/ichspi.c index 306b778..b90b864 100644 --- a/ichspi.c +++ b/ichspi.c @@ -389,13 +389,13 @@ #define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off) #define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep) -static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) +static void prettyprint_ich9_reg_hsfs(uint16_t reg_val, enum ich_chipset ich_gen) { msg_pdbg("HSFS: "); pprint_reg(HSFS, FDONE, reg_val, ", "); pprint_reg(HSFS, FCERR, reg_val, ", "); pprint_reg(HSFS, AEL, reg_val, ", "); - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -405,7 +405,7 @@ break; } pprint_reg(HSFS, SCIP, reg_val, ", "); - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -420,11 +420,11 @@ pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); } -static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) +static void prettyprint_ich9_reg_hsfc(uint16_t reg_val, enum ich_chipset ich_gen) { msg_pdbg("HSFC: "); pprint_reg(HSFC, FGO, reg_val, ", "); - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -1283,7 +1283,8 @@ Returns 0 if the cycle completes successfully without errors within timeout us, 1 on errors. */ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, - unsigned int len) + unsigned int len, + enum ich_chipset ich_gen) { uint16_t hsfs; uint32_t addr; @@ -1300,8 +1301,8 @@ msg_perr("Timeout error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); - prettyprint_ich9_reg_hsfs(hsfs); - prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + prettyprint_ich9_reg_hsfs(hsfs, ich_gen); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen); return 1; } @@ -1310,8 +1311,8 @@ msg_perr("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); - prettyprint_ich9_reg_hsfs(hsfs); - prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); + prettyprint_ich9_reg_hsfs(hsfs, ich_gen); + prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC), ich_gen); return 1; } return 0; @@ -1415,10 +1416,10 @@ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); - prettyprint_ich9_reg_hsfc(hsfc); + prettyprint_ich9_reg_hsfc(hsfc, ich_generation); REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len)) + if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_generation)) return -1; return 0; } @@ -1455,7 +1456,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) return 1; ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; @@ -1497,7 +1498,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) return -1; addr += block_len; buf += block_len; @@ -1840,7 +1841,7 @@ tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); - prettyprint_ich9_reg_hsfs(tmp2); + prettyprint_ich9_reg_hsfs(tmp2, ich_gen); if (tmp2 & HSFS_FLOCKDN) { msg_pinfo("SPI Configuration is locked down.\n"); ichspi_lock = 1; @@ -1856,7 +1857,7 @@ if (desc_valid) { tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); - prettyprint_ich9_reg_hsfc(tmp2); + prettyprint_ich9_reg_hsfc(tmp2, ich_gen); } tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); -- To view, visit https://review.coreboot.org/c/flashrom/+/43501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5d4fb012c6b9b843ac30c1fe2ea6fe754c545a43 Gerrit-Change-Number: 43501 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Make ich_set_bbar() parameteric on ich_generation
by Edward O'Callaghan (Code Review) 16 Jul '20

16 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43500 ) Change subject: ichspi.c: Make ich_set_bbar() parameteric on ich_generation ...................................................................... ichspi.c: Make ich_set_bbar() parameteric on ich_generation Work towards dropping ich_generation global usage and make the ich_set_bbar() function pure. Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/00/43500/1 diff --git a/ichspi.c b/ichspi.c index 82bbf9f..306b778 100644 --- a/ichspi.c +++ b/ichspi.c @@ -714,10 +714,10 @@ * Try to set BBAR (BIOS Base Address Register), but read back the value in case * it didn't stick. */ -static void ich_set_bbar(uint32_t min_addr) +static void ich_set_bbar(uint32_t min_addr, enum ich_chipset ich_gen) { int bbar_off; - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -1811,7 +1811,7 @@ ichspi_lock = 1; } ich_init_opcodes(ich_gen); - ich_set_bbar(0); + ich_set_bbar(0, ich_gen); register_spi_master(&spi_master_ich7); break; case CHIPSET_ICH8: @@ -1946,7 +1946,7 @@ default: ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); - ich_set_bbar(0); + ich_set_bbar(0, ich_gen); break; } @@ -2099,7 +2099,7 @@ ichspi_lock = 1; } - ich_set_bbar(0); + ich_set_bbar(0, ich_generation); ich_init_opcodes(ich_generation); return 0; -- To view, visit https://review.coreboot.org/c/flashrom/+/43500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Gerrit-Change-Number: 43500 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Make ich_init_opcodes() parameteric on ich_generation
by Edward O'Callaghan (Code Review) 16 Jul '20

16 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43499 ) Change subject: ichspi.c: Make ich_init_opcodes() parameteric on ich_generation ...................................................................... ichspi.c: Make ich_init_opcodes() parameteric on ich_generation Work towards dropping ich_generation global usage and make the ich_init_opcodes() function pure. Change-Id: I68cc078cc8bc1c772f52ca3e5e12559991180210 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/43499/1 diff --git a/ichspi.c b/ichspi.c index c044eb9..82bbf9f 100644 --- a/ichspi.c +++ b/ichspi.c @@ -288,8 +288,8 @@ /* Common SPI functions */ static int find_opcode(OPCODES *op, uint8_t opcode); static int find_preop(OPCODES *op, uint8_t preop); -static int generate_opcodes(OPCODES * op); -static int program_opcodes(OPCODES *op, int enable_undo); +static int generate_opcodes(OPCODES * op, enum ich_chipset ich_gen); +static int program_opcodes(OPCODES *op, int enable_undo, enum ich_chipset ich_gen); static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); @@ -524,7 +524,7 @@ int oppos = 2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes, 0); + program_opcodes(curopcodes, 0, ich_generation); oppos = find_opcode(curopcodes, opcode); msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); return oppos; @@ -565,7 +565,7 @@ } /* Create a struct OPCODES based on what we find in the locked down chipset. */ -static int generate_opcodes(OPCODES * op) +static int generate_opcodes(OPCODES * op, enum ich_chipset ich_gen) { int a; uint16_t preop, optype; @@ -576,7 +576,7 @@ return -1; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -619,7 +619,7 @@ return 0; } -static int program_opcodes(OPCODES *op, int enable_undo) +static int program_opcodes(OPCODES *op, int enable_undo, enum ich_chipset ich_gen) { uint8_t a; uint16_t preop, optype; @@ -650,7 +650,7 @@ } msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -801,7 +801,7 @@ * * It should be called before ICH sends any spi command. */ -static int ich_init_opcodes(void) +static int ich_init_opcodes(enum ich_chipset ich_gen) { int rc = 0; OPCODES *curopcodes_done; @@ -812,11 +812,11 @@ if (ichspi_lock) { msg_pdbg("Reading OPCODES... "); curopcodes_done = &O_EXISTING; - rc = generate_opcodes(curopcodes_done); + rc = generate_opcodes(curopcodes_done, ich_gen); } else { msg_pdbg("Programming OPCODES... "); curopcodes_done = &O_ST_M25P; - rc = program_opcodes(curopcodes_done, 1); + rc = program_opcodes(curopcodes_done, 1, ich_gen); } if (rc) { @@ -1810,7 +1810,7 @@ msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; } - ich_init_opcodes(); + ich_init_opcodes(ich_gen); ich_set_bbar(0); register_spi_master(&spi_master_ich7); break; @@ -1851,7 +1851,7 @@ msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n" "the Master Section of the flash descriptor are NOT in effect. Please note\n" "that Protected Range (PR) restrictions still apply.\n"); - ich_init_opcodes(); + ich_init_opcodes(ich_gen); if (desc_valid) { tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); @@ -2100,7 +2100,7 @@ } ich_set_bbar(0); - ich_init_opcodes(); + ich_init_opcodes(ich_generation); return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/43499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I68cc078cc8bc1c772f52ca3e5e12559991180210 Gerrit-Change-Number: 43499 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: Make ich_init_spi() parametric on ich_generation
by Edward O'Callaghan (Code Review) 16 Jul '20

16 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43498 ) Change subject: ichspi.c: Make ich_init_spi() parametric on ich_generation ...................................................................... ichspi.c: Make ich_init_spi() parametric on ich_generation Work towards dropping ich_generation global usage and make the ich_init_spi() function more pure. Change-Id: I5293e7ae6f20a2299577172655c2926861091f5a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/98/43498/1 diff --git a/ichspi.c b/ichspi.c index c780d52..c044eb9 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1736,7 +1736,7 @@ memset(&desc, 0x00, sizeof(struct ich_descriptors)); /* Moving registers / bits */ - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -1763,7 +1763,7 @@ hwseq_data.hsfc_fcycle = HSFC_FCYCLE; break; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_100_SERIES_SUNRISE_POINT: num_freg = 10; break; @@ -1779,7 +1779,7 @@ break; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -2021,14 +2021,14 @@ return ERROR_FATAL; } - int tmpi = getFCBA_component_density(ich_generation, &desc, 0); + int tmpi = getFCBA_component_density(ich_gen, &desc, 0); if (tmpi < 0) { msg_perr("Could not determine density of flash component %d.\n", 0); return ERROR_FATAL; } hwseq_data.size_comp0 = tmpi; - tmpi = getFCBA_component_density(ich_generation, &desc, 1); + tmpi = getFCBA_component_density(ich_gen, &desc, 1); if (tmpi < 0) { msg_perr("Could not determine density of flash component %d.\n", 1); return ERROR_FATAL; -- To view, visit https://review.coreboot.org/c/flashrom/+/43498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I5293e7ae6f20a2299577172655c2926861091f5a Gerrit-Change-Number: 43498 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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Change in flashrom[master]: ichspi.c: WIP Put ich_spibar inside spi_master data feild
by Edward O'Callaghan (Code Review) 16 Jul '20

16 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43507 ) Change subject: ichspi.c: WIP Put ich_spibar inside spi_master data feild ...................................................................... ichspi.c: WIP Put ich_spibar inside spi_master data feild Change-Id: I74469a48420eff9ef4f07040dcb2d297143859df Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/43507/1 diff --git a/ichspi.c b/ichspi.c index 661236e..4ea80c8 100644 --- a/ichspi.c +++ b/ichspi.c @@ -240,6 +240,7 @@ struct ich_spi_data { enum ich_chipset ich_gen; + void *ich_spibar; }; typedef struct _OPCODE { @@ -1753,7 +1754,6 @@ } ich_spi_mode = ich_auto; size_t num_freg, num_pr, reg_pr0; - ich_spibar = spibar; struct ich_spi_data *ich_data = calloc(1, sizeof(struct ich_spi_data)); if (!ich_data) { msg_perr("Unable to allocate space for extra SPI master data.\n"); @@ -1761,6 +1761,7 @@ } ich_data->ich_gen = ich_gen; + ich_data->ich_spibar = spibar; spi_master_ich7.data = ich_data; spi_master_ich9.data = ich_data; @@ -2098,13 +2099,6 @@ /* Not sure if it speaks all these bus protocols. */ internal_buses_supported &= BUS_LPC | BUS_FWH; - struct ich_spi_data ich_data = { - .ich_gen = CHIPSET_ICH7, - }; - spi_master_via.data = &ich_data; - - register_spi_master(&spi_master_via); - msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4)); @@ -2135,9 +2129,17 @@ ichspi_lock = 1; } + struct ich_spi_data ich_data = { + .ich_gen = CHIPSET_ICH7, + .ich_spibar = ich_spibar, + }; + spi_master_via.data = &ich_data; + ich_set_bbar(0, ich_data.ich_gen); ich_init_opcodes(ich_data.ich_gen); + register_spi_master(&spi_master_via); + return 0; } -- To view, visit https://review.coreboot.org/c/flashrom/+/43507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I74469a48420eff9ef4f07040dcb2d297143859df Gerrit-Change-Number: 43507 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 1

Change in flashrom[master]: ichspi: WIP Move global state into spi_master 'data' field
by Edward O'Callaghan (Code Review) 16 Jul '20

16 Jul '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/43504 ) Change subject: ichspi: WIP Move global state into spi_master 'data' field ...................................................................... ichspi: WIP Move global state into spi_master 'data' field NOT-FOR-MERGE-YET. Change-Id: I368846039445f5e52a7c84a91676ee13b4aab9be Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M ichspi.c 1 file changed, 42 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/43504/1 diff --git a/ichspi.c b/ichspi.c index b90b864..19ce8cf 100644 --- a/ichspi.c +++ b/ichspi.c @@ -239,6 +239,10 @@ static void *ich_spibar = NULL; +struct ich_spi_data { + enum ich_chipset ich_gen; +}; + typedef struct _OPCODE { uint8_t opcode; //This commands spi opcode uint8_t spi_type; //This commands spi type @@ -494,7 +498,7 @@ return 0xFF; } -static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) +static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt, enum ich_chipset ich_gen) { uint8_t spi_type; @@ -524,7 +528,7 @@ int oppos = 2; // use original JEDEC_BE_D8 offset curopcodes->opcode[oppos].opcode = opcode; curopcodes->opcode[oppos].spi_type = spi_type; - program_opcodes(curopcodes, 0, ich_generation); + program_opcodes(curopcodes, 0, ich_gen); oppos = find_opcode(curopcodes, opcode); msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); return oppos; @@ -1079,8 +1083,11 @@ { /* max_data_read == max_data_write for all Intel/VIA SPI masters */ uint8_t maxlength = flash->mst->spi.max_data_read; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; - if (ich_generation == CHIPSET_ICH_UNKNOWN) { + if (ich_gen == CHIPSET_ICH_UNKNOWN) { msg_perr("%s: unsupported chipset\n", __func__); return -1; } @@ -1092,7 +1099,7 @@ return SPI_INVALID_LENGTH; } - switch (ich_generation) { + switch (ich_gen) { case CHIPSET_ICH7: case CHIPSET_TUNNEL_CREEK: case CHIPSET_CENTERTON: @@ -1115,12 +1122,15 @@ uint32_t addr = 0; uint8_t *data; int count; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; /* find cmd in opcodes-table */ opcode_index = find_opcode(curopcodes, cmd); if (opcode_index == -1) { if (!ichspi_lock) - opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); + opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt, ich_gen); if (opcode_index == SPI_INVALID_LENGTH) { msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd); return SPI_INVALID_LENGTH; @@ -1380,6 +1390,9 @@ uint32_t erase_block; uint16_t hsfc; uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; erase_block = ich_hwseq_get_erase_block_size(addr); if (len != erase_block) { @@ -1416,10 +1429,10 @@ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); - prettyprint_ich9_reg_hsfc(hsfc, ich_generation); + prettyprint_ich9_reg_hsfc(hsfc, ich_gen); REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_gen)) return -1; return 0; } @@ -1430,6 +1443,9 @@ uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; if (addr + len > flash->chip->total_size * 1024) { msg_perr("Request to read from an inaccessible memory address " @@ -1456,7 +1472,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_gen)) return 1; ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; @@ -1471,6 +1487,9 @@ uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; + const struct ich_spi_data *ich_data = + (const struct ich_spi_data *)flash->mst->spi.data; + enum ich_chipset ich_gen = ich_data->ich_gen; if (addr + len > flash->chip->total_size * 1024) { msg_perr("Request to write to an inaccessible memory address " @@ -1498,7 +1517,7 @@ hsfc |= HSFC_FGO; /* start */ REGWRITE16(ICH9_REG_HSFC, hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation)) + if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_gen)) return -1; addr += block_len; buf += block_len; @@ -1539,7 +1558,7 @@ * No need to bother with fixups. */ if (!ichspi_lock) { - oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); + oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt, ich_gen); if (oppos == -1) continue; curopcodes->opcode[oppos].atomic = preoppos + 1; @@ -1686,7 +1705,7 @@ msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); } -static const struct spi_master spi_master_ich7 = { +static struct spi_master spi_master_ich7 = { .max_data_read = 64, .max_data_write = 64, .command = ich_spi_send_command, @@ -1696,7 +1715,7 @@ .write_aai = default_spi_write_aai, }; -static const struct spi_master spi_master_ich9 = { +static struct spi_master spi_master_ich9 = { .max_data_read = 64, .max_data_write = 64, .command = ich_spi_send_command, @@ -1733,6 +1752,16 @@ ich_generation = ich_gen; ich_spibar = spibar; + struct ich_spi_data *ich_data = calloc(1, sizeof(struct ich_spi_data)); + if (!ich_data) { + msg_perr("Unable to allocate space for extra SPI master data.\n"); + return SPI_GENERIC_ERROR; + } + + ich_data->ich_gen = ich_gen; + spi_master_ich7.data = ich_data; + spi_master_ich9.data = ich_data; + spi_master_via.data = ich_data; memset(&desc, 0x00, sizeof(struct ich_descriptors)); @@ -2046,7 +2075,7 @@ return 0; } -static const struct spi_master spi_master_via = { +static struct spi_master spi_master_via = { .max_data_read = 16, .max_data_write = 16, .command = ich_spi_send_command, -- To view, visit https://review.coreboot.org/c/flashrom/+/43504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I368846039445f5e52a7c84a91676ee13b4aab9be Gerrit-Change-Number: 43504 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in flashrom[master]: Install the man file when using meson as a buildsystem
by Richard Hughes (Code Review) 15 Jul '20

15 Jul '20

Richard Hughes has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38939 ) Change subject: Install the man file when using meson as a buildsystem ...................................................................... Install the man file when using meson as a buildsystem This fixes a regression with the Fedora package. Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c Signed-off-by: Richard Hughes <richard(a)hughsie.com> --- M meson.build 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/38939/1 diff --git a/meson.build b/meson.build index 375089c..df39290 100644 --- a/meson.build +++ b/meson.build @@ -299,6 +299,7 @@ prefix = get_option('prefix') sbindir = join_paths(prefix, get_option('sbindir')) libdir = join_paths(prefix, get_option('libdir')) +mandir = join_paths(prefix, get_option('mandir')) install_headers([ 'libflashrom.h', @@ -372,6 +373,14 @@ description : 'library to interact with flashrom', ) +configure_file( + input : 'flashrom.8.tmpl', + output : 'flashrom.8', + copy: true, + install: true, + install_dir: join_paths(mandir, 'man8'), +) + flashrom_dep = declare_dependency( link_with : flashrom, include_directories : include_directories('.'), -- To view, visit https://review.coreboot.org/c/flashrom/+/38939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c Gerrit-Change-Number: 38939 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Hughes <richard(a)hughsie.com> Gerrit-MessageType: newchange

7 14

Change in flashrom[master]: pcidev: On arm64 we are not getting a valid BAR0 address
by Martijn Berger (Code Review) 14 Jul '20

14 Jul '20

Martijn Berger has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/39965 ) Change subject: pcidev: On arm64 we are not getting a valid BAR0 address ...................................................................... pcidev: On arm64 we are not getting a valid BAR0 address It seems that there is some code to work around a possible bug in old versions of libpci. This trusts libpci if it is new enough Change-Id: I8bd32c6344b0831a949c3853abeb84905420922a Signed-off-by: Martijn Berger <martijn.berger(a)gmail.com> --- M pcidev.c M programmer.h 2 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/65/39965/1 diff --git a/pcidev.c b/pcidev.c index 54c1fd3..973acde 100644 --- a/pcidev.c +++ b/pcidev.c @@ -30,20 +30,47 @@ TYPE_UNKNOWN }; +int pci_bar_nuber_from_offset(int offset) +{ + switch (offset) { + case PCI_BASE_ADDRESS_0: + return 0; + case PCI_BASE_ADDRESS_1: + return 1; + case PCI_BASE_ADDRESS_2: + return 2; + case PCI_BASE_ADDRESS_3: + return 3; + case PCI_BASE_ADDRESS_4: + return 4; + case PCI_BASE_ADDRESS_5: + return 5; + default: + return -1; + } + return -1; +} + uintptr_t pcidev_readbar(struct pci_dev *dev, int bar) { uint64_t addr; uint32_t upperaddr; uint8_t headertype; uint16_t supported_cycles; + int bar_number; enum pci_bartype bartype = TYPE_UNKNOWN; headertype = pci_read_byte(dev, PCI_HEADER_TYPE) & 0x7f; msg_pspew("PCI header type 0x%02x\n", headertype); + bar_number = pci_bar_nuber_from_offset(bar); - /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ - addr = pci_read_long(dev, bar); + if (PCI_LIB_VERSION >= 0x030500 && bar_number > -1) { + addr = dev->base_addr[bar_number]; + } else { + /* Don't use dev->base_addr[x] (as value for 'bar'), won't work on older libpci. */ + addr = pci_read_long(dev, bar); + } /* Sanity checks. */ switch (headertype) { diff --git a/programmer.h b/programmer.h index 9a41be1..5d4c1d7 100644 --- a/programmer.h +++ b/programmer.h @@ -190,6 +190,7 @@ // FIXME: This needs to be local, not global(?) extern struct pci_access *pacc; int pci_init_common(void); +int pci_bar_nuber_from_offset(int offset); uintptr_t pcidev_readbar(struct pci_dev *dev, int bar); struct pci_dev *pcidev_init(const struct dev_entry *devs, int bar); /* rpci_write_* are reversible writes. The original PCI config space register -- To view, visit https://review.coreboot.org/c/flashrom/+/39965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I8bd32c6344b0831a949c3853abeb84905420922a Gerrit-Change-Number: 39965 Gerrit-PatchSet: 1 Gerrit-Owner: Martijn Berger Gerrit-MessageType: newchange

4 5

Change in flashrom[master]: Add Gemini Lake support
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/43349 to look at the new patch set (#4). Change subject: Add Gemini Lake support ...................................................................... Add Gemini Lake support FIXME: Split detailed softstrap printing into its own commit Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Change-Id: I926a44176558115a2c833ef0954956eeb75061ff --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 638 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/43349/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/43349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I926a44176558115a2c833ef0954956eeb75061ff Gerrit-Change-Number: 43349 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in flashrom[master]: Add Gemini Lake support
by Angel Pons (Code Review) 11 Jul '20

11 Jul '20

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/43349 to look at the new patch set (#3). Change subject: Add Gemini Lake support ...................................................................... Add Gemini Lake support FIXME: Split detailed softstrap printing into its own commit Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Change-Id: I926a44176558115a2c833ef0954956eeb75061ff --- M chipset_enable.c M ich_descriptors.c M ich_descriptors.h M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 6 files changed, 608 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/49/43349/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/43349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I926a44176558115a2c833ef0954956eeb75061ff Gerrit-Change-Number: 43349 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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