Change in coreboot[master]: soc/intel/alderlake:[TEST_ONLY] Disable SaGv

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59864 )

Change subject: soc/intel/alderlake:[TEST_ONLY] Disable SaGv
......................................................................

soc/intel/alderlake:[TEST_ONLY] Disable SaGv

Signed-off-by: Sridhar Siricilla 
Change-Id: I1335dd2ef304ba9ab97ce5c5889875ade691239c
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/59864/1

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 121251e..eaae07c 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -135,7 +135,7 @@
 static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
-	m_cfg->SaGv = config->SaGv;
+	m_cfg->SaGv = 0;
    m_cfg->RMT = config->RMT;
    if (config->MaxDramSpeed)
    	m_cfg->DdrFreqLimit = config->MaxDramSpeed;