Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage ......................................................................
Patch Set 74:
(5 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83635/comment/0a2cca84_bff85cb3?usp... : PS73, Line 45: SOC_INTEL_PANTHERLAKE_U_H
this is misleading, […]
Hi Subrata, We have 3 SKUs, U15 (PTL-U 15W Processor Base Power), H25 (PTL-H 12Xe25W Processor Base Power) & H25 (PTL-H 4Xe 25W Processor Base Power). Please ref doc #823589, section 2.0 table.
As suggested, i will be using two Kconfig SOC_INTEL_PANTHERLAKE_U_H & SOC_INTEL_PANTHERLAKE_H (which only supports PTL H 4Xe)
https://review.coreboot.org/c/coreboot/+/83635/comment/876e8832_9282becf?usp... : PS73, Line 260:
Can you please add the Pcie ltr max snoop/nosnoop latency values as well? […]
Ack, Adding in ramstage.
https://review.coreboot.org/c/coreboot/+/83635/comment/7d9df8f5_c90919aa?usp... : PS73, Line 269: SOC_INTEL_ACPI_GPIO_PINCTRL_COMPACT
I thought GPIO CL will introduce this Kconfig ?
Ack, Moved to GPIO CL.
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/16559b66_71f3ded1?usp... : PS72, Line 63: /* Bit values for use in LpmStateEnableMask. */ : enum lpm_state_mask { : LPM_S0i2_0 = BIT(0), : LPM_S0i2_1 = BIT(1), : LPM_S0i2_2 = BIT(2), : LPM_S0i3_0 = BIT(3), : LPM_S0i3_1 = BIT(4), : LPM_S0i3_2 = BIT(5), : LPM_S0i3_3 = BIT(6), : LPM_S0i3_4 = BIT(7), : LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 : | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, : }; :
Hi Subrata, we will be using these macros to get supported lpm mask. […]
Ack, moving to ramstage.
File src/soc/intel/pantherlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/83635/comment/7e46a5ff_d9362283?usp... : PS72, Line 5: PTL_U_H_POWER_LIMITS
Hi Subrata, i have added the corresponding 15W/25W/45W into enum. […]
Hi Subrata, we referred the data from FSP, due to PDG guide requires PNP completion, which is not achieved yet. Its too early. Anyway, i will keep a note in crosbug to update the data from PDG doc.