Change in coreboot[master]: soc/amd/psp_verstage: Init TPM on S0i3 resume

[Julius Werner (Code Review)]

Attention is currently required from: Raul Rangel, Andrey Pronin, Kangheui Won, Rob Barnes, Karthik Ramasubramanian.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58870 )

Change subject: soc/amd/psp_verstage: Init TPM on S0i3 resume
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Patch Set 7:

(2 comments)

File src/soc/amd/common/psp_verstage/psp_verstage.c:

https://review.coreboot.org/c/coreboot/+/58870/comment/a5e7e129_d039bf53 
PS5, Line 230: 	verstage_mainboard_s0i3_init();
> I think some additional GPIOs(eg. WLAN_AUX_REST_L) are re-initialized in ramstage. […]

Sure, but would it hurt to just initialize them the same as the normal boot path? I'd just recommend not creating more special cases than necessary.

File src/vendorcode/google/chromeos/Kconfig:

https://review.coreboot.org/c/coreboot/+/58870/comment/1a293779_cb481d5e 
PS3, Line 47: 	depends on TPM2 && RESUME_PATH_SAME_AS_BOOT
> Another option is to broaden RESUME_PATH_SAME_AS_BOOT depends to be ACPI_RESUME || PSP_INIT_TPM_ON_S […]

BTW, didn't see this discussion earlier, but as I understand it you're not running through ramstage on resume with this, right? So chromeos/tpm2.c doesn't do anything for you anyway and this question is pretty moot (that's why you had to add another tlcl_disable_platform_hierarchy() in this patch explicitly instead).