KOUAM Ledoux has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43887 )
Change subject: src: cast void *cbmem_top_chipset() functions to uintptr_t ......................................................................
src: cast void *cbmem_top_chipset() functions to uintptr_t
Cast all void *cbmem_top_chipset() to uintptr_t to avoid redondances.
Change-Id: I1cd637696b9437d56de241a371972779e68863aa Signed-off-by: kouamdo kouamdoux@gmail.com --- M src/cpu/ti/am335x/cbmem.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 35 files changed, 92 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43887/1
diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c index 3765874..8b487b4 100644 --- a/src/cpu/ti/am335x/cbmem.c +++ b/src/cpu/ti/am335x/cbmem.c @@ -2,8 +2,9 @@
#include <cbmem.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { return _dram + (CONFIG_DRAM_SIZE_MB << 20); } diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 29423ef..44d2feb 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -14,6 +14,7 @@ #include <timestamp.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/state_machine.h> +#include <stdint.h>
void __weak board_BeforeAgesa(struct sysinfo *cb) { }
@@ -108,8 +109,8 @@ romstage_main(); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of CBMEM is at highest usable DRAM address below 4GiB. */ - return (void *)restore_top_of_low_cacheable(); + return (uintptr_t)restore_top_of_low_cacheable(); } diff --git a/src/drivers/intel/fsp2_0/cbmem.c b/src/drivers/intel/fsp2_0/cbmem.c index 0efb462..a942e8a 100644 --- a/src/drivers/intel/fsp2_0/cbmem.c +++ b/src/drivers/intel/fsp2_0/cbmem.c @@ -2,11 +2,12 @@
#include <cbmem.h> #include <fsp/util.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { struct range_entry tolum;
fsp_find_bootloader_tolum(&tolum); - return (void *)(uintptr_t)range_entry_end(&tolum); + return (uintptr_t)range_entry_end(&tolum); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b548cd9..5b07927 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -65,7 +65,7 @@ * in the _cbmem_top_ptr symbol. Without CONFIG_RAMSTAGE_CBMEM_TOP_ARG the same * implementation as used in romstage will be used. */ -void *cbmem_top_chipset(void); +uintptr_t cbmem_top_chipset(void);
/* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original diff --git a/src/mainboard/emulation/qemu-aarch64/cbmem.c b/src/mainboard/emulation/qemu-aarch64/cbmem.c index fee2a36..8b34208 100644 --- a/src/mainboard/emulation/qemu-aarch64/cbmem.c +++ b/src/mainboard/emulation/qemu-aarch64/cbmem.c @@ -7,8 +7,9 @@ #include <cbmem.h> #include <ramdetect.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c index 157e443..4006d6a 100644 --- a/src/mainboard/emulation/qemu-armv7/cbmem.c +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -3,8 +3,9 @@ #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); } diff --git a/src/mainboard/emulation/qemu-i440fx/memmap.c b/src/mainboard/emulation/qemu-i440fx/memmap.c index b30b381..b3c1a37 100644 --- a/src/mainboard/emulation/qemu-i440fx/memmap.c +++ b/src/mainboard/emulation/qemu-i440fx/memmap.c @@ -40,7 +40,7 @@ return tomk; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top = 0;
@@ -50,7 +50,7 @@ top = (uintptr_t)qemu_get_memory_size() * 1024; }
- return (void *)top; + return top; }
/* Nothing to do, MTRRs are no-op on QEMU. */ diff --git a/src/mainboard/emulation/qemu-power8/cbmem.c b/src/mainboard/emulation/qemu-power8/cbmem.c index 15c20f8..ecf29c1 100644 --- a/src/mainboard/emulation/qemu-power8/cbmem.c +++ b/src/mainboard/emulation/qemu-power8/cbmem.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ /* For now, last 1M of 4G */ void *ptr = (void *) ((1ULL << 32) - 1048576); - return ptr; + return (uintptr_t)ptr; } diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index b1ac3d1..4eca0b9 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -9,8 +9,9 @@ #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "e7505.h" +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { const pci_devfn_t mch = PCI_DEV(0, 0, 0); uintptr_t tolm; @@ -19,7 +20,7 @@ tolm = pci_read_config16(mch, TOLM) >> 11; tolm <<= 27;
- return (void *)tolm; + return tolm; }
void northbridge_write_smram(u8 smram); diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 4fe3998..8c7bdb8 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -103,10 +103,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index a86efeb..89502ff 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
/* Use simple device model for this file even in ramstage */ +#include <stdint.h> #define __SIMPLE_DEVICE__
#include <arch/romstage.h> @@ -21,9 +22,9 @@ return tom & ~((1 << 20) - 1); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)smm_region_start(); + return (uintptr_t)smm_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index b6d9526..bf35217 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -6,9 +6,10 @@ #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> +#include <stdint.h> #include "i440bx.h"
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Base of TSEG is top of usable DRAM */ /* @@ -48,7 +49,7 @@ int tseg_size = 128 * KiB * (1 << (tseg >> 1)); tom -= tseg_size; } - return (void *)tom; + return (uintptr_t)tom; }
void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index c92e466..27cb383 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -58,10 +58,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; }
/* Decodes used Graphics Mode Select (GMS) to kilobytes. */ diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index 406b9a9..1584427 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h> #define __SIMPLE_DEVICE__
#include <arch/romstage.h> @@ -28,9 +29,9 @@ return CONFIG_SMM_TSEG_SIZE; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return smm_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index ad89aef..0504b06 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -114,9 +114,9 @@ * Depending of UMA and TSEG configuration, TSEG might start at any 1 MiB alignment. * As this may cause very greedy MTRR setup, push CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB); + return ALIGN_DOWN(northbridge_get_tseg_base(), 4 * MiB);
}
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 8da4ec9..31828ab 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <stdint.h> #define __SIMPLE_DEVICE__
#include <arch/romstage.h> @@ -16,10 +17,9 @@ /* Base of TSEG is top of usable DRAM */ return pci_read_config32(HOST_BRIDGE, TSEGMB); } - -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)smm_region_start(); + return (uintptr_t)smm_region_start(); }
static uintptr_t northbridge_get_tseg_base(void) diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index ee1ec5e..1e62ea6 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -113,10 +113,10 @@ * 1 MiB alignment. As this may cause very greedy MTRR setup, push * CBMEM top downwards to 4 MiB boundary. */ -void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB); - return (void *) top_of_ram; + return top_of_ram; }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 67a4319..bdfaf05 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -35,7 +35,7 @@ *size = BERT_REGION_MAX_SIZE; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { msr_t tom = rdmsr(TOP_MEM);
@@ -43,7 +43,7 @@ return 0;
/* 8MB alignment to keep MTRR usage low */ - return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() + return ALIGN_DOWN(restore_top_of_low_cacheable() - CONFIG_SMM_TSEG_SIZE - BERT_REGION_MAX_SIZE, 8*MiB); } diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index d50fe16..bb98dd6 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -4,9 +4,10 @@ #include <soc/addressmap.h> #include <soc/sdram.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* Make sure not to overlap with reserved ATF scratchpad */ - return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); + return ((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB); } diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index aa8e890..9942d03 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -5,6 +5,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <soc/iosf.h> +#include <stdint.h>
static uintptr_t smm_region_start(void) { @@ -16,9 +17,9 @@ return CONFIG_SMM_TSEG_SIZE; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) smm_region_start(); + return smm_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 6cfce43..941d956 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -3,6 +3,7 @@ #include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/iosf.h> +#include <stdint.h>
static size_t smm_region_size(void) { @@ -19,7 +20,7 @@ *size = smm_region_size(); }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { uintptr_t smm_base; size_t smm_size; @@ -53,5 +54,5 @@ */
smm_region(&smm_base, &smm_size); - return (void *)smm_base; + return smm_base; } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index bada5fd..379bd73 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -27,9 +27,9 @@ return tom; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *) dpr_region_start(); + return dpr_region_start(); }
void smm_region(uintptr_t *start, size_t *size) diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c index f9d11e9..b65778e 100644 --- a/src/soc/mediatek/common/cbmem.c +++ b/src/soc/mediatek/common/cbmem.c @@ -4,10 +4,11 @@ #include <commonlib/helpers.h> #include <symbols.h> #include <soc/emi.h> +#include <stdint.h>
#define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); + return MIN((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c index 3f59f06..984fa09 100644 --- a/src/soc/nvidia/tegra124/cbmem.c +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -3,8 +3,9 @@ #include <cbmem.h> #include <soc/display.h> #include <soc/sdram.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); + return ((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL); } diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c index d9b2226..1c8b139 100644 --- a/src/soc/nvidia/tegra210/cbmem.c +++ b/src/soc/nvidia/tegra210/cbmem.c @@ -2,8 +2,9 @@
#include <cbmem.h> #include <soc/addressmap.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { static uintptr_t addr;
@@ -19,5 +20,5 @@ addr = end_mib << 20; }
- return (void *)addr; + return addr; } diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c index 0ee9f9a..860a3c1 100644 --- a/src/soc/qualcomm/ipq40xx/cbmem.c +++ b/src/soc/qualcomm/ipq40xx/cbmem.c @@ -2,6 +2,7 @@
#include <cbmem.h> #include <soc/soc_services.h> +#include <stdint.h>
static int cbmem_backing_store_ready;
@@ -10,7 +11,7 @@ cbmem_backing_store_ready = 1; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -21,5 +22,5 @@ if (cbmem_backing_store_ready == 0) return NULL;
- return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index a695cf8..98c64ed6 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -2,6 +2,7 @@
#include <cbmem.h> #include <soc/soc_services.h> +#include <stdint.h>
static int cbmem_backing_store_ready;
@@ -10,7 +11,7 @@ cbmem_backing_store_ready = 1; }
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { /* * In romstage, make sure that cbmem backing store is ready before @@ -22,5 +23,5 @@ if (cbmem_backing_store_ready == 0) return NULL;
- return _memlayout_cbmem_top; + return (uintptr_t)_memlayout_cbmem_top; } diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c index 97ba38b..38c92e89 100644 --- a/src/soc/qualcomm/qcs405/cbmem.c +++ b/src/soc/qualcomm/qcs405/cbmem.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)3 * GiB); + return ((uintptr_t)3 * GiB); } diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c index 4b9eb37..cfddf3c 100644 --- a/src/soc/qualcomm/sc7180/cbmem.c +++ b/src/soc/qualcomm/sc7180/cbmem.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return ((uintptr_t)4 * GiB); } diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c index 4b9eb37..cfddf3c 100644 --- a/src/soc/qualcomm/sdm845/cbmem.c +++ b/src/soc/qualcomm/sdm845/cbmem.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)((uintptr_t)4 * GiB); + return ((uintptr_t)4 * GiB); } diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c index 5650114..fc5eeb3 100644 --- a/src/soc/rockchip/common/cbmem.c +++ b/src/soc/rockchip/common/cbmem.c @@ -5,9 +5,10 @@ #include <soc/addressmap.h> #include <soc/sdram.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, MAX_DRAM_ADDRESS); } diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c index 167bd80..61ca02c 100644 --- a/src/soc/samsung/exynos5250/cbmem.c +++ b/src/soc/samsung/exynos5250/cbmem.c @@ -2,8 +2,9 @@
#include <cbmem.h> #include <soc/cpu.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return (get_fb_base_kb() * KiB); } diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c index 167bd80..61ca02c 100644 --- a/src/soc/samsung/exynos5420/cbmem.c +++ b/src/soc/samsung/exynos5420/cbmem.c @@ -2,8 +2,9 @@
#include <cbmem.h> #include <soc/cpu.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)(get_fb_base_kb() * KiB); + return (get_fb_base_kb() * KiB); } diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c index af04130..c59940d 100644 --- a/src/soc/sifive/fu540/cbmem.c +++ b/src/soc/sifive/fu540/cbmem.c @@ -5,9 +5,10 @@ #include <soc/addressmap.h> #include <soc/sdram.h> #include <symbols.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { - return (void *)MIN((uintptr_t)_dram + sdram_size_mb() * MiB, + return MIN((uintptr_t)_dram + sdram_size_mb() * MiB, FU540_MAXDRAM); } diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c index 157e443..4006d6a 100644 --- a/src/soc/ucb/riscv/cbmem.c +++ b/src/soc/ucb/riscv/cbmem.c @@ -3,8 +3,9 @@ #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> +#include <stdint.h>
-void *cbmem_top_chipset(void) +uintptr_t cbmem_top_chipset(void) { return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB); }
Hello build bot (Jenkins), Philipp Hug, Damien Zammit, Julius Werner, Andrey Petrov, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43887
to look at the new patch set (#2).
Change subject: src: cast cbmem_top_chipset functions to uintptr_t ......................................................................
src: cast cbmem_top_chipset functions to uintptr_t
Cast all cbmem_top_chipset to avoid redondances.
Change-Id: I1cd637696b9437d56de241a371972779e68863aa Signed-off-by: kouamdo kouamdoux@gmail.com --- M src/cpu/ti/am335x/cbmem.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 35 files changed, 92 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43887/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43887 )
Change subject: src: cast cbmem_top_chipset functions to uintptr_t ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43887/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43887/1//COMMIT_MSG@9 PS1, Line 9: redondances ?
Hello build bot (Jenkins), Philipp Hug, Damien Zammit, Angel Pons, Julius Werner, Andrey Petrov, Aaron Durbin, Patrick Rudolph, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43887
to look at the new patch set (#3).
Change subject: src: cast cbmem_top_chipset functions to uintptr_t ......................................................................
src: cast cbmem_top_chipset functions to uintptr_t
Cast all cbmem_top_chipset to avoid making lots of casts in the coreboot tree
Change-Id: I1cd637696b9437d56de241a371972779e68863aa Signed-off-by: kouamdo kouamdoux@gmail.com --- M src/cpu/ti/am335x/cbmem.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp2_0/cbmem.c M src/include/cbmem.h M src/mainboard/emulation/qemu-aarch64/cbmem.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-i440fx/memmap.c M src/mainboard/emulation/qemu-power8/cbmem.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/stoneyridge/memmap.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/braswell/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/mediatek/common/cbmem.c M src/soc/nvidia/tegra124/cbmem.c M src/soc/nvidia/tegra210/cbmem.c M src/soc/qualcomm/ipq40xx/cbmem.c M src/soc/qualcomm/ipq806x/cbmem.c M src/soc/qualcomm/qcs405/cbmem.c M src/soc/qualcomm/sc7180/cbmem.c M src/soc/qualcomm/sdm845/cbmem.c M src/soc/rockchip/common/cbmem.c M src/soc/samsung/exynos5250/cbmem.c M src/soc/samsung/exynos5420/cbmem.c M src/soc/sifive/fu540/cbmem.c M src/soc/ucb/riscv/cbmem.c 35 files changed, 92 insertions(+), 66 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/43887/3
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43887 )
Change subject: src: cast cbmem_top_chipset functions to uintptr_t ......................................................................
Patch Set 3:
you already started this change : https://review.coreboot.org/c/coreboot/+/43756 , so please keep using it.
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43887 )
Change subject: src: cast cbmem_top_chipset functions to uintptr_t ......................................................................
Patch Set 3:
please dop this one and keep using the old one you started Thx
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43887 )
Change subject: src: cast cbmem_top_chipset functions to uintptr_t ......................................................................
Patch Set 3:
Patch Set 3:
please dop this one and keep using the old one you started Thx
drop*
KOUAM Ledoux has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43887 )
Change subject: src: cast cbmem_top_chipset functions to uintptr_t ......................................................................
Abandoned
-
HAOUAS Elyes (Code Review) -
KOUAM Ledoux (Code Review)
-
Michael Niewöhner (Code Review)