Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56826 )
Change subject: mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe Slot ......................................................................
mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe Slot
Keep the clock source for PCIe slots as always on. Also turn off the unused (0/1/5/6) clock sources. Currently bilby only uses clock sources 2, 3 and 4, out of which clock source 3 and 4 are routed for PCIe external slot. And clock source 2 is routed for M.2 PCIe slot.
TEST:Verify end devices enumerate on D:F 1.1/1.2 RPs over warm reboot.
Signed-off-by: Aamir Bohra aamirbohra@gmail.com Change-Id: Ida485b06279b0a8659c8d00873c3d6023d1e542f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56826 Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/amd/bilby/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 2d55a44..7073aee 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -137,13 +137,13 @@ }"
# genral purpose PCIe clock output configuration - register "gpp_clk_config[0]" = "GPP_CLK_REQ" - register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[0]" = "GPP_CLK_OFF" + register "gpp_clk_config[1]" = "GPP_CLK_OFF" register "gpp_clk_config[2]" = "GPP_CLK_REQ" - register "gpp_clk_config[3]" = "GPP_CLK_REQ" - register "gpp_clk_config[4]" = "GPP_CLK_REQ" - register "gpp_clk_config[5]" = "GPP_CLK_REQ" - register "gpp_clk_config[6]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_ON" + register "gpp_clk_config[4]" = "GPP_CLK_ON" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF"
register "pspp_policy" = "DXIO_PSPP_BALANCED"