Patch set updated for coreboot: 8c2df51 Jetway NF81-T56N-LF: Bump size of ROM found on board.
Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4811
-gerrit
commit 8c2df51e6bd2ce3e65c9b3555f8e613d99209b93 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Sun Jan 26 11:45:30 2014 +1100
Jetway NF81-T56N-LF: Bump size of ROM found on board.
Clean up vendor code from hard coded #define if-def chain with a pre-processor shift and subtract.
Change-Id: Ibce34ab576d7db8586a6ec8f9b2460268e0e1878 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/amd/persimmon/platform_cfg.h | 28 +++++------------------- src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 28 +++++------------------- 2 files changed, 12 insertions(+), 44 deletions(-)
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 0578e27..f084b2f 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -22,31 +22,15 @@ #define _PLATFORM_CFG_H_
/** - * @def BIOS_SIZE_1M - * @def BIOS_SIZE_2M - * @def BIOS_SIZE_4M - * @def BIOS_SIZE_8M - */ -#define BIOS_SIZE_1M 0 -#define BIOS_SIZE_2M 1 -#define BIOS_SIZE_4M 3 -#define BIOS_SIZE_8M 7 - -/* In SB800, default ROM size is 1M Bytes, if your platform ROM + * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * + * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 - #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 - #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 - #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 - #define BIOS_SIZE BIOS_SIZE_8M -#endif -#endif +#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) +#endif /* BIOS_SIZE */
/** * @def SPREAD_SPECTRUM @@ -270,4 +254,4 @@ static const CODECTBLLIST codec_tablelist[] = */ #define FADT_PM_PROFILE 1
-#endif +#endif /* _PLATFORM_CFG_H_ */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index e638892..ce08bee 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -23,31 +23,15 @@ #define _PLATFORM_CFG_H_
/** - * @def BIOS_SIZE_1M - * @def BIOS_SIZE_2M - * @def BIOS_SIZE_4M - * @def BIOS_SIZE_8M - */ -#define BIOS_SIZE_1M 0 -#define BIOS_SIZE_2M 1 -#define BIOS_SIZE_4M 3 -#define BIOS_SIZE_8M 7 - -/* In SB800, default ROM size is 1M Bytes, if your platform ROM + * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * + * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 - #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 - #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 - #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 - #define BIOS_SIZE BIOS_SIZE_8M -#endif -#endif +#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) +#endif /* BIOS_SIZE */
/** * @def SPREAD_SPECTRUM @@ -273,4 +257,4 @@ static const CODECTBLLIST codec_tablelist[] = */ #define FADT_PM_PROFILE 1
-#endif +#endif /* _PLATFORM_CFG_H_ */
-
Edward O'Callaghan