Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56861 )
Change subject: 3rdparty/intel-microcode: Update submodule to 20210608 release ......................................................................
3rdparty/intel-microcode: Update submodule to 20210608 release
Update submodule pointer to include microcode for TGL and others.
Tested the following still boot:
- galp3-c (WHL-U): sig=0x806eb pf=0x80 revision=0xe9 - oryp5 (CFL-H): sig=0x906ea pf=0x20 revision=0xe9 - gaze15 (CML-H): sig=0xa0652 pf=0x20 revision=0xe9
coreboot reports the revision as -1 from what it actually is. i.e., these should report revision=0xea (and that is what Linux reports). However, this behavior is not new.
Change-Id: I084ba67e8eaf7383f1c05fa5589b63c92ff900b1 Signed-off-by: Tim Crawford tcrawford@system76.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/56861 Reviewed-by: Felix Singer felixsinger@posteo.net Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M 3rdparty/intel-microcode 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Felix Singer: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve
diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 49bb67f..3f97690 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 49bb67f32a2e3e631ba1a9a73da1c52e1cac7fd9 +Subproject commit 3f97690f0da8011f52209b232450a1e5c4f2e1f6