Change in coreboot[master]: amd/stoneyridge: Force PSP command reg settings in bootblock

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22876

Change subject: amd/stoneyridge: Force PSP command reg settings in bootblock
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amd/stoneyridge: Force PSP command reg settings in bootblock

A subsequent patch to the PSP library will rely on the device already
having its PCI command register set to allow memory decoding and
mastering enabled.

Program the command register ahead of loading the SMU FW1 blob in
bootblock.  When the device has not been set up (e.g. when SMU FW
is not selectable), AGESA sets up the device.  As a result, a
similar change is not required before sending the DRAM ready
command.

Change-Id: Id586106751286c4767b5c16ed7e1604523635492
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/stoneyridge/bootblock/bootblock.c
1 file changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22876/1

diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 030c990..9f3827d 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -88,7 +88,7 @@
  */
 static void load_smu_fw1(void)
 {
-	u32 base, limit;
+	u32 base, limit, cmd;

/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
    base =  0x80000000;
@@ -101,6 +101,11 @@
    pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
    pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);

+	/* Enable memory access and master */
+	cmd = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND);
+	cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+	pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, cmd);
+
    psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW, "smu_fw");
 }