Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82609?usp=email )
(
5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/system76/mtl: Add Darter Pro 10 ......................................................................
mb/system76/mtl: Add Darter Pro 10
The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board.
There are 2 variants to differentiate them as they have different keyboards and so use different EC firmware.
- darp10: 16" model with 102 key keyboard - darp10-b: 14" model with 83 key keyboard
Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337 Signed-off-by: Tim Crawford tcrawford@system76.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/82609 Reviewed-by: Martin L Roth gaumless@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/mainboard/system76/mtl/Kconfig A src/mainboard/system76/mtl/Kconfig.name A src/mainboard/system76/mtl/Makefile.mk A src/mainboard/system76/mtl/acpi/backlight.asl A src/mainboard/system76/mtl/acpi/mainboard.asl A src/mainboard/system76/mtl/acpi/sleep.asl A src/mainboard/system76/mtl/board_info.txt A src/mainboard/system76/mtl/bootblock.c A src/mainboard/system76/mtl/cmos.default A src/mainboard/system76/mtl/cmos.layout A src/mainboard/system76/mtl/devicetree.cb A src/mainboard/system76/mtl/dsdt.asl A src/mainboard/system76/mtl/include/mainboard/gpio.h A src/mainboard/system76/mtl/ramstage.c A src/mainboard/system76/mtl/variants/darp10/board.fmd A src/mainboard/system76/mtl/variants/darp10/board_info.txt A src/mainboard/system76/mtl/variants/darp10/data.vbt A src/mainboard/system76/mtl/variants/darp10/gpio.c A src/mainboard/system76/mtl/variants/darp10/gpio_early.c A src/mainboard/system76/mtl/variants/darp10/hda_verb.c A src/mainboard/system76/mtl/variants/darp10/overridetree.cb A src/mainboard/system76/mtl/variants/darp10/ramstage.c A src/mainboard/system76/mtl/variants/darp10/romstage.c 23 files changed, 791 insertions(+), 0 deletions(-)
Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/system76/mtl/Kconfig b/src/mainboard/system76/mtl/Kconfig new file mode 100644 index 0000000..aef8ec3 --- /dev/null +++ b/src/mainboard/system76/mtl/Kconfig @@ -0,0 +1,96 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_SYSTEM76_MTL_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GENERIC_CBFS_SERIAL + select DRIVERS_GENERIC_CBFS_UUID + select DRIVERS_I2C_HID + select EC_SYSTEM76_EC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select PCIEXP_SUPPORT_RESIZABLE_BARS + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_METEORLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_RDRESP_NEED_DELAY + +config BOARD_SYSTEM76_DARP10 + select BOARD_SYSTEM76_MTL_COMMON + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + +config BOARD_SYSTEM76_DARP10_B + select BOARD_SYSTEM76_MTL_COMMON + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + +if BOARD_SYSTEM76_MTL_COMMON + +config MAINBOARD_DIR + default "system76/mtl" + +config VARIANT_DIR + default "darp10" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B + +config OVERRIDE_DEVICETREE + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + default "darp10" if BOARD_SYSTEM76_DARP10 + default "darp10-b" if BOARD_SYSTEM76_DARP10_B + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "Darter Pro" if BOARD_SYSTEM76_DARP10 || BOARD_SYSTEM76_DARP10_B + +config MAINBOARD_VERSION + default "darp10" if BOARD_SYSTEM76_DARP10 + default "darp10-b" if BOARD_SYSTEM76_DARP10_B + +config CMOS_DEFAULT_FILE + default "src/mainboard/$(MAINBOARDDIR)/cmos.default" + +config CONSOLE_POST + default y + +config D3COLD_SUPPORT + default n + +config DIMM_SPD_SIZE + default 1024 + +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/board.fmd" + +config ONBOARD_VGA_IS_PRIMARY + default y + +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + default 36 + +config POST_DEVICE + default n + +config TPM_MEASURED_BOOT + default y + +config UART_FOR_CONSOLE + default 0 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +endif diff --git a/src/mainboard/system76/mtl/Kconfig.name b/src/mainboard/system76/mtl/Kconfig.name new file mode 100644 index 0000000..877f91c --- /dev/null +++ b/src/mainboard/system76/mtl/Kconfig.name @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_SYSTEM76_DARP10 + bool "darp10" + +config BOARD_SYSTEM76_DARP10_B + bool "darp10-b" diff --git a/src/mainboard/system76/mtl/Makefile.mk b/src/mainboard/system76/mtl/Makefile.mk new file mode 100644 index 0000000..d61ee9c --- /dev/null +++ b/src/mainboard/system76/mtl/Makefile.mk @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c diff --git a/src/mainboard/system76/mtl/acpi/backlight.asl b/src/mainboard/system76/mtl/acpi/backlight.asl new file mode 100644 index 0000000..053ce57 --- /dev/null +++ b/src/mainboard/system76/mtl/acpi/backlight.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (22) { + 100, /* default AC */ + 100, /* default Battery */ + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/system76/mtl/acpi/mainboard.asl b/src/mainboard/system76/mtl/acpi/mainboard.asl new file mode 100644 index 0000000..c982a9e --- /dev/null +++ b/src/mainboard/system76/mtl/acpi/mainboard.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#include <ec/system76/ec/acpi/ec.asl> + +Scope (_SB) { + #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } +} diff --git a/src/mainboard/system76/mtl/acpi/sleep.asl b/src/mainboard/system76/mtl/acpi/sleep.asl new file mode 100644 index 0000000..8a2a22c --- /dev/null +++ b/src/mainboard/system76/mtl/acpi/sleep.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External(\TBTS, MethodObj) + +Method(MPTS, 1, Serialized) { + If (CondRefOf(\TBTS)) { + \TBTS() + } +} diff --git a/src/mainboard/system76/mtl/board_info.txt b/src/mainboard/system76/mtl/board_info.txt new file mode 100644 index 0000000..e67d880 --- /dev/null +++ b/src/mainboard/system76/mtl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: System76 +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/mtl/bootblock.c b/src/mainboard/system76/mtl/bootblock.c new file mode 100644 index 0000000..8d06adc --- /dev/null +++ b/src/mainboard/system76/mtl/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/system76/mtl/cmos.default b/src/mainboard/system76/mtl/cmos.default new file mode 100644 index 0000000..0cc5970 --- /dev/null +++ b/src/mainboard/system76/mtl/cmos.default @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +me_state=Disable diff --git a/src/mainboard/system76/mtl/cmos.layout b/src/mainboard/system76/mtl/cmos.layout new file mode 100644 index 0000000..b3df380 --- /dev/null +++ b/src/mainboard/system76/mtl/cmos.layout @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 384 r 0 reserved_memory + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 799 984 diff --git a/src/mainboard/system76/mtl/devicetree.cb b/src/mainboard/system76/mtl/devicetree.cb new file mode 100644 index 0000000..e26a7f07 --- /dev/null +++ b/src/mainboard/system76/mtl/devicetree.cb @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/meteorlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Thermal + register "tcc_offset" = "8" + + device cpu_cluster 0 on end + + device domain 0 on + device ref system_agent on end + device ref igpu on + # DDIA is eDP, TCP2 is HDMI + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + #register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref ioe_shared_sram on end + device ref pmc_shared_sram on end + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + + device ref heci1 on end + device ref soc_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0e01" # AP/EC command + register "gen3_dec" = "0x00fc0f01" # AP/EC debug + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref hda on + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/system76/mtl/dsdt.asl b/src/mainboard/system76/mtl/dsdt.asl new file mode 100644 index 0000000..cf8d58d --- /dev/null +++ b/src/mainboard/system76/mtl/dsdt.asl @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//TODO: HACK FOR MISSING MISCCFG_GPIO_PM_CONFIG_BITS +#include <soc/gpio.h> + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/meteorlake/acpi/southbridge.asl> + #include <soc/intel/meteorlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/mtl/include/mainboard/gpio.h b/src/mainboard/system76/mtl/include/mainboard/gpio.h new file mode 100644 index 0000000..c6393be --- /dev/null +++ b/src/mainboard/system76/mtl/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/system76/mtl/ramstage.c b/src/mainboard/system76/mtl/ramstage.c new file mode 100644 index 0000000..a3b12bb --- /dev/null +++ b/src/mainboard/system76/mtl/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/ramstage.h> + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/system76/mtl/variants/darp10/board.fmd b/src/mainboard/system76/mtl/variants/darp10/board.fmd new file mode 100644 index 0000000..8539c86 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/board.fmd @@ -0,0 +1,13 @@ +FLASH 32M { + SI_DESC 16K + SI_GBE 8K + SI_ME 10640K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/mtl/variants/darp10/board_info.txt b/src/mainboard/system76/mtl/variants/darp10/board_info.txt new file mode 100644 index 0000000..f24f9d9 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/board_info.txt @@ -0,0 +1,2 @@ +Board name: darp10 +Release year: 2024 diff --git a/src/mainboard/system76/mtl/variants/darp10/data.vbt b/src/mainboard/system76/mtl/variants/darp10/data.vbt new file mode 100644 index 0000000..9c2b149 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/data.vbt Binary files differ diff --git a/src/mainboard/system76/mtl/variants/darp10/gpio.c b/src/mainboard/system76/mtl/variants/darp10/gpio.c new file mode 100644 index 0000000..3d57ee2 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/gpio.c @@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), // ESPI_RESET_N + // GPP_A07 missing + // GPP_A08 missing + // GPP_A09 missing + // GPP_A10 missing + PAD_CFG_GPO(GPP_A11, 0, DEEP), // ADDS_CODE + PAD_CFG_GPI(GPP_A12, NONE, DEEP), // WLAN_WAKEUP# + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), // M2_SSD2_RST# + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), // CPU_SWI# (test point) + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_NC(GPP_A17, NONE), // TP_ATTN#_A17 + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), // PMC_I2C_INT + + PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), // TP_ATTN#_B00 + PAD_NC(GPP_B01, NONE), + PAD_NC(GPP_B02, NONE), + PAD_NC(GPP_B03, NONE), + PAD_CFG_GPO(GPP_B04, 0, DEEP), // NO REBOOT strap + PAD_CFG_GPO(GPP_B05, 0, DEEP), // CPU_KBCRST# (test point) + PAD_CFG_GPO(GPP_B06, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_B07, NONE), + PAD_NC(GPP_B08, NONE), + PAD_NC(GPP_B09, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), // HDMI_HPD + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLTRST# + PAD_CFG_GPI(GPP_B14, NONE, DEEP), // Top swap override strap + PAD_CFG_GPI(GPP_B15, NONE, DEEP), // GPP_B15_USB2_OC0_N + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 1, DEEP), // PCH_BT_EN + PAD_CFG_GPO(GPP_B19, 1, DEEP), // WIFI_RF_EN + PAD_NC(GPP_B20, NONE), + PAD_CFG_GPO(GPP_B21, 0, PLTRST), // TCP_RETIMER_FORCE_PWR + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_NF(GPP_C02, NONE, DEEP, NF1), // TLS confidentiality strap + PAD_CFG_NF(GPP_C03, UP_20K, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C04, UP_20K, DEEP, NF1), // SML0_DATA + PAD_CFG_NF(GPP_C05, UP_20K, DEEP, NF1), // eSPI disabled strap + PAD_CFG_NF(GPP_C06, UP_20K, DEEP, NF1), // PMC_I2C_SCL + PAD_CFG_NF(GPP_C07, UP_20K, DEEP, NF1), // PMC_I2C_SDA + PAD_NC(GPP_C08, NONE), + PAD_NC(GPP_C09, NONE), + PAD_NC(GPP_C10, NONE), + PAD_CFG_NF(GPP_C11, NONE, PWROK, NF1), // CPU_LAN_CLKREQ# + PAD_CFG_NF(GPP_C12, NONE, PWROK, NF1), // CPU_CARD_CLKREQ# + PAD_NC(GPP_C13, NONE), + // GPP_C14 missing + PAD_CFG_GPO(GPP_C15, 0, DEEP), // GPP_C15_STRAP + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // TBT_LSX0_TXD + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // TBT_LSX0_RXD + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), // HDMI_CTRLCLK + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), // HDMI_CTRLDATA + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + PAD_CFG_GPO(GPP_D00, 1, DEEP), // SB_BLON + PAD_CFG_GPO(GPP_D01, 1, DEEP), // SSD2_PWR_EN + PAD_CFG_GPO(GPP_D02, 1, DEEP), // M2_SSD1_RST# + PAD_NC(GPP_D03, NONE), + PAD_NC(GPP_D04, NONE), + PAD_CFG_GPO(GPP_D05, 1, DEEP), // SSD1_PWR_EN + PAD_NC(GPP_D06, NONE), + PAD_NC(GPP_D07, NONE), + PAD_NC(GPP_D08, NONE), + PAD_NC(GPP_D09, NONE), + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), // HDA_SDI0 + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_CFG_GPO(GPP_D16, 0, DEEP), // GPIO_SPK_MUTE + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), // HDA_RST# + PAD_NC(GPP_D18, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), // CPU_SSD1_CLKREQ# + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), // CPU_SSD2_CLKREQ# + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), // CPU_WLAN_CLKREQ# + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), + + PAD_NC(GPP_E00, NONE), + _PAD_CFG_STRUCT(GPP_E01, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_CFG_GPI(GPP_E02, NONE, DEEP), // BOARD_ID4 + PAD_CFG_GPI(GPP_E03, NONE, DEEP), // CNVI_WAKE# + PAD_NC(GPP_E04, NONE), + PAD_NC(GPP_E05, NONE), + PAD_CFG_GPO(GPP_E06, 0, DEEP), // JTAG ODT disable strap + PAD_NC(GPP_E07, NONE), + PAD_NC(GPP_E08, NONE), + PAD_CFG_GPI(GPP_E09, NONE, DEEP), // GPP_E9_USB2_OC0_N + PAD_NC(GPP_E10, NONE), + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID6 + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), // VRALERT# + PAD_CFG_GPO(GPP_E17, 0, DEEP), // BOARD_ID5 + // GPP_E18 missing + // GPP_E19 missing + // GPP_E20 missing + // GPP_E21 missing + PAD_CFG_GPO(GPP_E22, 0, DEEP), // DNX_FORCE_RELOAD + + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), // CNVI_RST# + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), // CNVI_CLKREQ + PAD_CFG_GPO(GPP_F06, 0, DEEP), // CNVI_GNSS_PA_BLANKING + PAD_NC(GPP_F07, NONE), + PAD_NC(GPP_F08, NONE), + PAD_CFG_GPI(GPP_F09, NONE, DEEP), // TPM_DET + PAD_NC(GPP_F10, NONE), + PAD_CFG_GPO(GPP_F11, 0, DEEP), // BOARD_ID3 + PAD_NC(GPP_F12, NONE), // I2C_SCL_CODEC + PAD_NC(GPP_F13, NONE), // I2C_SDA_CODEC + PAD_CFG_GPO(GPP_F14, 0, DEEP), // BOARD_ID1 + PAD_CFG_GPO(GPP_F15, 0, DEEP), // BOARD_ID2 + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CPU_CCD_WP# + PAD_NC(GPP_F19, NONE), + PAD_CFG_GPO(GPP_F20, 0, DEEP), // SVID support strap + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + PAD_CFG_GPO(GPP_H00, 0, DEEP), // eSPI flash sharing mode strap + PAD_CFG_GPO(GPP_H01, 0, DEEP), // SPI flash descriptor recovery strap + PAD_NC(GPP_H02, NONE), + // GPP_H03 missing + PAD_CFG_GPO(GPP_H04, 0, DEEP), // CNVI_MFUART2_RXD + PAD_CFG_GPO(GPP_H05, 0, DEEP), // CNVI_MFUART2_TXD + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), // I2C3_SDA (Pantone) + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), // I2C3_SCL (Pantone) + // GPP_H08 (UART0_RXD) configured in bootblock + // GPP_H09 (UART0_TXD) configured in bootblock + PAD_CFG_GPO(GPP_H10, 0, DEEP), + PAD_CFG_GPO(GPP_H11, 0, DEEP), + PAD_CFG_GPO(GPP_H12, 0, DEEP), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + // GPP_H18 missing + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), // PCH_I2C_SCL + + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), // DMIC_CLK_A1 + PAD_NC(GPP_S03, NONE), // DMIC_DATA_A1 + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), + PAD_NC(GPP_S06, NONE), + PAD_NC(GPP_S07, NONE), + + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), // PM_BATLOW# + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), // AC_PRESENT + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), // LAN_WAKEUP# + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), // PWR_BTN# + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), // SUSB#_PCH + PAD_CFG_NF(GPP_V05, UP_20K, DEEP, NF1), // SUSC#_PCH + PAD_CFG_NF(GPP_V06, NATIVE, DEEP, NF1), // SLP_A# + // GPP_V07 missing + PAD_CFG_NF(GPP_V08, UP_20K, DEEP, NF1), // SUS_CLK + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), // SLP_WLAN# + PAD_NC(GPP_V10, NONE), + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), // LANPHYPC + PAD_CFG_GPO(GPP_V12, 0, DEEP), // SLP_LAN# + // GPP_V13 missing + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), // PCIE_WAKE# + // GPP_V15 missing + // GPP_V16 missing + // GPP_V17 missing + // GPP_V18 missing + // GPP_V19 missing + // GPP_V20 missing + // GPP_V21 missing + PAD_NC(GPP_V22, NONE), + PAD_NC(GPP_V23, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/mtl/variants/darp10/gpio_early.c b/src/mainboard/system76/mtl/variants/darp10/gpio_early.c new file mode 100644 index 0000000..f17db26 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), // UART0_RX + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/mtl/variants/darp10/hda_verb.c b/src/mainboard/system76/mtl/variants/darp10/hda_verb.c new file mode 100644 index 0000000..2915f4d --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/hda_verb.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a763, /* Subsystem ID */ + 40, /* Number of entries */ + //AZALIA_SUBVENDOR(0, 0x1558a763), + AZALIA_SUBVENDOR(0, 0x1558a743), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, + 0x0205004a, 0x02042010, 0x02050038, 0x02047909, + 0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82, + 0x05350000, 0x0534201a, 0x05350000, 0x0534201a, + 0x0535001d, 0x05340800, 0x0535001e, 0x05340800, + 0x05350003, 0x05341ec4, 0x05350004, 0x05340000, + 0x05450000, 0x05442000, 0x0545001d, 0x05440800, + 0x0545001e, 0x05440800, 0x05450003, 0x05441ec4, + 0x05450004, 0x05440000, 0x05350000, 0x0534a01a, + 0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135, + 0x02050040, 0x02048800, 0x05a50001, 0x05a4001f, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, + 0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390, + 0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00, + 0x00170500, 0x00170500, 0x05a50004, 0x05a40113, + 0x02050008, 0x02046a8c, 0x02050076, 0x0204f000, + 0x0205000e, 0x020465c0, 0x02050033, 0x02048580, + 0x02050069, 0x0204fda8, 0x02050068, 0x02040000, + 0x02050003, 0x02040002, 0x02050069, 0x02040000, + 0x02050068, 0x02040001, 0x0205002e, 0x0204290e, + 0x02236100, 0x02235100, 0x00920011, 0x00970610, + 0x00936000, 0x00935000, 0x0205000d, 0x0204a020, + 0x00220011, 0x00270610, 0x0023a046, 0x00239046, + 0x0173b000, 0x01770740, 0x05a50001, 0x05a4001f, + 0x05c5000f, 0x05c40003, 0x02050036, 0x020437d7, + 0x0143b000, 0x01470740, 0x02050010, 0x02040020, + 0x01470c02, 0x01470c02, + + // XXX: Duplicate last 2 u32s to keep in 4-dword blocks + 0x01470c02, 0x01470c02, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb new file mode 100644 index 0000000..5648739 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/meteorlake + device domain 0 on + subsystemid 0x1558 0xa743 inherit + + device ref tbt_pcie_rp0 on end + device ref tcss_xhci on end + device ref tcss_dma0 on end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* J_AUD1 / AJ_USB3_1 */ + [1] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 */ + [2] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */ + [5] = USB2_PORT_MID(OC_SKIP), /* TBT */ + [6] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_AUD1 / AJ_USB3_1 */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */ + }" + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref pcie_rp5 on + # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING" + device pci 00.0 on end + end + device ref pcie_rp6 on + # Card Reader + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp8 on + # WLAN + register "pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp10 on + # SSD2 + # XXX: Schematics show RP[13:16] used + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp11 on + # SSD1 + # XXX: Schematics show RP[17:20] used + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref hda on + subsystemid 0x1558 0xa763 + end + device ref gbe on end + end +end diff --git a/src/mainboard/system76/mtl/variants/darp10/ramstage.c b/src/mainboard/system76/mtl/variants/darp10/ramstage.c new file mode 100644 index 0000000..2762794 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/ramstage.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // XXX: Enabling C10 reporting causes system to constantly enter and + // exit opportunistic suspend when idle. + params->PchEspiHostC10ReportEnable = 0; +} diff --git a/src/mainboard/system76/mtl/variants/darp10/romstage.c b/src/mainboard/system76/mtl/variants/darp10/romstage.c new file mode 100644 index 0000000..b047f52 --- /dev/null +++ b/src/mainboard/system76/mtl/variants/darp10/romstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +}
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Felix Held (Code Review)