[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71647 )

Change subject: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun
......................................................................

mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun

Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot.

It needs to confirm the PCIe Signal Integrity after enabled.

BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
     the FSP log.

Signed-off-by: Chris.Wang 
Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647
Reviewed-by: Jason Glenesk 
Tested-by: build bot (Jenkins) 
Reviewed-by: Dtrain Hsu 
---
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
1 file changed, 26 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Dtrain Hsu: Looks good to me, approved
  Jason Glenesk: Looks good to me, approved

diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
index 1d50bd5..b4e7c46 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
@@ -99,6 +99,9 @@
    register "stt_skin_temp_apu_F" = "0x3200"

device domain 0 on
+
+		register "dxio_tx_vboost_enable" = "1"
+
    	device ref gpp_bridge_1 on
    		# Required so the NVMe gets placed into D3 when entering S0i3.
    		chip drivers/pcie/rtd3/device