[XS] Change in coreboot[main]: soc/intel/xeon_sp: Support GNR PCIe root ports

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84311?usp=email )

Change subject: soc/intel/xeon_sp: Support GNR PCIe root ports
......................................................................

soc/intel/xeon_sp: Support GNR PCIe root ports

Add device IDs for GNR PCIe root ports so that these devices can
be supported by the Xeon-SP PCIe root port driver.

Change-Id: I450c0088aa2e3be60489becf0600f534ea90d7a4
Signed-off-by: Shuo Liu 
---
M src/soc/intel/xeon_sp/pcie_root_port.c
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/84311/1

diff --git a/src/soc/intel/xeon_sp/pcie_root_port.c b/src/soc/intel/xeon_sp/pcie_root_port.c
index fb9abde..6ecbcec 100644
--- a/src/soc/intel/xeon_sp/pcie_root_port.c
+++ b/src/soc/intel/xeon_sp/pcie_root_port.c
@@ -69,6 +69,14 @@
    0x352c,
    0x352d,
    0x347a,
+	0x0db0,
+	0x0db1,
+	0x0db2,
+	0x0db3,
+	0x0db6,
+	0x0db7,
+	0x0db8,
+	0x0db9,
    0
 };