Change in coreboot[master]: soc/intel/common/block/cpu: Enable ROM caching in ramstage

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62838 )

Change subject: soc/intel/common/block/cpu: Enable ROM caching in ramstage
......................................................................

soc/intel/common/block/cpu: Enable ROM caching in ramstage

This patch ensures to have `BIOS region` and `extended BIOS` region is
cached if the boot device is memory mapped, which is mostly the case
with Intel SoC platform.

Signed-off-by: Subrata Banik 
Change-Id: I02b80eefbb3b19331698a205251a0c4d17be534c
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/62838/1

diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 99d9507..2d838c5 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -152,6 +152,14 @@
    init_cpus();
 }

+static void post_cpus_add_romcache(void)
+{
+	if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
+		return;
+
+	fast_spi_cache_bios_region();
+}
+
 static void wrapper_x86_setup_mtrrs(void *unused)
 {
    x86_setup_mtrrs_with_detect();
@@ -163,6 +171,7 @@
    if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS)
    	printk(BIOS_ERR, "MTRR programming failure\n");

+	post_cpus_add_romcache();
    x86_mtrr_check();
 }