Change in coreboot[master]: soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guards

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35600 )

Change subject: soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guards
......................................................................

soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guards

Change in ssus_disable_internal_pull() is for romcc
compatibility.

Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600
Tested-by: build bot (Jenkins) 
Reviewed-by: Werner Zeh 
---
M src/soc/intel/fsp_baytrail/include/soc/gpio.h
1 file changed, 6 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved

diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
index 68c6235..137ec95 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h
@@ -313,8 +313,6 @@
 #define GPSSUS_GPIO_F1_RANGE_START	11
 #define GPSSUS_GPIO_F1_RANGE_END	21

-#ifndef __BOOTBLOCK__
-
 struct soc_gpio_map {
    u32 pad_conf0;
    u32 pad_conf1;
@@ -360,8 +358,6 @@
 void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
 void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);

-#endif /* #ifndef __BOOTBLOCK__ */
-
 /* Functions / defines for changing GPIOs in romstage */
 /* SCORE Pad definitions. */
 #define UART_RXD_PAD			82
@@ -401,7 +397,6 @@
    write32(pconf0_addr, reg);
 }

-#ifndef __BOOTBLOCK__

/* These functions require that the input pad be configured as an input GPIO */
 static inline int score_get_gpio(int pad)
@@ -436,10 +431,12 @@

static inline void ssus_disable_internal_pull(int pad)
 {
-	const uint32_t pull_mask = ~(0xf << 7);
-	write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask);
-}
+	uint32_t reg;
+	uint32_t *pconf0_addr = ssus_pconf0(pad);

-#endif /* #ifndef __BOOTBLOCK__ */
+	reg = read32(pconf0_addr);
+	reg &= ~(0xf << 7);
+	write32(pconf0_addr, reg);
+}

#endif /* _BAYTRAIL_GPIO_H_ */