Change in coreboot[master]: nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45425 )
Change subject: nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files ......................................................................
nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I457fd753079fb9658d0b89a26003a0e83a32ade0 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/northbridge/intel/x4x/registers/dmibar.h A src/northbridge/intel/x4x/registers/epbar.h A src/northbridge/intel/x4x/registers/mchbar.h M src/northbridge/intel/x4x/x4x.h 4 files changed, 113 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45425/1
diff --git a/src/northbridge/intel/x4x/registers/dmibar.h b/src/northbridge/intel/x4x/registers/dmibar.h new file mode 100644 index 0000000..6fef8d3 --- /dev/null +++ b/src/northbridge/intel/x4x/registers/dmibar.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_DMIBAR_H__ +#define __X4X_REGISTERS_DMIBAR_H__ + +#define DMIVCECH 0x000 /* 32bit */ +#define DMIPVCCAP1 0x004 /* 32bit */ + +#define DMIVC0RCAP 0x010 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ +#define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP (1 << 1) + +#define DMIVC1RCAP 0x01c /* 32bit */ +#define DMIVC1RCTL 0x020 /* 32bit */ +#define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP (1 << 1) + +#define DMIVCPRCAP 0x028 /* 32bit */ +#define DMIVCPRCTL 0x02c /* 32bit */ +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP (1 << 1) + +#define DMIVCMRCAP 0x034 /* 32bit */ +#define DMIVCMRCTL 0x038 /* 32bit */ +#define DMIVCMRSTS 0x03e /* 16bit */ +#define VCMNP (1 << 1) + +#define DMIESD 0x044 /* 32bit */ + +#define DMILE1D 0x050 /* 32bit */ +#define DMILE1A 0x058 /* 64bit */ +#define DMILE2D 0x060 /* 32bit */ +#define DMILE2A 0x068 /* 64bit */ + +#define DMILCAP 0x084 /* 32bit */ +#define DMILCTL 0x088 /* 16bit */ +#define DMILSTS 0x08a /* 16bit */ + +#define DMIUESTS 0x1c4 /* 32bit */ +#define DMICESTS 0x1d0 /* 32bit */ + +#endif /* __X4X_REGISTERS_DMIBAR_H__ */ diff --git a/src/northbridge/intel/x4x/registers/epbar.h b/src/northbridge/intel/x4x/registers/epbar.h new file mode 100644 index 0000000..14ba313 --- /dev/null +++ b/src/northbridge/intel/x4x/registers/epbar.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_EPBAR_H__ +#define __X4X_REGISTERS_EPBAR_H__ + +#define EPPVCCAP1 0x004 /* 32bit */ +#define EPPVCCTL 0x00c /* 32bit */ + +#define EPVC0RCAP 0x010 /* 32bit */ +#define EPVC0RCTL 0x014 /* 32bit */ +#define EPVC0RSTS 0x01a /* 16bit */ + +#define EPVC1RCAP 0x01c /* 32bit */ +#define EPVC1RCTL 0x020 /* 32bit */ +#define EPVC1RSTS 0x026 /* 16bit */ + +#define EPVC1MTS 0x028 /* 32bit */ +#define EPVC1ITC 0x02c /* 32bit */ + +#define EPESD 0x044 /* 32bit */ + +#define EPLE1D 0x050 /* 32bit */ +#define EPLE1A 0x058 /* 64bit */ +#define EPLE2D 0x060 /* 32bit */ +#define EPLE2A 0x068 /* 64bit */ + +#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ + +#endif /* __X4X_REGISTERS_EPBAR_H__ */ diff --git a/src/northbridge/intel/x4x/registers/mchbar.h b/src/northbridge/intel/x4x/registers/mchbar.h new file mode 100644 index 0000000..e44078c --- /dev/null +++ b/src/northbridge/intel/x4x/registers/mchbar.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __X4X_REGISTERS_MCHBAR_H__ +#define __X4X_REGISTERS_MCHBAR_H__ + +#define CHDECMISC 0x111 +#define STACKED_MEM (1 << 1) + +#define C0DRB0 0x200 +#define C0DRB1 0x202 +#define C0DRB2 0x204 +#define C0DRB3 0x206 +#define C0DRA01 0x208 +#define C0DRA23 0x20a +#define C0CKECTRL 0x260 + +#define C1DRB0 0x600 +#define C1DRB1 0x602 +#define C1DRB2 0x604 +#define C1DRB3 0x606 +#define C1DRA01 0x608 +#define C1DRA23 0x60a +#define C1CKECTRL 0x660 + +#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ +#define PMSTS_WARM_RESET (1 << 8) +#define PMSTS_BOTH_SELFREFRESH (3 << 0) + +#define CLKCFG_MCHBAR 0x0c00 +#define CLKCFG_FSBCLK_SHIFT 0 +#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) +#define CLKCFG_MEMCLK_SHIFT 4 +#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) +#define CLKCFG_UPDATE (1 << 12) + +#define SSKPD_MCHBAR 0x0c20 /* 64 bit */ + +#endif /* __X4X_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index ea34fe0..948f5f8 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -57,37 +57,7 @@ #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
-#define CHDECMISC 0x111 -#define STACKED_MEM (1 << 1) - -#define C0DRB0 0x200 -#define C0DRB1 0x202 -#define C0DRB2 0x204 -#define C0DRB3 0x206 -#define C0DRA01 0x208 -#define C0DRA23 0x20a -#define C0CKECTRL 0x260 - -#define C1DRB0 0x600 -#define C1DRB1 0x602 -#define C1DRB2 0x604 -#define C1DRB3 0x606 -#define C1DRA01 0x608 -#define C1DRA23 0x60a -#define C1CKECTRL 0x660 - -#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ -#define PMSTS_WARM_RESET (1 << 8) -#define PMSTS_BOTH_SELFREFRESH (3 << 0) - -#define CLKCFG_MCHBAR 0x0c00 -#define CLKCFG_FSBCLK_SHIFT 0 -#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) -#define CLKCFG_MEMCLK_SHIFT 4 -#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) -#define CLKCFG_UPDATE (1 << 12) - -#define SSKPD_MCHBAR 0x0c20 /* 64 bit */ +#include "registers/mchbar.h"
/* * DMIBAR @@ -97,42 +67,7 @@ #define DMIBAR16(x) (*((volatile u16 *)(DEFAULT_DMIBAR + (x)))) #define DMIBAR32(x) (*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
-#define DMIVCECH 0x000 /* 32bit */ -#define DMIPVCCAP1 0x004 /* 32bit */ - -#define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL 0x014 /* 32bit */ -#define DMIVC0RSTS 0x01a /* 16bit */ -#define VC0NP (1 << 1) - -#define DMIVC1RCAP 0x01c /* 32bit */ -#define DMIVC1RCTL 0x020 /* 32bit */ -#define DMIVC1RSTS 0x026 /* 16bit */ -#define VC1NP (1 << 1) - -#define DMIVCPRCAP 0x028 /* 32bit */ -#define DMIVCPRCTL 0x02c /* 32bit */ -#define DMIVCPRSTS 0x032 /* 16bit */ -#define VCPNP (1 << 1) - -#define DMIVCMRCAP 0x034 /* 32bit */ -#define DMIVCMRCTL 0x038 /* 32bit */ -#define DMIVCMRSTS 0x03e /* 16bit */ -#define VCMNP (1 << 1) - -#define DMIESD 0x044 /* 32bit */ - -#define DMILE1D 0x050 /* 32bit */ -#define DMILE1A 0x058 /* 64bit */ -#define DMILE2D 0x060 /* 32bit */ -#define DMILE2A 0x068 /* 64bit */ - -#define DMILCAP 0x084 /* 32bit */ -#define DMILCTL 0x088 /* 16bit */ -#define DMILSTS 0x08a /* 16bit */ - -#define DMIUESTS 0x1c4 /* 32bit */ -#define DMICESTS 0x1d0 /* 32bit */ +#include "registers/dmibar.h"
/* * EPBAR @@ -142,28 +77,7 @@ #define EPBAR16(x) (*((volatile u16 *)(DEFAULT_EPBAR + (x)))) #define EPBAR32(x) (*((volatile u32 *)(DEFAULT_EPBAR + (x))))
-#define EPPVCCAP1 0x004 /* 32bit */ -#define EPPVCCTL 0x00c /* 32bit */ - -#define EPVC0RCAP 0x010 /* 32bit */ -#define EPVC0RCTL 0x014 /* 32bit */ -#define EPVC0RSTS 0x01a /* 16bit */ - -#define EPVC1RCAP 0x01c /* 32bit */ -#define EPVC1RCTL 0x020 /* 32bit */ -#define EPVC1RSTS 0x026 /* 16bit */ - -#define EPVC1MTS 0x028 /* 32bit */ -#define EPVC1ITC 0x02c /* 32bit */ - -#define EPESD 0x044 /* 32bit */ - -#define EPLE1D 0x050 /* 32bit */ -#define EPLE1A 0x058 /* 64bit */ -#define EPLE2D 0x060 /* 32bit */ -#define EPLE2A 0x068 /* 64bit */ - -#define EP_PORTARB(x) (0x100 + 4 * (x)) /* 256bit */ +#include "registers/epbar.h"
void x4x_early_init(void); void x4x_late_init(int s3resume);
Hello Damien Zammit, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45425
to look at the new patch set (#2).
Change subject: nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files ......................................................................
nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: I457fd753079fb9658d0b89a26003a0e83a32ade0 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/northbridge/intel/x4x/registers/dmibar.h A src/northbridge/intel/x4x/registers/epbar.h A src/northbridge/intel/x4x/registers/mchbar.h M src/northbridge/intel/x4x/x4x.h 4 files changed, 113 insertions(+), 89 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45425/2
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/45425 )
Change subject: nb/intel/x4x: Put DMIBAR/EPBAR/MCHBAR registers into separate files ......................................................................
Abandoned
-
Angel Pons (Code Review)