Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Meera Ravindranath. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56881 )
Change subject: mb/intel/adlrvp: Add support for DDR5 MR SKU ......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/intel/adlrvp/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/56881/comment/48ca8ef1_aa7ea708 PS2, Line 63: ADL_P_DDR5_2
Yes, Subrata. Here is the spd hex data - […]
does it make sense to extend the https://review.coreboot.org/c/coreboot/+/56881/2/src/mainboard/intel/adlrvp/... itself to accommodate DRR5 there and rename it to "memory_down_spd_info" from "lp4_lp5_spd_info"(existing)and "mr_ddr5_spd_info" (newly added). Finally add ADL_P_DDR5_2 here below and call `memcfg_init` with memory_down_spd_info as argument? https://review.coreboot.org/c/coreboot/+/56881/2/src/mainboard/intel/adlrvp/...
Also, you could consider to change "ddr4_ddr5_spd_info" to "dimm_module_spd_info" so at high level we have only 2 types of memory topology to handle and as per board id it fall in place ?
Thoughts ?